1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* Assembly Writer Source Fragment *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9/// getMnemonic - This method is automatically generated by tablegen
10/// from the instruction set description.
11std::pair<const char *, uint64_t> AArch64InstPrinter::getMnemonic(const MCInst *MI) {
12
13#ifdef __GNUC__
14#pragma GCC diagnostic push
15#pragma GCC diagnostic ignored "-Woverlength-strings"
16#endif
17 static const char AsmStrs[] = {
18 /* 0 */ "sha1su0\t\0"
19 /* 9 */ "sha512su0\t\0"
20 /* 20 */ "sha256su0\t\0"
21 /* 31 */ "st64bv0\t\0"
22 /* 40 */ "ld1\t\0"
23 /* 45 */ "trn1\t\0"
24 /* 51 */ "zip1\t\0"
25 /* 57 */ "uzp1\t\0"
26 /* 63 */ "dcps1\t\0"
27 /* 70 */ "sm3ss1\t\0"
28 /* 78 */ "st1\t\0"
29 /* 83 */ "sha1su1\t\0"
30 /* 92 */ "sha512su1\t\0"
31 /* 103 */ "sha256su1\t\0"
32 /* 114 */ "sm3partw1\t\0"
33 /* 125 */ "rax1\t\0"
34 /* 131 */ "rev32\t\0"
35 /* 138 */ "ld2\t\0"
36 /* 143 */ "sha512h2\t\0"
37 /* 153 */ "sha256h2\t\0"
38 /* 163 */ "sabal2\t\0"
39 /* 171 */ "uabal2\t\0"
40 /* 179 */ "sqdmlal2\t\0"
41 /* 189 */ "fmlal2\t\0"
42 /* 197 */ "smlal2\t\0"
43 /* 205 */ "umlal2\t\0"
44 /* 213 */ "ssubl2\t\0"
45 /* 221 */ "usubl2\t\0"
46 /* 229 */ "sabdl2\t\0"
47 /* 237 */ "uabdl2\t\0"
48 /* 245 */ "saddl2\t\0"
49 /* 253 */ "uaddl2\t\0"
50 /* 261 */ "sshll2\t\0"
51 /* 269 */ "ushll2\t\0"
52 /* 277 */ "sqdmull2\t\0"
53 /* 287 */ "pmull2\t\0"
54 /* 295 */ "smull2\t\0"
55 /* 303 */ "umull2\t\0"
56 /* 311 */ "sqdmlsl2\t\0"
57 /* 321 */ "fmlsl2\t\0"
58 /* 329 */ "smlsl2\t\0"
59 /* 337 */ "umlsl2\t\0"
60 /* 345 */ "fcvtl2\t\0"
61 /* 353 */ "rsubhn2\t\0"
62 /* 362 */ "raddhn2\t\0"
63 /* 371 */ "sqshrn2\t\0"
64 /* 380 */ "uqshrn2\t\0"
65 /* 389 */ "sqrshrn2\t\0"
66 /* 399 */ "uqrshrn2\t\0"
67 /* 409 */ "trn2\t\0"
68 /* 415 */ "bfcvtn2\t\0"
69 /* 424 */ "sqxtn2\t\0"
70 /* 432 */ "uqxtn2\t\0"
71 /* 440 */ "sqshrun2\t\0"
72 /* 450 */ "sqrshrun2\t\0"
73 /* 461 */ "sqxtun2\t\0"
74 /* 470 */ "fcvtxn2\t\0"
75 /* 479 */ "zip2\t\0"
76 /* 485 */ "uzp2\t\0"
77 /* 491 */ "dcps2\t\0"
78 /* 498 */ "st2\t\0"
79 /* 503 */ "ssubw2\t\0"
80 /* 511 */ "usubw2\t\0"
81 /* 519 */ "saddw2\t\0"
82 /* 527 */ "uaddw2\t\0"
83 /* 535 */ "sm3partw2\t\0"
84 /* 546 */ "ld3\t\0"
85 /* 551 */ "eor3\t\0"
86 /* 557 */ "dcps3\t\0"
87 /* 564 */ "st3\t\0"
88 /* 569 */ "rev64\t\0"
89 /* 576 */ "ld4\t\0"
90 /* 581 */ "st4\t\0"
91 /* 586 */ "setf16\t\0"
92 /* 594 */ "rev16\t\0"
93 /* 601 */ "setf8\t\0"
94 /* 608 */ "sm3tt1a\t\0"
95 /* 617 */ "sm3tt2a\t\0"
96 /* 626 */ "braa\t\0"
97 /* 632 */ "ldraa\t\0"
98 /* 639 */ "blraa\t\0"
99 /* 646 */ "saba\t\0"
100 /* 652 */ "uaba\t\0"
101 /* 658 */ "pacda\t\0"
102 /* 665 */ "ldadda\t\0"
103 /* 673 */ "fadda\t\0"
104 /* 680 */ "autda\t\0"
105 /* 687 */ "pacga\t\0"
106 /* 694 */ "pacia\t\0"
107 /* 701 */ "autia\t\0"
108 /* 708 */ "brka\t\0"
109 /* 714 */ "fcmla\t\0"
110 /* 721 */ "fmla\t\0"
111 /* 727 */ "bfmmla\t\0"
112 /* 735 */ "usmmla\t\0"
113 /* 743 */ "ummla\t\0"
114 /* 750 */ "fnmla\t\0"
115 /* 757 */ "ldsmina\t\0"
116 /* 766 */ "ldumina\t\0"
117 /* 775 */ "brkpa\t\0"
118 /* 782 */ "caspa\t\0"
119 /* 789 */ "swpa\t\0"
120 /* 795 */ "fexpa\t\0"
121 /* 802 */ "ldclra\t\0"
122 /* 810 */ "ldeora\t\0"
123 /* 818 */ "srsra\t\0"
124 /* 825 */ "ursra\t\0"
125 /* 832 */ "ssra\t\0"
126 /* 838 */ "usra\t\0"
127 /* 844 */ "casa\t\0"
128 /* 850 */ "ldseta\t\0"
129 /* 858 */ "frinta\t\0"
130 /* 866 */ "clasta\t\0"
131 /* 874 */ "ldsmaxa\t\0"
132 /* 883 */ "ldumaxa\t\0"
133 /* 892 */ "pacdza\t\0"
134 /* 900 */ "autdza\t\0"
135 /* 908 */ "paciza\t\0"
136 /* 916 */ "autiza\t\0"
137 /* 924 */ "ld1b\t\0"
138 /* 930 */ "ldff1b\t\0"
139 /* 938 */ "ldnf1b\t\0"
140 /* 946 */ "ldnt1b\t\0"
141 /* 954 */ "stnt1b\t\0"
142 /* 962 */ "st1b\t\0"
143 /* 968 */ "sm3tt1b\t\0"
144 /* 977 */ "crc32b\t\0"
145 /* 985 */ "ld2b\t\0"
146 /* 991 */ "st2b\t\0"
147 /* 997 */ "sm3tt2b\t\0"
148 /* 1006 */ "ld3b\t\0"
149 /* 1012 */ "st3b\t\0"
150 /* 1018 */ "ld64b\t\0"
151 /* 1025 */ "st64b\t\0"
152 /* 1032 */ "ld4b\t\0"
153 /* 1038 */ "st4b\t\0"
154 /* 1044 */ "ldaddab\t\0"
155 /* 1053 */ "ldsminab\t\0"
156 /* 1063 */ "lduminab\t\0"
157 /* 1073 */ "swpab\t\0"
158 /* 1080 */ "brab\t\0"
159 /* 1086 */ "ldrab\t\0"
160 /* 1093 */ "blrab\t\0"
161 /* 1100 */ "ldclrab\t\0"
162 /* 1109 */ "ldeorab\t\0"
163 /* 1118 */ "casab\t\0"
164 /* 1125 */ "ldsetab\t\0"
165 /* 1134 */ "ldsmaxab\t\0"
166 /* 1144 */ "ldumaxab\t\0"
167 /* 1154 */ "crc32cb\t\0"
168 /* 1163 */ "sqdecb\t\0"
169 /* 1171 */ "uqdecb\t\0"
170 /* 1179 */ "sqincb\t\0"
171 /* 1187 */ "uqincb\t\0"
172 /* 1195 */ "pacdb\t\0"
173 /* 1202 */ "ldaddb\t\0"
174 /* 1210 */ "autdb\t\0"
175 /* 1217 */ "prfb\t\0"
176 /* 1223 */ "flogb\t\0"
177 /* 1230 */ "pacib\t\0"
178 /* 1237 */ "autib\t\0"
179 /* 1244 */ "brkb\t\0"
180 /* 1250 */ "sabalb\t\0"
181 /* 1258 */ "uabalb\t\0"
182 /* 1266 */ "ldaddalb\t\0"
183 /* 1276 */ "sqdmlalb\t\0"
184 /* 1286 */ "bfmlalb\t\0"
185 /* 1295 */ "smlalb\t\0"
186 /* 1303 */ "umlalb\t\0"
187 /* 1311 */ "ldsminalb\t\0"
188 /* 1322 */ "lduminalb\t\0"
189 /* 1333 */ "swpalb\t\0"
190 /* 1341 */ "ldclralb\t\0"
191 /* 1351 */ "ldeoralb\t\0"
192 /* 1361 */ "casalb\t\0"
193 /* 1369 */ "ldsetalb\t\0"
194 /* 1379 */ "ldsmaxalb\t\0"
195 /* 1390 */ "ldumaxalb\t\0"
196 /* 1401 */ "ssublb\t\0"
197 /* 1409 */ "usublb\t\0"
198 /* 1417 */ "sbclb\t\0"
199 /* 1424 */ "adclb\t\0"
200 /* 1431 */ "sabdlb\t\0"
201 /* 1439 */ "uabdlb\t\0"
202 /* 1447 */ "ldaddlb\t\0"
203 /* 1456 */ "saddlb\t\0"
204 /* 1464 */ "uaddlb\t\0"
205 /* 1472 */ "sshllb\t\0"
206 /* 1480 */ "ushllb\t\0"
207 /* 1488 */ "sqdmullb\t\0"
208 /* 1498 */ "pmullb\t\0"
209 /* 1506 */ "smullb\t\0"
210 /* 1514 */ "umullb\t\0"
211 /* 1522 */ "ldsminlb\t\0"
212 /* 1532 */ "lduminlb\t\0"
213 /* 1542 */ "swplb\t\0"
214 /* 1549 */ "ldclrlb\t\0"
215 /* 1558 */ "ldeorlb\t\0"
216 /* 1567 */ "caslb\t\0"
217 /* 1574 */ "sqdmlslb\t\0"
218 /* 1584 */ "fmlslb\t\0"
219 /* 1592 */ "smlslb\t\0"
220 /* 1600 */ "umlslb\t\0"
221 /* 1608 */ "ldsetlb\t\0"
222 /* 1617 */ "ldsmaxlb\t\0"
223 /* 1627 */ "ldumaxlb\t\0"
224 /* 1637 */ "dmb\t\0"
225 /* 1642 */ "rsubhnb\t\0"
226 /* 1651 */ "raddhnb\t\0"
227 /* 1660 */ "ldsminb\t\0"
228 /* 1669 */ "lduminb\t\0"
229 /* 1678 */ "sqshrnb\t\0"
230 /* 1687 */ "uqshrnb\t\0"
231 /* 1696 */ "sqrshrnb\t\0"
232 /* 1706 */ "uqrshrnb\t\0"
233 /* 1716 */ "sqxtnb\t\0"
234 /* 1724 */ "uqxtnb\t\0"
235 /* 1732 */ "sqshrunb\t\0"
236 /* 1742 */ "sqrshrunb\t\0"
237 /* 1753 */ "sqxtunb\t\0"
238 /* 1762 */ "ld1rob\t\0"
239 /* 1770 */ "brkpb\t\0"
240 /* 1777 */ "swpb\t\0"
241 /* 1783 */ "ld1rqb\t\0"
242 /* 1791 */ "ld1rb\t\0"
243 /* 1798 */ "ldarb\t\0"
244 /* 1805 */ "ldlarb\t\0"
245 /* 1813 */ "ldrb\t\0"
246 /* 1819 */ "ldclrb\t\0"
247 /* 1827 */ "stllrb\t\0"
248 /* 1835 */ "stlrb\t\0"
249 /* 1842 */ "ldeorb\t\0"
250 /* 1850 */ "ldaprb\t\0"
251 /* 1858 */ "ldtrb\t\0"
252 /* 1865 */ "strb\t\0"
253 /* 1871 */ "sttrb\t\0"
254 /* 1878 */ "ldurb\t\0"
255 /* 1885 */ "stlurb\t\0"
256 /* 1893 */ "ldapurb\t\0"
257 /* 1902 */ "sturb\t\0"
258 /* 1909 */ "ldaxrb\t\0"
259 /* 1917 */ "ldxrb\t\0"
260 /* 1924 */ "stlxrb\t\0"
261 /* 1932 */ "stxrb\t\0"
262 /* 1939 */ "ld1sb\t\0"
263 /* 1946 */ "ldff1sb\t\0"
264 /* 1955 */ "ldnf1sb\t\0"
265 /* 1964 */ "ldnt1sb\t\0"
266 /* 1973 */ "casb\t\0"
267 /* 1979 */ "dsb\t\0"
268 /* 1984 */ "isb\t\0"
269 /* 1989 */ "fmsb\t\0"
270 /* 1995 */ "fnmsb\t\0"
271 /* 2002 */ "ld1rsb\t\0"
272 /* 2010 */ "ldrsb\t\0"
273 /* 2017 */ "ldtrsb\t\0"
274 /* 2025 */ "ldursb\t\0"
275 /* 2033 */ "ldapursb\t\0"
276 /* 2043 */ "tsb\t\0"
277 /* 2048 */ "ldsetb\t\0"
278 /* 2056 */ "ssubltb\t\0"
279 /* 2065 */ "cntb\t\0"
280 /* 2071 */ "eortb\t\0"
281 /* 2078 */ "clastb\t\0"
282 /* 2086 */ "sxtb\t\0"
283 /* 2092 */ "uxtb\t\0"
284 /* 2098 */ "fsub\t\0"
285 /* 2104 */ "shsub\t\0"
286 /* 2111 */ "uhsub\t\0"
287 /* 2118 */ "fmsub\t\0"
288 /* 2125 */ "fnmsub\t\0"
289 /* 2133 */ "sqsub\t\0"
290 /* 2140 */ "uqsub\t\0"
291 /* 2147 */ "revb\t\0"
292 /* 2153 */ "ssubwb\t\0"
293 /* 2161 */ "usubwb\t\0"
294 /* 2169 */ "saddwb\t\0"
295 /* 2177 */ "uaddwb\t\0"
296 /* 2185 */ "ldsmaxb\t\0"
297 /* 2194 */ "ldumaxb\t\0"
298 /* 2203 */ "pacdzb\t\0"
299 /* 2211 */ "autdzb\t\0"
300 /* 2219 */ "pacizb\t\0"
301 /* 2227 */ "autizb\t\0"
302 /* 2235 */ "sha1c\t\0"
303 /* 2242 */ "sbc\t\0"
304 /* 2247 */ "adc\t\0"
305 /* 2252 */ "bic\t\0"
306 /* 2257 */ "aesimc\t\0"
307 /* 2265 */ "aesmc\t\0"
308 /* 2272 */ "csinc\t\0"
309 /* 2279 */ "hvc\t\0"
310 /* 2284 */ "svc\t\0"
311 /* 2289 */ "ld1d\t\0"
312 /* 2295 */ "ldff1d\t\0"
313 /* 2303 */ "ldnf1d\t\0"
314 /* 2311 */ "ldnt1d\t\0"
315 /* 2319 */ "stnt1d\t\0"
316 /* 2327 */ "st1d\t\0"
317 /* 2333 */ "ld2d\t\0"
318 /* 2339 */ "st2d\t\0"
319 /* 2345 */ "ld3d\t\0"
320 /* 2351 */ "st3d\t\0"
321 /* 2357 */ "ld4d\t\0"
322 /* 2363 */ "st4d\t\0"
323 /* 2369 */ "fmad\t\0"
324 /* 2375 */ "fnmad\t\0"
325 /* 2382 */ "ftmad\t\0"
326 /* 2389 */ "fabd\t\0"
327 /* 2395 */ "sabd\t\0"
328 /* 2401 */ "uabd\t\0"
329 /* 2407 */ "xpacd\t\0"
330 /* 2414 */ "sqdecd\t\0"
331 /* 2422 */ "uqdecd\t\0"
332 /* 2430 */ "sqincd\t\0"
333 /* 2438 */ "uqincd\t\0"
334 /* 2446 */ "fcadd\t\0"
335 /* 2453 */ "sqcadd\t\0"
336 /* 2461 */ "ldadd\t\0"
337 /* 2468 */ "fadd\t\0"
338 /* 2474 */ "srhadd\t\0"
339 /* 2482 */ "urhadd\t\0"
340 /* 2490 */ "shadd\t\0"
341 /* 2497 */ "uhadd\t\0"
342 /* 2504 */ "fmadd\t\0"
343 /* 2511 */ "fnmadd\t\0"
344 /* 2519 */ "usqadd\t\0"
345 /* 2527 */ "suqadd\t\0"
346 /* 2535 */ "prfd\t\0"
347 /* 2541 */ "nand\t\0"
348 /* 2547 */ "ld1rod\t\0"
349 /* 2555 */ "ld1rqd\t\0"
350 /* 2563 */ "ld1rd\t\0"
351 /* 2570 */ "asrd\t\0"
352 /* 2576 */ "aesd\t\0"
353 /* 2582 */ "cntd\t\0"
354 /* 2588 */ "sm4e\t\0"
355 /* 2594 */ "splice\t\0"
356 /* 2602 */ "facge\t\0"
357 /* 2609 */ "whilege\t\0"
358 /* 2618 */ "fcmge\t\0"
359 /* 2625 */ "cmpge\t\0"
360 /* 2632 */ "fscale\t\0"
361 /* 2640 */ "whilele\t\0"
362 /* 2649 */ "fcmle\t\0"
363 /* 2656 */ "cmple\t\0"
364 /* 2663 */ "fcmne\t\0"
365 /* 2670 */ "ctermne\t\0"
366 /* 2679 */ "cmpne\t\0"
367 /* 2686 */ "frecpe\t\0"
368 /* 2694 */ "urecpe\t\0"
369 /* 2702 */ "fccmpe\t\0"
370 /* 2710 */ "fcmpe\t\0"
371 /* 2717 */ "aese\t\0"
372 /* 2723 */ "pfalse\t\0"
373 /* 2731 */ "frsqrte\t\0"
374 /* 2740 */ "ursqrte\t\0"
375 /* 2749 */ "ptrue\t\0"
376 /* 2756 */ "udf\t\0"
377 /* 2761 */ "bif\t\0"
378 /* 2766 */ "rmif\t\0"
379 /* 2772 */ "scvtf\t\0"
380 /* 2779 */ "ucvtf\t\0"
381 /* 2786 */ "st2g\t\0"
382 /* 2792 */ "stz2g\t\0"
383 /* 2799 */ "subg\t\0"
384 /* 2805 */ "addg\t\0"
385 /* 2811 */ "ldg\t\0"
386 /* 2816 */ "fneg\t\0"
387 /* 2822 */ "sqneg\t\0"
388 /* 2829 */ "csneg\t\0"
389 /* 2836 */ "histseg\t\0"
390 /* 2845 */ "irg\t\0"
391 /* 2850 */ "stg\t\0"
392 /* 2855 */ "stzg\t\0"
393 /* 2861 */ "sha1h\t\0"
394 /* 2868 */ "ld1h\t\0"
395 /* 2874 */ "ldff1h\t\0"
396 /* 2882 */ "ldnf1h\t\0"
397 /* 2890 */ "ldnt1h\t\0"
398 /* 2898 */ "stnt1h\t\0"
399 /* 2906 */ "st1h\t\0"
400 /* 2912 */ "sha512h\t\0"
401 /* 2921 */ "crc32h\t\0"
402 /* 2929 */ "ld2h\t\0"
403 /* 2935 */ "st2h\t\0"
404 /* 2941 */ "ld3h\t\0"
405 /* 2947 */ "st3h\t\0"
406 /* 2953 */ "ld4h\t\0"
407 /* 2959 */ "st4h\t\0"
408 /* 2965 */ "sha256h\t\0"
409 /* 2974 */ "ldaddah\t\0"
410 /* 2983 */ "sqrdcmlah\t\0"
411 /* 2994 */ "sqrdmlah\t\0"
412 /* 3004 */ "ldsminah\t\0"
413 /* 3014 */ "lduminah\t\0"
414 /* 3024 */ "swpah\t\0"
415 /* 3031 */ "ldclrah\t\0"
416 /* 3040 */ "ldeorah\t\0"
417 /* 3049 */ "casah\t\0"
418 /* 3056 */ "ldsetah\t\0"
419 /* 3065 */ "ldsmaxah\t\0"
420 /* 3075 */ "ldumaxah\t\0"
421 /* 3085 */ "crc32ch\t\0"
422 /* 3094 */ "sqdech\t\0"
423 /* 3102 */ "uqdech\t\0"
424 /* 3110 */ "sqinch\t\0"
425 /* 3118 */ "uqinch\t\0"
426 /* 3126 */ "nmatch\t\0"
427 /* 3134 */ "ldaddh\t\0"
428 /* 3142 */ "prfh\t\0"
429 /* 3148 */ "ldaddalh\t\0"
430 /* 3158 */ "ldsminalh\t\0"
431 /* 3169 */ "lduminalh\t\0"
432 /* 3180 */ "swpalh\t\0"
433 /* 3188 */ "ldclralh\t\0"
434 /* 3198 */ "ldeoralh\t\0"
435 /* 3208 */ "casalh\t\0"
436 /* 3216 */ "ldsetalh\t\0"
437 /* 3226 */ "ldsmaxalh\t\0"
438 /* 3237 */ "ldumaxalh\t\0"
439 /* 3248 */ "ldaddlh\t\0"
440 /* 3257 */ "ldsminlh\t\0"
441 /* 3267 */ "lduminlh\t\0"
442 /* 3277 */ "swplh\t\0"
443 /* 3284 */ "ldclrlh\t\0"
444 /* 3293 */ "ldeorlh\t\0"
445 /* 3302 */ "caslh\t\0"
446 /* 3309 */ "ldsetlh\t\0"
447 /* 3318 */ "sqdmulh\t\0"
448 /* 3327 */ "sqrdmulh\t\0"
449 /* 3337 */ "smulh\t\0"
450 /* 3344 */ "umulh\t\0"
451 /* 3351 */ "ldsmaxlh\t\0"
452 /* 3361 */ "ldumaxlh\t\0"
453 /* 3371 */ "ldsminh\t\0"
454 /* 3380 */ "lduminh\t\0"
455 /* 3389 */ "ld1roh\t\0"
456 /* 3397 */ "swph\t\0"
457 /* 3403 */ "ld1rqh\t\0"
458 /* 3411 */ "ld1rh\t\0"
459 /* 3418 */ "ldarh\t\0"
460 /* 3425 */ "ldlarh\t\0"
461 /* 3433 */ "ldrh\t\0"
462 /* 3439 */ "ldclrh\t\0"
463 /* 3447 */ "stllrh\t\0"
464 /* 3455 */ "stlrh\t\0"
465 /* 3462 */ "ldeorh\t\0"
466 /* 3470 */ "ldaprh\t\0"
467 /* 3478 */ "ldtrh\t\0"
468 /* 3485 */ "strh\t\0"
469 /* 3491 */ "sttrh\t\0"
470 /* 3498 */ "ldurh\t\0"
471 /* 3505 */ "stlurh\t\0"
472 /* 3513 */ "ldapurh\t\0"
473 /* 3522 */ "sturh\t\0"
474 /* 3529 */ "ldaxrh\t\0"
475 /* 3537 */ "ldxrh\t\0"
476 /* 3544 */ "stlxrh\t\0"
477 /* 3552 */ "stxrh\t\0"
478 /* 3559 */ "ld1sh\t\0"
479 /* 3566 */ "ldff1sh\t\0"
480 /* 3575 */ "ldnf1sh\t\0"
481 /* 3584 */ "ldnt1sh\t\0"
482 /* 3593 */ "cash\t\0"
483 /* 3599 */ "sqrdmlsh\t\0"
484 /* 3609 */ "ld1rsh\t\0"
485 /* 3617 */ "ldrsh\t\0"
486 /* 3624 */ "ldtrsh\t\0"
487 /* 3632 */ "ldursh\t\0"
488 /* 3640 */ "ldapursh\t\0"
489 /* 3650 */ "ldseth\t\0"
490 /* 3658 */ "cnth\t\0"
491 /* 3664 */ "sxth\t\0"
492 /* 3670 */ "uxth\t\0"
493 /* 3676 */ "revh\t\0"
494 /* 3682 */ "ldsmaxh\t\0"
495 /* 3691 */ "ldumaxh\t\0"
496 /* 3700 */ "xpaci\t\0"
497 /* 3707 */ "whilehi\t\0"
498 /* 3716 */ "punpkhi\t\0"
499 /* 3725 */ "sunpkhi\t\0"
500 /* 3734 */ "uunpkhi\t\0"
501 /* 3743 */ "cmhi\t\0"
502 /* 3749 */ "cmphi\t\0"
503 /* 3756 */ "sli\t\0"
504 /* 3761 */ "gmi\t\0"
505 /* 3766 */ "mvni\t\0"
506 /* 3772 */ "sri\t\0"
507 /* 3777 */ "frinti\t\0"
508 /* 3785 */ "movi\t\0"
509 /* 3791 */ "brk\t\0"
510 /* 3796 */ "movk\t\0"
511 /* 3802 */ "sabal\t\0"
512 /* 3809 */ "uabal\t\0"
513 /* 3816 */ "ldaddal\t\0"
514 /* 3825 */ "sqdmlal\t\0"
515 /* 3834 */ "fmlal\t\0"
516 /* 3841 */ "smlal\t\0"
517 /* 3848 */ "umlal\t\0"
518 /* 3855 */ "ldsminal\t\0"
519 /* 3865 */ "lduminal\t\0"
520 /* 3875 */ "caspal\t\0"
521 /* 3883 */ "swpal\t\0"
522 /* 3890 */ "ldclral\t\0"
523 /* 3899 */ "ldeoral\t\0"
524 /* 3908 */ "casal\t\0"
525 /* 3915 */ "ldsetal\t\0"
526 /* 3924 */ "ldsmaxal\t\0"
527 /* 3934 */ "ldumaxal\t\0"
528 /* 3944 */ "tbl\t\0"
529 /* 3949 */ "smsubl\t\0"
530 /* 3957 */ "umsubl\t\0"
531 /* 3965 */ "ssubl\t\0"
532 /* 3972 */ "usubl\t\0"
533 /* 3979 */ "sabdl\t\0"
534 /* 3986 */ "uabdl\t\0"
535 /* 3993 */ "ldaddl\t\0"
536 /* 4001 */ "smaddl\t\0"
537 /* 4009 */ "umaddl\t\0"
538 /* 4017 */ "saddl\t\0"
539 /* 4024 */ "uaddl\t\0"
540 /* 4031 */ "tcancel\t\0"
541 /* 4040 */ "fcsel\t\0"
542 /* 4047 */ "ftssel\t\0"
543 /* 4055 */ "sqshl\t\0"
544 /* 4062 */ "uqshl\t\0"
545 /* 4069 */ "sqrshl\t\0"
546 /* 4077 */ "uqrshl\t\0"
547 /* 4085 */ "srshl\t\0"
548 /* 4092 */ "urshl\t\0"
549 /* 4099 */ "sshl\t\0"
550 /* 4105 */ "ushl\t\0"
551 /* 4111 */ "sshll\t\0"
552 /* 4118 */ "ushll\t\0"
553 /* 4125 */ "sqdmull\t\0"
554 /* 4134 */ "pmull\t\0"
555 /* 4141 */ "smull\t\0"
556 /* 4148 */ "umull\t\0"
557 /* 4155 */ "ldsminl\t\0"
558 /* 4164 */ "lduminl\t\0"
559 /* 4173 */ "addpl\t\0"
560 /* 4180 */ "caspl\t\0"
561 /* 4187 */ "swpl\t\0"
562 /* 4193 */ "ldclrl\t\0"
563 /* 4201 */ "ldeorl\t\0"
564 /* 4209 */ "casl\t\0"
565 /* 4215 */ "nbsl\t\0"
566 /* 4221 */ "sqdmlsl\t\0"
567 /* 4230 */ "fmlsl\t\0"
568 /* 4237 */ "smlsl\t\0"
569 /* 4244 */ "umlsl\t\0"
570 /* 4251 */ "sysl\t\0"
571 /* 4257 */ "ldsetl\t\0"
572 /* 4265 */ "fcvtl\t\0"
573 /* 4272 */ "fmul\t\0"
574 /* 4278 */ "fnmul\t\0"
575 /* 4285 */ "pmul\t\0"
576 /* 4291 */ "ftsmul\t\0"
577 /* 4299 */ "addvl\t\0"
578 /* 4306 */ "rdvl\t\0"
579 /* 4312 */ "ldsmaxl\t\0"
580 /* 4321 */ "ldumaxl\t\0"
581 /* 4330 */ "sha1m\t\0"
582 /* 4337 */ "sbfm\t\0"
583 /* 4343 */ "ubfm\t\0"
584 /* 4349 */ "prfm\t\0"
585 /* 4355 */ "ldgm\t\0"
586 /* 4361 */ "stgm\t\0"
587 /* 4367 */ "stzgm\t\0"
588 /* 4374 */ "fminnm\t\0"
589 /* 4382 */ "fmaxnm\t\0"
590 /* 4390 */ "dupm\t\0"
591 /* 4396 */ "frintm\t\0"
592 /* 4404 */ "prfum\t\0"
593 /* 4411 */ "bsl1n\t\0"
594 /* 4418 */ "bsl2n\t\0"
595 /* 4425 */ "rsubhn\t\0"
596 /* 4433 */ "raddhn\t\0"
597 /* 4441 */ "fmin\t\0"
598 /* 4447 */ "ldsmin\t\0"
599 /* 4455 */ "ldumin\t\0"
600 /* 4463 */ "brkn\t\0"
601 /* 4469 */ "ccmn\t\0"
602 /* 4475 */ "eon\t\0"
603 /* 4480 */ "sqshrn\t\0"
604 /* 4488 */ "uqshrn\t\0"
605 /* 4496 */ "sqrshrn\t\0"
606 /* 4505 */ "uqrshrn\t\0"
607 /* 4514 */ "orn\t\0"
608 /* 4519 */ "frintn\t\0"
609 /* 4527 */ "bfcvtn\t\0"
610 /* 4535 */ "sqxtn\t\0"
611 /* 4542 */ "uqxtn\t\0"
612 /* 4549 */ "sqshrun\t\0"
613 /* 4558 */ "sqrshrun\t\0"
614 /* 4568 */ "sqxtun\t\0"
615 /* 4576 */ "movn\t\0"
616 /* 4582 */ "fcvtxn\t\0"
617 /* 4590 */ "whilelo\t\0"
618 /* 4599 */ "punpklo\t\0"
619 /* 4608 */ "sunpklo\t\0"
620 /* 4617 */ "uunpklo\t\0"
621 /* 4626 */ "cmplo\t\0"
622 /* 4633 */ "fcmuo\t\0"
623 /* 4640 */ "sha1p\t\0"
624 /* 4647 */ "subp\t\0"
625 /* 4653 */ "sqdecp\t\0"
626 /* 4661 */ "uqdecp\t\0"
627 /* 4669 */ "sqincp\t\0"
628 /* 4677 */ "uqincp\t\0"
629 /* 4685 */ "faddp\t\0"
630 /* 4692 */ "ldp\t\0"
631 /* 4697 */ "bdep\t\0"
632 /* 4703 */ "stgp\t\0"
633 /* 4709 */ "sadalp\t\0"
634 /* 4717 */ "uadalp\t\0"
635 /* 4725 */ "saddlp\t\0"
636 /* 4733 */ "uaddlp\t\0"
637 /* 4741 */ "fccmp\t\0"
638 /* 4748 */ "fcmp\t\0"
639 /* 4754 */ "fminnmp\t\0"
640 /* 4763 */ "fmaxnmp\t\0"
641 /* 4772 */ "ldnp\t\0"
642 /* 4778 */ "fminp\t\0"
643 /* 4785 */ "sminp\t\0"
644 /* 4792 */ "uminp\t\0"
645 /* 4799 */ "stnp\t\0"
646 /* 4805 */ "adrp\t\0"
647 /* 4811 */ "bgrp\t\0"
648 /* 4817 */ "casp\t\0"
649 /* 4823 */ "cntp\t\0"
650 /* 4829 */ "frintp\t\0"
651 /* 4837 */ "stp\t\0"
652 /* 4842 */ "fdup\t\0"
653 /* 4848 */ "swp\t\0"
654 /* 4853 */ "ldaxp\t\0"
655 /* 4860 */ "fmaxp\t\0"
656 /* 4867 */ "smaxp\t\0"
657 /* 4874 */ "umaxp\t\0"
658 /* 4881 */ "ldxp\t\0"
659 /* 4887 */ "stlxp\t\0"
660 /* 4894 */ "stxp\t\0"
661 /* 4900 */ "fcmeq\t\0"
662 /* 4907 */ "ctermeq\t\0"
663 /* 4916 */ "cmpeq\t\0"
664 /* 4923 */ "ld1r\t\0"
665 /* 4929 */ "ld2r\t\0"
666 /* 4935 */ "ld3r\t\0"
667 /* 4941 */ "ld4r\t\0"
668 /* 4947 */ "ldar\t\0"
669 /* 4953 */ "ldlar\t\0"
670 /* 4960 */ "xar\t\0"
671 /* 4965 */ "fsubr\t\0"
672 /* 4972 */ "shsubr\t\0"
673 /* 4980 */ "uhsubr\t\0"
674 /* 4988 */ "sqsubr\t\0"
675 /* 4996 */ "uqsubr\t\0"
676 /* 5004 */ "adr\t\0"
677 /* 5009 */ "ldr\t\0"
678 /* 5014 */ "rdffr\t\0"
679 /* 5021 */ "wrffr\t\0"
680 /* 5028 */ "srshr\t\0"
681 /* 5035 */ "urshr\t\0"
682 /* 5042 */ "sshr\t\0"
683 /* 5048 */ "ushr\t\0"
684 /* 5054 */ "blr\t\0"
685 /* 5059 */ "ldclr\t\0"
686 /* 5066 */ "sqshlr\t\0"
687 /* 5074 */ "uqshlr\t\0"
688 /* 5082 */ "sqrshlr\t\0"
689 /* 5091 */ "uqrshlr\t\0"
690 /* 5100 */ "srshlr\t\0"
691 /* 5108 */ "urshlr\t\0"
692 /* 5116 */ "stllr\t\0"
693 /* 5123 */ "lslr\t\0"
694 /* 5129 */ "stlr\t\0"
695 /* 5135 */ "ldeor\t\0"
696 /* 5142 */ "nor\t\0"
697 /* 5147 */ "ror\t\0"
698 /* 5152 */ "ldapr\t\0"
699 /* 5159 */ "orr\t\0"
700 /* 5164 */ "asrr\t\0"
701 /* 5170 */ "lsrr\t\0"
702 /* 5176 */ "asr\t\0"
703 /* 5181 */ "lsr\t\0"
704 /* 5186 */ "msr\t\0"
705 /* 5191 */ "insr\t\0"
706 /* 5197 */ "ldtr\t\0"
707 /* 5203 */ "str\t\0"
708 /* 5208 */ "sttr\t\0"
709 /* 5214 */ "extr\t\0"
710 /* 5220 */ "ldur\t\0"
711 /* 5226 */ "stlur\t\0"
712 /* 5233 */ "ldapur\t\0"
713 /* 5241 */ "stur\t\0"
714 /* 5247 */ "fdivr\t\0"
715 /* 5254 */ "sdivr\t\0"
716 /* 5261 */ "udivr\t\0"
717 /* 5268 */ "whilewr\t\0"
718 /* 5277 */ "ldaxr\t\0"
719 /* 5284 */ "ldxr\t\0"
720 /* 5290 */ "stlxr\t\0"
721 /* 5297 */ "stxr\t\0"
722 /* 5303 */ "cas\t\0"
723 /* 5308 */ "brkas\t\0"
724 /* 5315 */ "brkpas\t\0"
725 /* 5323 */ "fcvtas\t\0"
726 /* 5331 */ "fabs\t\0"
727 /* 5337 */ "sqabs\t\0"
728 /* 5344 */ "brkbs\t\0"
729 /* 5351 */ "brkpbs\t\0"
730 /* 5359 */ "subs\t\0"
731 /* 5365 */ "sbcs\t\0"
732 /* 5371 */ "adcs\t\0"
733 /* 5377 */ "bics\t\0"
734 /* 5383 */ "adds\t\0"
735 /* 5389 */ "nands\t\0"
736 /* 5396 */ "ptrues\t\0"
737 /* 5404 */ "whilehs\t\0"
738 /* 5413 */ "cmhs\t\0"
739 /* 5419 */ "cmphs\t\0"
740 /* 5426 */ "cls\t\0"
741 /* 5431 */ "whilels\t\0"
742 /* 5440 */ "fmls\t\0"
743 /* 5446 */ "fnmls\t\0"
744 /* 5453 */ "cmpls\t\0"
745 /* 5460 */ "fcvtms\t\0"
746 /* 5468 */ "ins\t\0"
747 /* 5473 */ "brkns\t\0"
748 /* 5480 */ "orns\t\0"
749 /* 5486 */ "fcvtns\t\0"
750 /* 5494 */ "subps\t\0"
751 /* 5501 */ "frecps\t\0"
752 /* 5509 */ "fcvtps\t\0"
753 /* 5517 */ "rdffrs\t\0"
754 /* 5525 */ "mrs\t\0"
755 /* 5530 */ "eors\t\0"
756 /* 5536 */ "nors\t\0"
757 /* 5542 */ "orrs\t\0"
758 /* 5548 */ "frsqrts\t\0"
759 /* 5557 */ "sys\t\0"
760 /* 5562 */ "fcvtzs\t\0"
761 /* 5570 */ "fjcvtzs\t\0"
762 /* 5579 */ "sqdmlalbt\t\0"
763 /* 5590 */ "ssublbt\t\0"
764 /* 5599 */ "saddlbt\t\0"
765 /* 5608 */ "sqdmlslbt\t\0"
766 /* 5619 */ "eorbt\t\0"
767 /* 5626 */ "compact\t\0"
768 /* 5635 */ "wfet\t\0"
769 /* 5641 */ "ret\t\0"
770 /* 5646 */ "ldset\t\0"
771 /* 5653 */ "facgt\t\0"
772 /* 5660 */ "whilegt\t\0"
773 /* 5669 */ "fcmgt\t\0"
774 /* 5676 */ "cmpgt\t\0"
775 /* 5683 */ "rbit\t\0"
776 /* 5689 */ "wfit\t\0"
777 /* 5695 */ "sabalt\t\0"
778 /* 5703 */ "uabalt\t\0"
779 /* 5711 */ "sqdmlalt\t\0"
780 /* 5721 */ "bfmlalt\t\0"
781 /* 5730 */ "smlalt\t\0"
782 /* 5738 */ "umlalt\t\0"
783 /* 5746 */ "ssublt\t\0"
784 /* 5754 */ "usublt\t\0"
785 /* 5762 */ "sbclt\t\0"
786 /* 5769 */ "adclt\t\0"
787 /* 5776 */ "sabdlt\t\0"
788 /* 5784 */ "uabdlt\t\0"
789 /* 5792 */ "saddlt\t\0"
790 /* 5800 */ "uaddlt\t\0"
791 /* 5808 */ "whilelt\t\0"
792 /* 5817 */ "hlt\t\0"
793 /* 5822 */ "sshllt\t\0"
794 /* 5830 */ "ushllt\t\0"
795 /* 5838 */ "sqdmullt\t\0"
796 /* 5848 */ "pmullt\t\0"
797 /* 5856 */ "smullt\t\0"
798 /* 5864 */ "umullt\t\0"
799 /* 5872 */ "fcmlt\t\0"
800 /* 5879 */ "cmplt\t\0"
801 /* 5886 */ "sqdmlslt\t\0"
802 /* 5896 */ "fmlslt\t\0"
803 /* 5904 */ "smlslt\t\0"
804 /* 5912 */ "umlslt\t\0"
805 /* 5920 */ "fcvtlt\t\0"
806 /* 5928 */ "histcnt\t\0"
807 /* 5937 */ "rsubhnt\t\0"
808 /* 5946 */ "raddhnt\t\0"
809 /* 5955 */ "hint\t\0"
810 /* 5961 */ "sqshrnt\t\0"
811 /* 5970 */ "uqshrnt\t\0"
812 /* 5979 */ "sqrshrnt\t\0"
813 /* 5989 */ "uqrshrnt\t\0"
814 /* 5999 */ "bfcvtnt\t\0"
815 /* 6008 */ "sqxtnt\t\0"
816 /* 6016 */ "uqxtnt\t\0"
817 /* 6024 */ "sqshrunt\t\0"
818 /* 6034 */ "sqrshrunt\t\0"
819 /* 6045 */ "sqxtunt\t\0"
820 /* 6054 */ "fcvtxnt\t\0"
821 /* 6063 */ "cdot\t\0"
822 /* 6069 */ "bfdot\t\0"
823 /* 6076 */ "usdot\t\0"
824 /* 6083 */ "sudot\t\0"
825 /* 6090 */ "cnot\t\0"
826 /* 6096 */ "tstart\t\0"
827 /* 6104 */ "fsqrt\t\0"
828 /* 6111 */ "ptest\t\0"
829 /* 6118 */ "ttest\t\0"
830 /* 6125 */ "pfirst\t\0"
831 /* 6133 */ "cmtst\t\0"
832 /* 6140 */ "bfcvt\t\0"
833 /* 6147 */ "ssubwt\t\0"
834 /* 6155 */ "usubwt\t\0"
835 /* 6163 */ "saddwt\t\0"
836 /* 6171 */ "uaddwt\t\0"
837 /* 6179 */ "bext\t\0"
838 /* 6185 */ "pnext\t\0"
839 /* 6192 */ "fcvtau\t\0"
840 /* 6200 */ "sqshlu\t\0"
841 /* 6208 */ "fcvtmu\t\0"
842 /* 6216 */ "fcvtnu\t\0"
843 /* 6224 */ "fcvtpu\t\0"
844 /* 6232 */ "fcvtzu\t\0"
845 /* 6240 */ "st64bv\t\0"
846 /* 6248 */ "faddv\t\0"
847 /* 6255 */ "saddv\t\0"
848 /* 6262 */ "uaddv\t\0"
849 /* 6269 */ "andv\t\0"
850 /* 6275 */ "rev\t\0"
851 /* 6280 */ "fdiv\t\0"
852 /* 6286 */ "sdiv\t\0"
853 /* 6292 */ "udiv\t\0"
854 /* 6298 */ "saddlv\t\0"
855 /* 6306 */ "uaddlv\t\0"
856 /* 6314 */ "fminnmv\t\0"
857 /* 6323 */ "fmaxnmv\t\0"
858 /* 6332 */ "fminv\t\0"
859 /* 6339 */ "sminv\t\0"
860 /* 6346 */ "uminv\t\0"
861 /* 6353 */ "csinv\t\0"
862 /* 6360 */ "fmov\t\0"
863 /* 6366 */ "smov\t\0"
864 /* 6372 */ "umov\t\0"
865 /* 6378 */ "eorv\t\0"
866 /* 6384 */ "fmaxv\t\0"
867 /* 6391 */ "smaxv\t\0"
868 /* 6398 */ "umaxv\t\0"
869 /* 6405 */ "ld1w\t\0"
870 /* 6411 */ "ldff1w\t\0"
871 /* 6419 */ "ldnf1w\t\0"
872 /* 6427 */ "ldnt1w\t\0"
873 /* 6435 */ "stnt1w\t\0"
874 /* 6443 */ "st1w\t\0"
875 /* 6449 */ "crc32w\t\0"
876 /* 6457 */ "ld2w\t\0"
877 /* 6463 */ "st2w\t\0"
878 /* 6469 */ "ld3w\t\0"
879 /* 6475 */ "st3w\t\0"
880 /* 6481 */ "ld4w\t\0"
881 /* 6487 */ "st4w\t\0"
882 /* 6493 */ "ssubw\t\0"
883 /* 6500 */ "usubw\t\0"
884 /* 6507 */ "crc32cw\t\0"
885 /* 6516 */ "sqdecw\t\0"
886 /* 6524 */ "uqdecw\t\0"
887 /* 6532 */ "sqincw\t\0"
888 /* 6540 */ "uqincw\t\0"
889 /* 6548 */ "saddw\t\0"
890 /* 6555 */ "uaddw\t\0"
891 /* 6562 */ "prfw\t\0"
892 /* 6568 */ "ld1row\t\0"
893 /* 6576 */ "ld1rqw\t\0"
894 /* 6584 */ "ld1rw\t\0"
895 /* 6591 */ "whilerw\t\0"
896 /* 6600 */ "ld1sw\t\0"
897 /* 6607 */ "ldff1sw\t\0"
898 /* 6616 */ "ldnf1sw\t\0"
899 /* 6625 */ "ldnt1sw\t\0"
900 /* 6634 */ "ldpsw\t\0"
901 /* 6641 */ "ld1rsw\t\0"
902 /* 6649 */ "ldrsw\t\0"
903 /* 6656 */ "ldtrsw\t\0"
904 /* 6664 */ "ldursw\t\0"
905 /* 6672 */ "ldapursw\t\0"
906 /* 6682 */ "cntw\t\0"
907 /* 6688 */ "sxtw\t\0"
908 /* 6694 */ "uxtw\t\0"
909 /* 6700 */ "revw\t\0"
910 /* 6706 */ "crc32x\t\0"
911 /* 6714 */ "frint32x\t\0"
912 /* 6724 */ "frint64x\t\0"
913 /* 6734 */ "bcax\t\0"
914 /* 6740 */ "fmax\t\0"
915 /* 6746 */ "ldsmax\t\0"
916 /* 6754 */ "ldumax\t\0"
917 /* 6762 */ "tbx\t\0"
918 /* 6767 */ "crc32cx\t\0"
919 /* 6776 */ "index\t\0"
920 /* 6783 */ "clrex\t\0"
921 /* 6790 */ "movprfx\t\0"
922 /* 6799 */ "fmulx\t\0"
923 /* 6806 */ "frecpx\t\0"
924 /* 6814 */ "frintx\t\0"
925 /* 6822 */ "fcvtx\t\0"
926 /* 6829 */ "sm4ekey\t\0"
927 /* 6838 */ "fcpy\t\0"
928 /* 6844 */ "frint32z\t\0"
929 /* 6854 */ "frint64z\t\0"
930 /* 6864 */ "braaz\t\0"
931 /* 6871 */ "blraaz\t\0"
932 /* 6879 */ "brabz\t\0"
933 /* 6886 */ "blrabz\t\0"
934 /* 6894 */ "cbz\t\0"
935 /* 6899 */ "tbz\t\0"
936 /* 6904 */ "clz\t\0"
937 /* 6909 */ "cbnz\t\0"
938 /* 6915 */ "tbnz\t\0"
939 /* 6921 */ "frintz\t\0"
940 /* 6929 */ "movz\t\0"
941 /* 6935 */ ".tlsdesccall \0"
942 /* 6949 */ "# XRay Function Patchable RET.\0"
943 /* 6980 */ "b.\0"
944 /* 6983 */ "# XRay Typed Event Log.\0"
945 /* 7007 */ "# XRay Custom Event Log.\0"
946 /* 7032 */ "# XRay Function Enter.\0"
947 /* 7055 */ "# XRay Tail Call Exit.\0"
948 /* 7078 */ "# XRay Function Exit.\0"
949 /* 7100 */ "hint\t#10\0"
950 /* 7109 */ "hint\t#30\0"
951 /* 7118 */ "hint\t#31\0"
952 /* 7127 */ "hint\t#12\0"
953 /* 7136 */ "hint\t#14\0"
954 /* 7145 */ "hint\t#24\0"
955 /* 7154 */ "hint\t#25\0"
956 /* 7163 */ "hint\t#26\0"
957 /* 7172 */ "hint\t#7\0"
958 /* 7180 */ "hint\t#27\0"
959 /* 7189 */ "hint\t#8\0"
960 /* 7197 */ "hint\t#28\0"
961 /* 7206 */ "hint\t#29\0"
962 /* 7215 */ "LIFETIME_END\0"
963 /* 7228 */ "PSEUDO_PROBE\0"
964 /* 7241 */ "BUNDLE\0"
965 /* 7248 */ "DBG_VALUE\0"
966 /* 7258 */ "DBG_INSTR_REF\0"
967 /* 7272 */ "DBG_LABEL\0"
968 /* 7282 */ "LIFETIME_START\0"
969 /* 7297 */ "eretaa\0"
970 /* 7304 */ "eretab\0"
971 /* 7311 */ "sb\0"
972 /* 7314 */ "xaflag\0"
973 /* 7321 */ "axflag\0"
974 /* 7328 */ "brb\tinj\0"
975 /* 7336 */ "# FEntry call\0"
976 /* 7350 */ "brb\tiall\0"
977 /* 7359 */ "setffr\0"
978 /* 7366 */ "drps\0"
979 /* 7371 */ "eret\0"
980 /* 7376 */ "tcommit\0"
981 /* 7384 */ "cfinv\0"
982};
983#ifdef __GNUC__
984#pragma GCC diagnostic pop
985#endif
986
987 static const uint32_t OpInfo0[] = {
988 0U, // PHI
989 0U, // INLINEASM
990 0U, // INLINEASM_BR
991 0U, // CFI_INSTRUCTION
992 0U, // EH_LABEL
993 0U, // GC_LABEL
994 0U, // ANNOTATION_LABEL
995 0U, // KILL
996 0U, // EXTRACT_SUBREG
997 0U, // INSERT_SUBREG
998 0U, // IMPLICIT_DEF
999 0U, // SUBREG_TO_REG
1000 0U, // COPY_TO_REGCLASS
1001 7249U, // DBG_VALUE
1002 7259U, // DBG_INSTR_REF
1003 7273U, // DBG_LABEL
1004 0U, // REG_SEQUENCE
1005 0U, // COPY
1006 7242U, // BUNDLE
1007 7283U, // LIFETIME_START
1008 7216U, // LIFETIME_END
1009 7229U, // PSEUDO_PROBE
1010 0U, // STACKMAP
1011 7337U, // FENTRY_CALL
1012 0U, // PATCHPOINT
1013 0U, // LOAD_STACK_GUARD
1014 0U, // PREALLOCATED_SETUP
1015 0U, // PREALLOCATED_ARG
1016 0U, // STATEPOINT
1017 0U, // LOCAL_ESCAPE
1018 0U, // FAULTING_OP
1019 0U, // PATCHABLE_OP
1020 7033U, // PATCHABLE_FUNCTION_ENTER
1021 6950U, // PATCHABLE_RET
1022 7079U, // PATCHABLE_FUNCTION_EXIT
1023 7056U, // PATCHABLE_TAIL_CALL
1024 7008U, // PATCHABLE_EVENT_CALL
1025 6984U, // PATCHABLE_TYPED_EVENT_CALL
1026 0U, // ICALL_BRANCH_FUNNEL
1027 0U, // G_ADD
1028 0U, // G_SUB
1029 0U, // G_MUL
1030 0U, // G_SDIV
1031 0U, // G_UDIV
1032 0U, // G_SREM
1033 0U, // G_UREM
1034 0U, // G_AND
1035 0U, // G_OR
1036 0U, // G_XOR
1037 0U, // G_IMPLICIT_DEF
1038 0U, // G_PHI
1039 0U, // G_FRAME_INDEX
1040 0U, // G_GLOBAL_VALUE
1041 0U, // G_EXTRACT
1042 0U, // G_UNMERGE_VALUES
1043 0U, // G_INSERT
1044 0U, // G_MERGE_VALUES
1045 0U, // G_BUILD_VECTOR
1046 0U, // G_BUILD_VECTOR_TRUNC
1047 0U, // G_CONCAT_VECTORS
1048 0U, // G_PTRTOINT
1049 0U, // G_INTTOPTR
1050 0U, // G_BITCAST
1051 0U, // G_FREEZE
1052 0U, // G_INTRINSIC_TRUNC
1053 0U, // G_INTRINSIC_ROUND
1054 0U, // G_INTRINSIC_LRINT
1055 0U, // G_INTRINSIC_ROUNDEVEN
1056 0U, // G_READCYCLECOUNTER
1057 0U, // G_LOAD
1058 0U, // G_SEXTLOAD
1059 0U, // G_ZEXTLOAD
1060 0U, // G_INDEXED_LOAD
1061 0U, // G_INDEXED_SEXTLOAD
1062 0U, // G_INDEXED_ZEXTLOAD
1063 0U, // G_STORE
1064 0U, // G_INDEXED_STORE
1065 0U, // G_ATOMIC_CMPXCHG_WITH_SUCCESS
1066 0U, // G_ATOMIC_CMPXCHG
1067 0U, // G_ATOMICRMW_XCHG
1068 0U, // G_ATOMICRMW_ADD
1069 0U, // G_ATOMICRMW_SUB
1070 0U, // G_ATOMICRMW_AND
1071 0U, // G_ATOMICRMW_NAND
1072 0U, // G_ATOMICRMW_OR
1073 0U, // G_ATOMICRMW_XOR
1074 0U, // G_ATOMICRMW_MAX
1075 0U, // G_ATOMICRMW_MIN
1076 0U, // G_ATOMICRMW_UMAX
1077 0U, // G_ATOMICRMW_UMIN
1078 0U, // G_ATOMICRMW_FADD
1079 0U, // G_ATOMICRMW_FSUB
1080 0U, // G_FENCE
1081 0U, // G_BRCOND
1082 0U, // G_BRINDIRECT
1083 0U, // G_INTRINSIC
1084 0U, // G_INTRINSIC_W_SIDE_EFFECTS
1085 0U, // G_ANYEXT
1086 0U, // G_TRUNC
1087 0U, // G_CONSTANT
1088 0U, // G_FCONSTANT
1089 0U, // G_VASTART
1090 0U, // G_VAARG
1091 0U, // G_SEXT
1092 0U, // G_SEXT_INREG
1093 0U, // G_ZEXT
1094 0U, // G_SHL
1095 0U, // G_LSHR
1096 0U, // G_ASHR
1097 0U, // G_FSHL
1098 0U, // G_FSHR
1099 0U, // G_ICMP
1100 0U, // G_FCMP
1101 0U, // G_SELECT
1102 0U, // G_UADDO
1103 0U, // G_UADDE
1104 0U, // G_USUBO
1105 0U, // G_USUBE
1106 0U, // G_SADDO
1107 0U, // G_SADDE
1108 0U, // G_SSUBO
1109 0U, // G_SSUBE
1110 0U, // G_UMULO
1111 0U, // G_SMULO
1112 0U, // G_UMULH
1113 0U, // G_SMULH
1114 0U, // G_UADDSAT
1115 0U, // G_SADDSAT
1116 0U, // G_USUBSAT
1117 0U, // G_SSUBSAT
1118 0U, // G_USHLSAT
1119 0U, // G_SSHLSAT
1120 0U, // G_SMULFIX
1121 0U, // G_UMULFIX
1122 0U, // G_SMULFIXSAT
1123 0U, // G_UMULFIXSAT
1124 0U, // G_SDIVFIX
1125 0U, // G_UDIVFIX
1126 0U, // G_SDIVFIXSAT
1127 0U, // G_UDIVFIXSAT
1128 0U, // G_FADD
1129 0U, // G_FSUB
1130 0U, // G_FMUL
1131 0U, // G_FMA
1132 0U, // G_FMAD
1133 0U, // G_FDIV
1134 0U, // G_FREM
1135 0U, // G_FPOW
1136 0U, // G_FPOWI
1137 0U, // G_FEXP
1138 0U, // G_FEXP2
1139 0U, // G_FLOG
1140 0U, // G_FLOG2
1141 0U, // G_FLOG10
1142 0U, // G_FNEG
1143 0U, // G_FPEXT
1144 0U, // G_FPTRUNC
1145 0U, // G_FPTOSI
1146 0U, // G_FPTOUI
1147 0U, // G_SITOFP
1148 0U, // G_UITOFP
1149 0U, // G_FABS
1150 0U, // G_FCOPYSIGN
1151 0U, // G_FCANONICALIZE
1152 0U, // G_FMINNUM
1153 0U, // G_FMAXNUM
1154 0U, // G_FMINNUM_IEEE
1155 0U, // G_FMAXNUM_IEEE
1156 0U, // G_FMINIMUM
1157 0U, // G_FMAXIMUM
1158 0U, // G_PTR_ADD
1159 0U, // G_PTRMASK
1160 0U, // G_SMIN
1161 0U, // G_SMAX
1162 0U, // G_UMIN
1163 0U, // G_UMAX
1164 0U, // G_ABS
1165 0U, // G_BR
1166 0U, // G_BRJT
1167 0U, // G_INSERT_VECTOR_ELT
1168 0U, // G_EXTRACT_VECTOR_ELT
1169 0U, // G_SHUFFLE_VECTOR
1170 0U, // G_CTTZ
1171 0U, // G_CTTZ_ZERO_UNDEF
1172 0U, // G_CTLZ
1173 0U, // G_CTLZ_ZERO_UNDEF
1174 0U, // G_CTPOP
1175 0U, // G_BSWAP
1176 0U, // G_BITREVERSE
1177 0U, // G_FCEIL
1178 0U, // G_FCOS
1179 0U, // G_FSIN
1180 0U, // G_FSQRT
1181 0U, // G_FFLOOR
1182 0U, // G_FRINT
1183 0U, // G_FNEARBYINT
1184 0U, // G_ADDRSPACE_CAST
1185 0U, // G_BLOCK_ADDR
1186 0U, // G_JUMP_TABLE
1187 0U, // G_DYN_STACKALLOC
1188 0U, // G_STRICT_FADD
1189 0U, // G_STRICT_FSUB
1190 0U, // G_STRICT_FMUL
1191 0U, // G_STRICT_FDIV
1192 0U, // G_STRICT_FREM
1193 0U, // G_STRICT_FMA
1194 0U, // G_STRICT_FSQRT
1195 0U, // G_READ_REGISTER
1196 0U, // G_WRITE_REGISTER
1197 0U, // G_MEMCPY
1198 0U, // G_MEMMOVE
1199 0U, // G_MEMSET
1200 0U, // G_VECREDUCE_SEQ_FADD
1201 0U, // G_VECREDUCE_SEQ_FMUL
1202 0U, // G_VECREDUCE_FADD
1203 0U, // G_VECREDUCE_FMUL
1204 0U, // G_VECREDUCE_FMAX
1205 0U, // G_VECREDUCE_FMIN
1206 0U, // G_VECREDUCE_ADD
1207 0U, // G_VECREDUCE_MUL
1208 0U, // G_VECREDUCE_AND
1209 0U, // G_VECREDUCE_OR
1210 0U, // G_VECREDUCE_XOR
1211 0U, // G_VECREDUCE_SMAX
1212 0U, // G_VECREDUCE_SMIN
1213 0U, // G_VECREDUCE_UMAX
1214 0U, // G_VECREDUCE_UMIN
1215 0U, // ADDSWrr
1216 0U, // ADDSXrr
1217 0U, // ADDWrr
1218 0U, // ADDXrr
1219 0U, // ADD_ZPZZ_UNDEF_B
1220 0U, // ADD_ZPZZ_UNDEF_D
1221 0U, // ADD_ZPZZ_UNDEF_H
1222 0U, // ADD_ZPZZ_UNDEF_S
1223 0U, // ADD_ZPZZ_ZERO_B
1224 0U, // ADD_ZPZZ_ZERO_D
1225 0U, // ADD_ZPZZ_ZERO_H
1226 0U, // ADD_ZPZZ_ZERO_S
1227 0U, // ADDlowTLS
1228 0U, // ADJCALLSTACKDOWN
1229 0U, // ADJCALLSTACKUP
1230 0U, // AESIMCrrTied
1231 0U, // AESMCrrTied
1232 0U, // ANDSWrr
1233 0U, // ANDSXrr
1234 0U, // ANDWrr
1235 0U, // ANDXrr
1236 0U, // ASRD_ZPZI_ZERO_B
1237 0U, // ASRD_ZPZI_ZERO_D
1238 0U, // ASRD_ZPZI_ZERO_H
1239 0U, // ASRD_ZPZI_ZERO_S
1240 0U, // ASR_ZPZI_UNDEF_B
1241 0U, // ASR_ZPZI_UNDEF_D
1242 0U, // ASR_ZPZI_UNDEF_H
1243 0U, // ASR_ZPZI_UNDEF_S
1244 0U, // ASR_ZPZZ_UNDEF_B
1245 0U, // ASR_ZPZZ_UNDEF_D
1246 0U, // ASR_ZPZZ_UNDEF_H
1247 0U, // ASR_ZPZZ_UNDEF_S
1248 0U, // ASR_ZPZZ_ZERO_B
1249 0U, // ASR_ZPZZ_ZERO_D
1250 0U, // ASR_ZPZZ_ZERO_H
1251 0U, // ASR_ZPZZ_ZERO_S
1252 0U, // BICSWrr
1253 0U, // BICSXrr
1254 0U, // BICWrr
1255 0U, // BICXrr
1256 0U, // BLRNoIP
1257 0U, // BLR_RVMARKER
1258 0U, // BSPv16i8
1259 0U, // BSPv8i8
1260 0U, // CATCHRET
1261 0U, // CLEANUPRET
1262 0U, // CMP_SWAP_128
1263 0U, // CMP_SWAP_16
1264 0U, // CMP_SWAP_32
1265 0U, // CMP_SWAP_64
1266 0U, // CMP_SWAP_8
1267 0U, // CompilerBarrier
1268 0U, // EMITBKEY
1269 0U, // EONWrr
1270 0U, // EONXrr
1271 0U, // EORWrr
1272 0U, // EORXrr
1273 0U, // F128CSEL
1274 0U, // FABD_ZPZZ_ZERO_D
1275 0U, // FABD_ZPZZ_ZERO_H
1276 0U, // FABD_ZPZZ_ZERO_S
1277 0U, // FADD_ZPZZ_UNDEF_D
1278 0U, // FADD_ZPZZ_UNDEF_H
1279 0U, // FADD_ZPZZ_UNDEF_S
1280 0U, // FADD_ZPZZ_ZERO_D
1281 0U, // FADD_ZPZZ_ZERO_H
1282 0U, // FADD_ZPZZ_ZERO_S
1283 0U, // FDIVR_ZPZZ_ZERO_D
1284 0U, // FDIVR_ZPZZ_ZERO_H
1285 0U, // FDIVR_ZPZZ_ZERO_S
1286 0U, // FDIV_ZPZZ_UNDEF_D
1287 0U, // FDIV_ZPZZ_UNDEF_H
1288 0U, // FDIV_ZPZZ_UNDEF_S
1289 0U, // FDIV_ZPZZ_ZERO_D
1290 0U, // FDIV_ZPZZ_ZERO_H
1291 0U, // FDIV_ZPZZ_ZERO_S
1292 0U, // FMAXNM_ZPZZ_UNDEF_D
1293 0U, // FMAXNM_ZPZZ_UNDEF_H
1294 0U, // FMAXNM_ZPZZ_UNDEF_S
1295 0U, // FMAXNM_ZPZZ_ZERO_D
1296 0U, // FMAXNM_ZPZZ_ZERO_H
1297 0U, // FMAXNM_ZPZZ_ZERO_S
1298 0U, // FMAX_ZPZZ_ZERO_D
1299 0U, // FMAX_ZPZZ_ZERO_H
1300 0U, // FMAX_ZPZZ_ZERO_S
1301 0U, // FMINNM_ZPZZ_UNDEF_D
1302 0U, // FMINNM_ZPZZ_UNDEF_H
1303 0U, // FMINNM_ZPZZ_UNDEF_S
1304 0U, // FMINNM_ZPZZ_ZERO_D
1305 0U, // FMINNM_ZPZZ_ZERO_H
1306 0U, // FMINNM_ZPZZ_ZERO_S
1307 0U, // FMIN_ZPZZ_ZERO_D
1308 0U, // FMIN_ZPZZ_ZERO_H
1309 0U, // FMIN_ZPZZ_ZERO_S
1310 0U, // FMOVD0
1311 0U, // FMOVH0
1312 0U, // FMOVS0
1313 0U, // FMULX_ZPZZ_ZERO_D
1314 0U, // FMULX_ZPZZ_ZERO_H
1315 0U, // FMULX_ZPZZ_ZERO_S
1316 0U, // FMUL_ZPZZ_UNDEF_D
1317 0U, // FMUL_ZPZZ_UNDEF_H
1318 0U, // FMUL_ZPZZ_UNDEF_S
1319 0U, // FMUL_ZPZZ_ZERO_D
1320 0U, // FMUL_ZPZZ_ZERO_H
1321 0U, // FMUL_ZPZZ_ZERO_S
1322 0U, // FSUBR_ZPZZ_ZERO_D
1323 0U, // FSUBR_ZPZZ_ZERO_H
1324 0U, // FSUBR_ZPZZ_ZERO_S
1325 0U, // FSUB_ZPZZ_UNDEF_D
1326 0U, // FSUB_ZPZZ_UNDEF_H
1327 0U, // FSUB_ZPZZ_UNDEF_S
1328 0U, // FSUB_ZPZZ_ZERO_D
1329 0U, // FSUB_ZPZZ_ZERO_H
1330 0U, // FSUB_ZPZZ_ZERO_S
1331 0U, // GLD1B_D
1332 0U, // GLD1B_D_IMM
1333 0U, // GLD1B_D_SXTW
1334 0U, // GLD1B_D_UXTW
1335 0U, // GLD1B_S_IMM
1336 0U, // GLD1B_S_SXTW
1337 0U, // GLD1B_S_UXTW
1338 0U, // GLD1D
1339 0U, // GLD1D_IMM
1340 0U, // GLD1D_SCALED
1341 0U, // GLD1D_SXTW
1342 0U, // GLD1D_SXTW_SCALED
1343 0U, // GLD1D_UXTW
1344 0U, // GLD1D_UXTW_SCALED
1345 0U, // GLD1H_D
1346 0U, // GLD1H_D_IMM
1347 0U, // GLD1H_D_SCALED
1348 0U, // GLD1H_D_SXTW
1349 0U, // GLD1H_D_SXTW_SCALED
1350 0U, // GLD1H_D_UXTW
1351 0U, // GLD1H_D_UXTW_SCALED
1352 0U, // GLD1H_S_IMM
1353 0U, // GLD1H_S_SXTW
1354 0U, // GLD1H_S_SXTW_SCALED
1355 0U, // GLD1H_S_UXTW
1356 0U, // GLD1H_S_UXTW_SCALED
1357 0U, // GLD1SB_D
1358 0U, // GLD1SB_D_IMM
1359 0U, // GLD1SB_D_SXTW
1360 0U, // GLD1SB_D_UXTW
1361 0U, // GLD1SB_S_IMM
1362 0U, // GLD1SB_S_SXTW
1363 0U, // GLD1SB_S_UXTW
1364 0U, // GLD1SH_D
1365 0U, // GLD1SH_D_IMM
1366 0U, // GLD1SH_D_SCALED
1367 0U, // GLD1SH_D_SXTW
1368 0U, // GLD1SH_D_SXTW_SCALED
1369 0U, // GLD1SH_D_UXTW
1370 0U, // GLD1SH_D_UXTW_SCALED
1371 0U, // GLD1SH_S_IMM
1372 0U, // GLD1SH_S_SXTW
1373 0U, // GLD1SH_S_SXTW_SCALED
1374 0U, // GLD1SH_S_UXTW
1375 0U, // GLD1SH_S_UXTW_SCALED
1376 0U, // GLD1SW_D
1377 0U, // GLD1SW_D_IMM
1378 0U, // GLD1SW_D_SCALED
1379 0U, // GLD1SW_D_SXTW
1380 0U, // GLD1SW_D_SXTW_SCALED
1381 0U, // GLD1SW_D_UXTW
1382 0U, // GLD1SW_D_UXTW_SCALED
1383 0U, // GLD1W_D
1384 0U, // GLD1W_D_IMM
1385 0U, // GLD1W_D_SCALED
1386 0U, // GLD1W_D_SXTW
1387 0U, // GLD1W_D_SXTW_SCALED
1388 0U, // GLD1W_D_UXTW
1389 0U, // GLD1W_D_UXTW_SCALED
1390 0U, // GLD1W_IMM
1391 0U, // GLD1W_SXTW
1392 0U, // GLD1W_SXTW_SCALED
1393 0U, // GLD1W_UXTW
1394 0U, // GLD1W_UXTW_SCALED
1395 0U, // GLDFF1B_D
1396 0U, // GLDFF1B_D_IMM
1397 0U, // GLDFF1B_D_SXTW
1398 0U, // GLDFF1B_D_UXTW
1399 0U, // GLDFF1B_S_IMM
1400 0U, // GLDFF1B_S_SXTW
1401 0U, // GLDFF1B_S_UXTW
1402 0U, // GLDFF1D
1403 0U, // GLDFF1D_IMM
1404 0U, // GLDFF1D_SCALED
1405 0U, // GLDFF1D_SXTW
1406 0U, // GLDFF1D_SXTW_SCALED
1407 0U, // GLDFF1D_UXTW
1408 0U, // GLDFF1D_UXTW_SCALED
1409 0U, // GLDFF1H_D
1410 0U, // GLDFF1H_D_IMM
1411 0U, // GLDFF1H_D_SCALED
1412 0U, // GLDFF1H_D_SXTW
1413 0U, // GLDFF1H_D_SXTW_SCALED
1414 0U, // GLDFF1H_D_UXTW
1415 0U, // GLDFF1H_D_UXTW_SCALED
1416 0U, // GLDFF1H_S_IMM
1417 0U, // GLDFF1H_S_SXTW
1418 0U, // GLDFF1H_S_SXTW_SCALED
1419 0U, // GLDFF1H_S_UXTW
1420 0U, // GLDFF1H_S_UXTW_SCALED
1421 0U, // GLDFF1SB_D
1422 0U, // GLDFF1SB_D_IMM
1423 0U, // GLDFF1SB_D_SXTW
1424 0U, // GLDFF1SB_D_UXTW
1425 0U, // GLDFF1SB_S_IMM
1426 0U, // GLDFF1SB_S_SXTW
1427 0U, // GLDFF1SB_S_UXTW
1428 0U, // GLDFF1SH_D
1429 0U, // GLDFF1SH_D_IMM
1430 0U, // GLDFF1SH_D_SCALED
1431 0U, // GLDFF1SH_D_SXTW
1432 0U, // GLDFF1SH_D_SXTW_SCALED
1433 0U, // GLDFF1SH_D_UXTW
1434 0U, // GLDFF1SH_D_UXTW_SCALED
1435 0U, // GLDFF1SH_S_IMM
1436 0U, // GLDFF1SH_S_SXTW
1437 0U, // GLDFF1SH_S_SXTW_SCALED
1438 0U, // GLDFF1SH_S_UXTW
1439 0U, // GLDFF1SH_S_UXTW_SCALED
1440 0U, // GLDFF1SW_D
1441 0U, // GLDFF1SW_D_IMM
1442 0U, // GLDFF1SW_D_SCALED
1443 0U, // GLDFF1SW_D_SXTW
1444 0U, // GLDFF1SW_D_SXTW_SCALED
1445 0U, // GLDFF1SW_D_UXTW
1446 0U, // GLDFF1SW_D_UXTW_SCALED
1447 0U, // GLDFF1W_D
1448 0U, // GLDFF1W_D_IMM
1449 0U, // GLDFF1W_D_SCALED
1450 0U, // GLDFF1W_D_SXTW
1451 0U, // GLDFF1W_D_SXTW_SCALED
1452 0U, // GLDFF1W_D_UXTW
1453 0U, // GLDFF1W_D_UXTW_SCALED
1454 0U, // GLDFF1W_IMM
1455 0U, // GLDFF1W_SXTW
1456 0U, // GLDFF1W_SXTW_SCALED
1457 0U, // GLDFF1W_UXTW
1458 0U, // GLDFF1W_UXTW_SCALED
1459 0U, // G_ADD_LOW
1460 0U, // G_DUP
1461 0U, // G_DUPLANE16
1462 0U, // G_DUPLANE32
1463 0U, // G_DUPLANE64
1464 0U, // G_DUPLANE8
1465 0U, // G_EXT
1466 0U, // G_REV16
1467 0U, // G_REV32
1468 0U, // G_REV64
1469 0U, // G_SITOF
1470 0U, // G_TRN1
1471 0U, // G_TRN2
1472 0U, // G_UITOF
1473 0U, // G_UZP1
1474 0U, // G_UZP2
1475 0U, // G_VASHR
1476 0U, // G_VLSHR
1477 0U, // G_ZIP1
1478 0U, // G_ZIP2
1479 0U, // HWASAN_CHECK_MEMACCESS
1480 0U, // HWASAN_CHECK_MEMACCESS_SHORTGRANULES
1481 0U, // IRGstack
1482 0U, // JumpTableDest16
1483 0U, // JumpTableDest32
1484 0U, // JumpTableDest8
1485 0U, // LD1B_D_IMM
1486 0U, // LD1B_H_IMM
1487 0U, // LD1B_IMM
1488 0U, // LD1B_S_IMM
1489 0U, // LD1D_IMM
1490 0U, // LD1H_D_IMM
1491 0U, // LD1H_IMM
1492 0U, // LD1H_S_IMM
1493 0U, // LD1SB_D_IMM
1494 0U, // LD1SB_H_IMM
1495 0U, // LD1SB_S_IMM
1496 0U, // LD1SH_D_IMM
1497 0U, // LD1SH_S_IMM
1498 0U, // LD1SW_D_IMM
1499 0U, // LD1W_D_IMM
1500 0U, // LD1W_IMM
1501 0U, // LDFF1B
1502 0U, // LDFF1B_D
1503 0U, // LDFF1B_H
1504 0U, // LDFF1B_S
1505 0U, // LDFF1D
1506 0U, // LDFF1H
1507 0U, // LDFF1H_D
1508 0U, // LDFF1H_S
1509 0U, // LDFF1SB_D
1510 0U, // LDFF1SB_H
1511 0U, // LDFF1SB_S
1512 0U, // LDFF1SH_D
1513 0U, // LDFF1SH_S
1514 0U, // LDFF1SW_D
1515 0U, // LDFF1W
1516 0U, // LDFF1W_D
1517 0U, // LDNF1B_D_IMM
1518 0U, // LDNF1B_H_IMM
1519 0U, // LDNF1B_IMM
1520 0U, // LDNF1B_S_IMM
1521 0U, // LDNF1D_IMM
1522 0U, // LDNF1H_D_IMM
1523 0U, // LDNF1H_IMM
1524 0U, // LDNF1H_S_IMM
1525 0U, // LDNF1SB_D_IMM
1526 0U, // LDNF1SB_H_IMM
1527 0U, // LDNF1SB_S_IMM
1528 0U, // LDNF1SH_D_IMM
1529 0U, // LDNF1SH_S_IMM
1530 0U, // LDNF1SW_D_IMM
1531 0U, // LDNF1W_D_IMM
1532 0U, // LDNF1W_IMM
1533 0U, // LDR_ZZXI
1534 0U, // LDR_ZZZXI
1535 0U, // LDR_ZZZZXI
1536 0U, // LOADgot
1537 0U, // LSL_ZPZI_UNDEF_B
1538 0U, // LSL_ZPZI_UNDEF_D
1539 0U, // LSL_ZPZI_UNDEF_H
1540 0U, // LSL_ZPZI_UNDEF_S
1541 0U, // LSL_ZPZZ_UNDEF_B
1542 0U, // LSL_ZPZZ_UNDEF_D
1543 0U, // LSL_ZPZZ_UNDEF_H
1544 0U, // LSL_ZPZZ_UNDEF_S
1545 0U, // LSL_ZPZZ_ZERO_B
1546 0U, // LSL_ZPZZ_ZERO_D
1547 0U, // LSL_ZPZZ_ZERO_H
1548 0U, // LSL_ZPZZ_ZERO_S
1549 0U, // LSR_ZPZI_UNDEF_B
1550 0U, // LSR_ZPZI_UNDEF_D
1551 0U, // LSR_ZPZI_UNDEF_H
1552 0U, // LSR_ZPZI_UNDEF_S
1553 0U, // LSR_ZPZZ_UNDEF_B
1554 0U, // LSR_ZPZZ_UNDEF_D
1555 0U, // LSR_ZPZZ_UNDEF_H
1556 0U, // LSR_ZPZZ_UNDEF_S
1557 0U, // LSR_ZPZZ_ZERO_B
1558 0U, // LSR_ZPZZ_ZERO_D
1559 0U, // LSR_ZPZZ_ZERO_H
1560 0U, // LSR_ZPZZ_ZERO_S
1561 0U, // MOVMCSym
1562 0U, // MOVaddr
1563 0U, // MOVaddrBA
1564 0U, // MOVaddrCP
1565 0U, // MOVaddrEXT
1566 0U, // MOVaddrJT
1567 0U, // MOVaddrTLS
1568 0U, // MOVbaseTLS
1569 0U, // MOVi32imm
1570 0U, // MOVi64imm
1571 0U, // MUL_ZPZZ_UNDEF_B
1572 0U, // MUL_ZPZZ_UNDEF_D
1573 0U, // MUL_ZPZZ_UNDEF_H
1574 0U, // MUL_ZPZZ_UNDEF_S
1575 0U, // ORNWrr
1576 0U, // ORNXrr
1577 0U, // ORRWrr
1578 0U, // ORRXrr
1579 0U, // RDFFR_P
1580 0U, // RDFFR_PPz
1581 0U, // RET_ReallyLR
1582 0U, // SDIV_ZPZZ_UNDEF_D
1583 0U, // SDIV_ZPZZ_UNDEF_S
1584 0U, // SEH_AddFP
1585 0U, // SEH_EpilogEnd
1586 0U, // SEH_EpilogStart
1587 0U, // SEH_Nop
1588 0U, // SEH_PrologEnd
1589 0U, // SEH_SaveFPLR
1590 0U, // SEH_SaveFPLR_X
1591 0U, // SEH_SaveFReg
1592 0U, // SEH_SaveFRegP
1593 0U, // SEH_SaveFRegP_X
1594 0U, // SEH_SaveFReg_X
1595 0U, // SEH_SaveReg
1596 0U, // SEH_SaveRegP
1597 0U, // SEH_SaveRegP_X
1598 0U, // SEH_SaveReg_X
1599 0U, // SEH_SetFP
1600 0U, // SEH_StackAlloc
1601 0U, // SMAX_ZPZZ_UNDEF_B
1602 0U, // SMAX_ZPZZ_UNDEF_D
1603 0U, // SMAX_ZPZZ_UNDEF_H
1604 0U, // SMAX_ZPZZ_UNDEF_S
1605 0U, // SMIN_ZPZZ_UNDEF_B
1606 0U, // SMIN_ZPZZ_UNDEF_D
1607 0U, // SMIN_ZPZZ_UNDEF_H
1608 0U, // SMIN_ZPZZ_UNDEF_S
1609 0U, // SPACE
1610 0U, // SQSHLU_ZPZI_ZERO_B
1611 0U, // SQSHLU_ZPZI_ZERO_D
1612 0U, // SQSHLU_ZPZI_ZERO_H
1613 0U, // SQSHLU_ZPZI_ZERO_S
1614 0U, // SQSHL_ZPZI_ZERO_B
1615 0U, // SQSHL_ZPZI_ZERO_D
1616 0U, // SQSHL_ZPZI_ZERO_H
1617 0U, // SQSHL_ZPZI_ZERO_S
1618 0U, // SRSHR_ZPZI_ZERO_B
1619 0U, // SRSHR_ZPZI_ZERO_D
1620 0U, // SRSHR_ZPZI_ZERO_H
1621 0U, // SRSHR_ZPZI_ZERO_S
1622 0U, // STGloop
1623 0U, // STGloop_wback
1624 0U, // STR_ZZXI
1625 0U, // STR_ZZZXI
1626 0U, // STR_ZZZZXI
1627 0U, // STZGloop
1628 0U, // STZGloop_wback
1629 0U, // SUBR_ZPZZ_ZERO_B
1630 0U, // SUBR_ZPZZ_ZERO_D
1631 0U, // SUBR_ZPZZ_ZERO_H
1632 0U, // SUBR_ZPZZ_ZERO_S
1633 0U, // SUBSWrr
1634 0U, // SUBSXrr
1635 0U, // SUBWrr
1636 0U, // SUBXrr
1637 0U, // SUB_ZPZZ_UNDEF_B
1638 0U, // SUB_ZPZZ_UNDEF_D
1639 0U, // SUB_ZPZZ_UNDEF_H
1640 0U, // SUB_ZPZZ_UNDEF_S
1641 0U, // SUB_ZPZZ_ZERO_B
1642 0U, // SUB_ZPZZ_ZERO_D
1643 0U, // SUB_ZPZZ_ZERO_H
1644 0U, // SUB_ZPZZ_ZERO_S
1645 0U, // SpeculationBarrierISBDSBEndBB
1646 0U, // SpeculationBarrierSBEndBB
1647 0U, // SpeculationSafeValueW
1648 0U, // SpeculationSafeValueX
1649 0U, // TAGPstack
1650 0U, // TCRETURNdi
1651 0U, // TCRETURNri
1652 0U, // TCRETURNriALL
1653 0U, // TCRETURNriBTI
1654 15128U, // TLSDESCCALL
1655 0U, // TLSDESC_CALLSEQ
1656 0U, // UDIV_ZPZZ_UNDEF_D
1657 0U, // UDIV_ZPZZ_UNDEF_S
1658 0U, // UMAX_ZPZZ_UNDEF_B
1659 0U, // UMAX_ZPZZ_UNDEF_D
1660 0U, // UMAX_ZPZZ_UNDEF_H
1661 0U, // UMAX_ZPZZ_UNDEF_S
1662 0U, // UMIN_ZPZZ_UNDEF_B
1663 0U, // UMIN_ZPZZ_UNDEF_D
1664 0U, // UMIN_ZPZZ_UNDEF_H
1665 0U, // UMIN_ZPZZ_UNDEF_S
1666 0U, // UQSHL_ZPZI_ZERO_B
1667 0U, // UQSHL_ZPZI_ZERO_D
1668 0U, // UQSHL_ZPZI_ZERO_H
1669 0U, // UQSHL_ZPZI_ZERO_S
1670 0U, // URSHR_ZPZI_ZERO_B
1671 0U, // URSHR_ZPZI_ZERO_D
1672 0U, // URSHR_ZPZI_ZERO_H
1673 0U, // URSHR_ZPZI_ZERO_S
1674 546005U, // ABS_ZPmZ_B
1675 2148037845U, // ABS_ZPmZ_D
1676 34641109U, // ABS_ZPmZ_H
1677 570581U, // ABS_ZPmZ_S
1678 2216219861U, // ABSv16i8
1679 101201109U, // ABSv1i64
1680 2216744149U, // ABSv2i32
1681 69784789U, // ABSv2i64
1682 2217792725U, // ABSv4i16
1683 70833365U, // ABSv4i32
1684 2218841301U, // ABSv8i16
1685 71881941U, // ABSv8i8
1686 2282251665U, // ADCLB_ZZZ_D
1687 2315822481U, // ADCLB_ZZZ_S
1688 2282256010U, // ADCLT_ZZZ_D
1689 2315826826U, // ADCLT_ZZZ_S
1690 2248684796U, // ADCSWr
1691 2248684796U, // ADCSXr
1692 2248681672U, // ADCWr
1693 2248681672U, // ADCXr
1694 2248682230U, // ADDG
1695 2349352565U, // ADDHNB_ZZZ_B
1696 240158325U, // ADDHNB_ZZZ_H
1697 2416486005U, // ADDHNB_ZZZ_S
1698 2450020156U, // ADDHNT_ZZZ_B
1699 240686908U, // ADDHNT_ZZZ_H
1700 2282272572U, // ADDHNT_ZZZ_S
1701 2216743251U, // ADDHNv2i64_v2i32
1702 2486755692U, // ADDHNv2i64_v4i32
1703 70308179U, // ADDHNv4i32_v4i16
1704 339796332U, // ADDHNv4i32_v8i16
1705 2484658540U, // ADDHNv8i16_v16i8
1706 2219364691U, // ADDHNv8i16_v8i8
1707 2248683598U, // ADDPL_XXI
1708 369644111U, // ADDP_ZPmZ_B
1709 369652303U, // ADDP_ZPmZ_D
1710 2556465743U, // ADDP_ZPmZ_H
1711 369668687U, // ADDP_ZPmZ_S
1712 68735567U, // ADDPv16i8
1713 2216743503U, // ADDPv2i32
1714 2217267791U, // ADDPv2i64
1715 67646031U, // ADDPv2i64p
1716 70308431U, // ADDPv4i16
1717 70832719U, // ADDPv4i32
1718 2218840655U, // ADDPv8i16
1719 2219364943U, // ADDPv8i8
1720 2248684808U, // ADDSWri
1721 2248684808U, // ADDSWrs
1722 2248684808U, // ADDSWrx
1723 2248684808U, // ADDSXri
1724 2248684808U, // ADDSXrs
1725 2248684808U, // ADDSXrx
1726 2248684808U, // ADDSXrx64
1727 2248683724U, // ADDVL_XXI
1728 2215131242U, // ADDVv16i8v
1729 2215131242U, // ADDVv4i16v
1730 67647594U, // ADDVv4i32v
1731 2215131242U, // ADDVv8i16v
1732 67647594U, // ADDVv8i8v
1733 2248681873U, // ADDWri
1734 2248681873U, // ADDWrs
1735 2248681873U, // ADDWrx
1736 2248681873U, // ADDXri
1737 2248681873U, // ADDXrs
1738 2248681873U, // ADDXrx
1739 2248681873U, // ADDXrx64
1740 2584234385U, // ADD_ZI_B
1741 2416470417U, // ADD_ZI_D
1742 241731985U, // ADD_ZI_H
1743 2617813393U, // ADD_ZI_S
1744 369641873U, // ADD_ZPmZ_B
1745 369650065U, // ADD_ZPmZ_D
1746 2556463505U, // ADD_ZPmZ_H
1747 369666449U, // ADD_ZPmZ_S
1748 2584234385U, // ADD_ZZZ_B
1749 2416470417U, // ADD_ZZZ_D
1750 2389215633U, // ADD_ZZZ_H
1751 2617813393U, // ADD_ZZZ_S
1752 68733329U, // ADDv16i8
1753 2248681873U, // ADDv1i64
1754 2216741265U, // ADDv2i32
1755 2217265553U, // ADDv2i64
1756 70306193U, // ADDv4i16
1757 70830481U, // ADDv4i32
1758 2218838417U, // ADDv8i16
1759 2219362705U, // ADDv8i8
1760 101200781U, // ADR
1761 503853766U, // ADRP
1762 2423288717U, // ADR_LSL_ZZZ_D_0
1763 2423288717U, // ADR_LSL_ZZZ_D_1
1764 2423288717U, // ADR_LSL_ZZZ_D_2
1765 2423288717U, // ADR_LSL_ZZZ_D_3
1766 2624631693U, // ADR_LSL_ZZZ_S_0
1767 2624631693U, // ADR_LSL_ZZZ_S_1
1768 2624631693U, // ADR_LSL_ZZZ_S_2
1769 2624631693U, // ADR_LSL_ZZZ_S_3
1770 2423288717U, // ADR_SXTW_ZZZ_D_0
1771 2423288717U, // ADR_SXTW_ZZZ_D_1
1772 2423288717U, // ADR_SXTW_ZZZ_D_2
1773 2423288717U, // ADR_SXTW_ZZZ_D_3
1774 2423288717U, // ADR_UXTW_ZZZ_D_0
1775 2423288717U, // ADR_UXTW_ZZZ_D_1
1776 2423288717U, // ADR_UXTW_ZZZ_D_2
1777 2423288717U, // ADR_UXTW_ZZZ_D_3
1778 2584234513U, // AESD_ZZZ_B
1779 2484660753U, // AESDrr
1780 2584234654U, // AESE_ZZZ_B
1781 2484660894U, // AESErr
1782 436750546U, // AESIMC_ZZ_B
1783 2216216786U, // AESIMCrr
1784 436750554U, // AESMC_ZZ_B
1785 2216216794U, // AESMCrr
1786 2248684815U, // ANDSWri
1787 2248684815U, // ANDSWrs
1788 2248684815U, // ANDSXri
1789 2248684815U, // ANDSXrs
1790 2517128463U, // ANDS_PPzPP
1791 71806U, // ANDV_VPZ_B
1792 544815230U, // ANDV_VPZ_D
1793 545347710U, // ANDV_VPZ_H
1794 542734462U, // ANDV_VPZ_S
1795 2248681967U, // ANDWri
1796 2248681967U, // ANDWrs
1797 2248681967U, // ANDXri
1798 2248681967U, // ANDXrs
1799 2517125615U, // AND_PPzPP
1800 2416470511U, // AND_ZI
1801 369641967U, // AND_ZPmZ_B
1802 369650159U, // AND_ZPmZ_D
1803 2556463599U, // AND_ZPmZ_H
1804 369666543U, // AND_ZPmZ_S
1805 2416470511U, // AND_ZZZ
1806 68733423U, // ANDv16i8
1807 2219362799U, // ANDv8i8
1808 369641995U, // ASRD_ZPmI_B
1809 369650187U, // ASRD_ZPmI_D
1810 2556463627U, // ASRD_ZPmI_H
1811 369666571U, // ASRD_ZPmI_S
1812 369644589U, // ASRR_ZPmZ_B
1813 369652781U, // ASRR_ZPmZ_D
1814 2556466221U, // ASRR_ZPmZ_H
1815 369669165U, // ASRR_ZPmZ_S
1816 2248684601U, // ASRVWr
1817 2248684601U, // ASRVXr
1818 369644601U, // ASR_WIDE_ZPmZ_B
1819 2556466233U, // ASR_WIDE_ZPmZ_H
1820 369669177U, // ASR_WIDE_ZPmZ_S
1821 2584237113U, // ASR_WIDE_ZZZ_B
1822 241734713U, // ASR_WIDE_ZZZ_H
1823 2617816121U, // ASR_WIDE_ZZZ_S
1824 369644601U, // ASR_ZPmI_B
1825 369652793U, // ASR_ZPmI_D
1826 2556466233U, // ASR_ZPmI_H
1827 369669177U, // ASR_ZPmI_S
1828 369644601U, // ASR_ZPmZ_B
1829 369652793U, // ASR_ZPmZ_D
1830 2556466233U, // ASR_ZPmZ_H
1831 369669177U, // ASR_ZPmZ_S
1832 2584237113U, // ASR_ZZI_B
1833 2416473145U, // ASR_ZZI_D
1834 2389218361U, // ASR_ZZI_H
1835 2617816121U, // ASR_ZZI_S
1836 101196457U, // AUTDA
1837 101196987U, // AUTDB
1838 9093U, // AUTDZA
1839 10404U, // AUTDZB
1840 101196478U, // AUTIA
1841 7128U, // AUTIA1716
1842 7207U, // AUTIASP
1843 7198U, // AUTIAZ
1844 101197014U, // AUTIB
1845 7137U, // AUTIB1716
1846 7119U, // AUTIBSP
1847 7110U, // AUTIBZ
1848 9109U, // AUTIZA
1849 10420U, // AUTIZB
1850 7322U, // AXFLAG
1851 99232U, // B
1852 68737615U, // BCAX
1853 2416474703U, // BCAX_ZZZZ
1854 2584236634U, // BDEP_ZZZ_B
1855 2416472666U, // BDEP_ZZZ_D
1856 2389217882U, // BDEP_ZZZ_H
1857 2617815642U, // BDEP_ZZZ_S
1858 2584238116U, // BEXT_ZZZ_B
1859 2416474148U, // BEXT_ZZZ_D
1860 2389219364U, // BEXT_ZZZ_H
1861 2617817124U, // BEXT_ZZZ_S
1862 337704886U, // BF16DOTlanev4bf16
1863 2486761398U, // BF16DOTlanev8bf16
1864 101201917U, // BFCVT
1865 70308272U, // BFCVTN
1866 339796384U, // BFCVTN2
1867 571512688U, // BFCVTNT_ZPmZ
1868 571512829U, // BFCVT_ZPmZ
1869 2450044854U, // BFDOT_ZZI
1870 2450044854U, // BFDOT_ZZZ
1871 337704886U, // BFDOTv4bf16
1872 2486761398U, // BFDOTv8bf16
1873 2486756615U, // BFMLALB
1874 2486756615U, // BFMLALBIdx
1875 2486761050U, // BFMLALT
1876 2486761050U, // BFMLALTIdx
1877 2486756056U, // BFMMLA
1878 2450040071U, // BFMMLA_B_ZZI
1879 2450040071U, // BFMMLA_B_ZZZ
1880 2450044506U, // BFMMLA_T_ZZI
1881 2450044506U, // BFMMLA_T_ZZZ
1882 2450039512U, // BFMMLA_ZZZ
1883 2752000243U, // BFMWri
1884 2752000243U, // BFMXri
1885 2584236748U, // BGRP_ZZZ_B
1886 2416472780U, // BGRP_ZZZ_D
1887 2389217996U, // BGRP_ZZZ_H
1888 2617815756U, // BGRP_ZZZ_S
1889 2248684802U, // BICSWrs
1890 2248684802U, // BICSXrs
1891 2517128450U, // BICS_PPzPP
1892 2248681677U, // BICWrs
1893 2248681677U, // BICXrs
1894 2517125325U, // BIC_PPzPP
1895 369641677U, // BIC_ZPmZ_B
1896 369649869U, // BIC_ZPmZ_D
1897 2556463309U, // BIC_ZPmZ_H
1898 369666253U, // BIC_ZPmZ_S
1899 2416470221U, // BIC_ZZZ
1900 68733133U, // BICv16i8
1901 639690957U, // BICv2i32
1902 640739533U, // BICv4i16
1903 641263821U, // BICv4i32
1904 641788109U, // BICv8i16
1905 2219362509U, // BICv8i8
1906 337177290U, // BIFv16i8
1907 2487806666U, // BIFv8i8
1908 337180213U, // BITv16i8
1909 2487809589U, // BITv8i8
1910 102250U, // BL
1911 13247U, // BLR
1912 101196416U, // BLRAA
1913 15064U, // BLRAAZ
1914 101196870U, // BLRAB
1915 15079U, // BLRABZ
1916 13161U, // BR
1917 101196403U, // BRAA
1918 15057U, // BRAAZ
1919 101196857U, // BRAB
1920 15072U, // BRABZ
1921 7351U, // BRB_IALL
1922 7329U, // BRB_INJ
1923 110288U, // BRK
1924 2517128381U, // BRKAS_PPzP
1925 541381U, // BRKA_PPmP
1926 2517123781U, // BRKA_PPzP
1927 2517128417U, // BRKBS_PPzP
1928 541917U, // BRKB_PPmP
1929 2517124317U, // BRKB_PPzP
1930 2517128546U, // BRKNS_PPzP
1931 2517127536U, // BRKN_PPzP
1932 2517128388U, // BRKPAS_PPzPP
1933 2517123848U, // BRKPA_PPzPP
1934 2517128424U, // BRKPBS_PPzPP
1935 2517124843U, // BRKPB_PPzPP
1936 2416472380U, // BSL1N_ZZZZ
1937 2416472387U, // BSL2N_ZZZZ
1938 2416472185U, // BSL_ZZZZ
1939 337178745U, // BSLv16i8
1940 2487808121U, // BSLv8i8
1941 121669U, // Bcc
1942 2584234384U, // CADD_ZZI_B
1943 2416470416U, // CADD_ZZI_D
1944 2389215632U, // CADD_ZZI_H
1945 2617813392U, // CADD_ZZI_S
1946 604628063U, // CASAB
1947 604629994U, // CASAH
1948 604628306U, // CASALB
1949 604630153U, // CASALH
1950 604630853U, // CASALW
1951 604630853U, // CASALX
1952 604627789U, // CASAW
1953 604627789U, // CASAX
1954 604628918U, // CASB
1955 604630538U, // CASH
1956 604628512U, // CASLB
1957 604630247U, // CASLH
1958 604631154U, // CASLW
1959 604631154U, // CASLX
1960 134948U, // CASPALW
1961 143140U, // CASPALX
1962 131855U, // CASPAW
1963 140047U, // CASPAX
1964 135253U, // CASPLW
1965 143445U, // CASPLX
1966 135890U, // CASPW
1967 144082U, // CASPX
1968 604632248U, // CASW
1969 604632248U, // CASX
1970 671628030U, // CBNZW
1971 671628030U, // CBNZX
1972 671628015U, // CBZW
1973 671628015U, // CBZX
1974 2248683894U, // CCMNWi
1975 2248683894U, // CCMNWr
1976 2248683894U, // CCMNXi
1977 2248683894U, // CCMNXr
1978 2248684167U, // CCMPWi
1979 2248684167U, // CCMPWr
1980 2248684167U, // CCMPXi
1981 2248684167U, // CCMPXr
1982 2450028464U, // CDOT_ZZZI_D
1983 705214384U, // CDOT_ZZZI_S
1984 2450028464U, // CDOT_ZZZ_D
1985 705214384U, // CDOT_ZZZ_S
1986 7385U, // CFINV
1987 2517115747U, // CLASTA_RPZ_B
1988 2517115747U, // CLASTA_RPZ_D
1989 2517115747U, // CLASTA_RPZ_H
1990 2517115747U, // CLASTA_RPZ_S
1991 2517115747U, // CLASTA_VPZ_B
1992 2517115747U, // CLASTA_VPZ_D
1993 2517115747U, // CLASTA_VPZ_H
1994 2517115747U, // CLASTA_VPZ_S
1995 2517123939U, // CLASTA_ZPZ_B
1996 2517132131U, // CLASTA_ZPZ_D
1997 2388689763U, // CLASTA_ZPZ_H
1998 2517148515U, // CLASTA_ZPZ_S
1999 2517116959U, // CLASTB_RPZ_B
2000 2517116959U, // CLASTB_RPZ_D
2001 2517116959U, // CLASTB_RPZ_H
2002 2517116959U, // CLASTB_RPZ_S
2003 2517116959U, // CLASTB_VPZ_B
2004 2517116959U, // CLASTB_VPZ_D
2005 2517116959U, // CLASTB_VPZ_H
2006 2517116959U, // CLASTB_VPZ_S
2007 2517125151U, // CLASTB_ZPZ_B
2008 2517133343U, // CLASTB_ZPZ_D
2009 2388690975U, // CLASTB_ZPZ_H
2010 2517149727U, // CLASTB_ZPZ_S
2011 14976U, // CLREX
2012 101201203U, // CLSWr
2013 101201203U, // CLSXr
2014 546099U, // CLS_ZPmZ_B
2015 2148037939U, // CLS_ZPmZ_D
2016 34641203U, // CLS_ZPmZ_H
2017 570675U, // CLS_ZPmZ_S
2018 2216219955U, // CLSv16i8
2019 2216744243U, // CLSv2i32
2020 2217792819U, // CLSv4i16
2021 70833459U, // CLSv4i32
2022 2218841395U, // CLSv8i16
2023 71882035U, // CLSv8i8
2024 101202681U, // CLZWr
2025 101202681U, // CLZXr
2026 547577U, // CLZ_ZPmZ_B
2027 2148039417U, // CLZ_ZPmZ_D
2028 34642681U, // CLZ_ZPmZ_H
2029 572153U, // CLZ_ZPmZ_S
2030 2216221433U, // CLZv16i8
2031 2216745721U, // CLZv2i32
2032 2217794297U, // CLZv4i16
2033 70834937U, // CLZv4i32
2034 2218842873U, // CLZv8i16
2035 71883513U, // CLZv8i8
2036 68735782U, // CMEQv16i8
2037 2216219430U, // CMEQv16i8rz
2038 2248684326U, // CMEQv1i64
2039 101200678U, // CMEQv1i64rz
2040 2216743718U, // CMEQv2i32
2041 2216743718U, // CMEQv2i32rz
2042 2217268006U, // CMEQv2i64
2043 69784358U, // CMEQv2i64rz
2044 70308646U, // CMEQv4i16
2045 2217792294U, // CMEQv4i16rz
2046 70832934U, // CMEQv4i32
2047 70832934U, // CMEQv4i32rz
2048 2218840870U, // CMEQv8i16
2049 2218840870U, // CMEQv8i16rz
2050 2219365158U, // CMEQv8i8
2051 71881510U, // CMEQv8i8rz
2052 68733500U, // CMGEv16i8
2053 2216217148U, // CMGEv16i8rz
2054 2248682044U, // CMGEv1i64
2055 101198396U, // CMGEv1i64rz
2056 2216741436U, // CMGEv2i32
2057 2216741436U, // CMGEv2i32rz
2058 2217265724U, // CMGEv2i64
2059 69782076U, // CMGEv2i64rz
2060 70306364U, // CMGEv4i16
2061 2217790012U, // CMGEv4i16rz
2062 70830652U, // CMGEv4i32
2063 70830652U, // CMGEv4i32rz
2064 2218838588U, // CMGEv8i16
2065 2218838588U, // CMGEv8i16rz
2066 2219362876U, // CMGEv8i8
2067 71879228U, // CMGEv8i8rz
2068 68736551U, // CMGTv16i8
2069 2216220199U, // CMGTv16i8rz
2070 2248685095U, // CMGTv1i64
2071 101201447U, // CMGTv1i64rz
2072 2216744487U, // CMGTv2i32
2073 2216744487U, // CMGTv2i32rz
2074 2217268775U, // CMGTv2i64
2075 69785127U, // CMGTv2i64rz
2076 70309415U, // CMGTv4i16
2077 2217793063U, // CMGTv4i16rz
2078 70833703U, // CMGTv4i32
2079 70833703U, // CMGTv4i32rz
2080 2218841639U, // CMGTv8i16
2081 2218841639U, // CMGTv8i16rz
2082 2219365927U, // CMGTv8i8
2083 71882279U, // CMGTv8i8rz
2084 68734624U, // CMHIv16i8
2085 2248683168U, // CMHIv1i64
2086 2216742560U, // CMHIv2i32
2087 2217266848U, // CMHIv2i64
2088 70307488U, // CMHIv4i16
2089 70831776U, // CMHIv4i32
2090 2218839712U, // CMHIv8i16
2091 2219364000U, // CMHIv8i8
2092 68736294U, // CMHSv16i8
2093 2248684838U, // CMHSv1i64
2094 2216744230U, // CMHSv2i32
2095 2217268518U, // CMHSv2i64
2096 70309158U, // CMHSv4i16
2097 70833446U, // CMHSv4i32
2098 2218841382U, // CMHSv8i16
2099 2219365670U, // CMHSv8i8
2100 2390786764U, // CMLA_ZZZI_H
2101 2315821772U, // CMLA_ZZZI_S
2102 705184460U, // CMLA_ZZZ_B
2103 2282250956U, // CMLA_ZZZ_D
2104 2390786764U, // CMLA_ZZZ_H
2105 2315821772U, // CMLA_ZZZ_S
2106 2216217179U, // CMLEv16i8rz
2107 101198427U, // CMLEv1i64rz
2108 2216741467U, // CMLEv2i32rz
2109 69782107U, // CMLEv2i64rz
2110 2217790043U, // CMLEv4i16rz
2111 70830683U, // CMLEv4i32rz
2112 2218838619U, // CMLEv8i16rz
2113 71879259U, // CMLEv8i8rz
2114 2216220402U, // CMLTv16i8rz
2115 101201650U, // CMLTv1i64rz
2116 2216744690U, // CMLTv2i32rz
2117 69785330U, // CMLTv2i64rz
2118 2217793266U, // CMLTv4i16rz
2119 70833906U, // CMLTv4i32rz
2120 2218841842U, // CMLTv8i16rz
2121 71882482U, // CMLTv8i8rz
2122 2517127989U, // CMPEQ_PPzZI_B
2123 2517136181U, // CMPEQ_PPzZI_D
2124 2892010293U, // CMPEQ_PPzZI_H
2125 2517152565U, // CMPEQ_PPzZI_S
2126 2517127989U, // CMPEQ_PPzZZ_B
2127 2517136181U, // CMPEQ_PPzZZ_D
2128 2892010293U, // CMPEQ_PPzZZ_H
2129 2517152565U, // CMPEQ_PPzZZ_S
2130 2517127989U, // CMPEQ_WIDE_PPzZZ_B
2131 2892010293U, // CMPEQ_WIDE_PPzZZ_H
2132 2517152565U, // CMPEQ_WIDE_PPzZZ_S
2133 2517125698U, // CMPGE_PPzZI_B
2134 2517133890U, // CMPGE_PPzZI_D
2135 2892008002U, // CMPGE_PPzZI_H
2136 2517150274U, // CMPGE_PPzZI_S
2137 2517125698U, // CMPGE_PPzZZ_B
2138 2517133890U, // CMPGE_PPzZZ_D
2139 2892008002U, // CMPGE_PPzZZ_H
2140 2517150274U, // CMPGE_PPzZZ_S
2141 2517125698U, // CMPGE_WIDE_PPzZZ_B
2142 2892008002U, // CMPGE_WIDE_PPzZZ_H
2143 2517150274U, // CMPGE_WIDE_PPzZZ_S
2144 2517128749U, // CMPGT_PPzZI_B
2145 2517136941U, // CMPGT_PPzZI_D
2146 2892011053U, // CMPGT_PPzZI_H
2147 2517153325U, // CMPGT_PPzZI_S
2148 2517128749U, // CMPGT_PPzZZ_B
2149 2517136941U, // CMPGT_PPzZZ_D
2150 2892011053U, // CMPGT_PPzZZ_H
2151 2517153325U, // CMPGT_PPzZZ_S
2152 2517128749U, // CMPGT_WIDE_PPzZZ_B
2153 2892011053U, // CMPGT_WIDE_PPzZZ_H
2154 2517153325U, // CMPGT_WIDE_PPzZZ_S
2155 2517126822U, // CMPHI_PPzZI_B
2156 2517135014U, // CMPHI_PPzZI_D
2157 2892009126U, // CMPHI_PPzZI_H
2158 2517151398U, // CMPHI_PPzZI_S
2159 2517126822U, // CMPHI_PPzZZ_B
2160 2517135014U, // CMPHI_PPzZZ_D
2161 2892009126U, // CMPHI_PPzZZ_H
2162 2517151398U, // CMPHI_PPzZZ_S
2163 2517126822U, // CMPHI_WIDE_PPzZZ_B
2164 2892009126U, // CMPHI_WIDE_PPzZZ_H
2165 2517151398U, // CMPHI_WIDE_PPzZZ_S
2166 2517128492U, // CMPHS_PPzZI_B
2167 2517136684U, // CMPHS_PPzZI_D
2168 2892010796U, // CMPHS_PPzZI_H
2169 2517153068U, // CMPHS_PPzZI_S
2170 2517128492U, // CMPHS_PPzZZ_B
2171 2517136684U, // CMPHS_PPzZZ_D
2172 2892010796U, // CMPHS_PPzZZ_H
2173 2517153068U, // CMPHS_PPzZZ_S
2174 2517128492U, // CMPHS_WIDE_PPzZZ_B
2175 2892010796U, // CMPHS_WIDE_PPzZZ_H
2176 2517153068U, // CMPHS_WIDE_PPzZZ_S
2177 2517125729U, // CMPLE_PPzZI_B
2178 2517133921U, // CMPLE_PPzZI_D
2179 2892008033U, // CMPLE_PPzZI_H
2180 2517150305U, // CMPLE_PPzZI_S
2181 2517125729U, // CMPLE_WIDE_PPzZZ_B
2182 2892008033U, // CMPLE_WIDE_PPzZZ_H
2183 2517150305U, // CMPLE_WIDE_PPzZZ_S
2184 2517127699U, // CMPLO_PPzZI_B
2185 2517135891U, // CMPLO_PPzZI_D
2186 2892010003U, // CMPLO_PPzZI_H
2187 2517152275U, // CMPLO_PPzZI_S
2188 2517127699U, // CMPLO_WIDE_PPzZZ_B
2189 2892010003U, // CMPLO_WIDE_PPzZZ_H
2190 2517152275U, // CMPLO_WIDE_PPzZZ_S
2191 2517128526U, // CMPLS_PPzZI_B
2192 2517136718U, // CMPLS_PPzZI_D
2193 2892010830U, // CMPLS_PPzZI_H
2194 2517153102U, // CMPLS_PPzZI_S
2195 2517128526U, // CMPLS_WIDE_PPzZZ_B
2196 2892010830U, // CMPLS_WIDE_PPzZZ_H
2197 2517153102U, // CMPLS_WIDE_PPzZZ_S
2198 2517128952U, // CMPLT_PPzZI_B
2199 2517137144U, // CMPLT_PPzZI_D
2200 2892011256U, // CMPLT_PPzZI_H
2201 2517153528U, // CMPLT_PPzZI_S
2202 2517128952U, // CMPLT_WIDE_PPzZZ_B
2203 2892011256U, // CMPLT_WIDE_PPzZZ_H
2204 2517153528U, // CMPLT_WIDE_PPzZZ_S
2205 2517125752U, // CMPNE_PPzZI_B
2206 2517133944U, // CMPNE_PPzZI_D
2207 2892008056U, // CMPNE_PPzZI_H
2208 2517150328U, // CMPNE_PPzZI_S
2209 2517125752U, // CMPNE_PPzZZ_B
2210 2517133944U, // CMPNE_PPzZZ_D
2211 2892008056U, // CMPNE_PPzZZ_H
2212 2517150328U, // CMPNE_PPzZZ_S
2213 2517125752U, // CMPNE_WIDE_PPzZZ_B
2214 2892008056U, // CMPNE_WIDE_PPzZZ_H
2215 2517150328U, // CMPNE_WIDE_PPzZZ_S
2216 68737014U, // CMTSTv16i8
2217 2248685558U, // CMTSTv1i64
2218 2216744950U, // CMTSTv2i32
2219 2217269238U, // CMTSTv2i64
2220 70309878U, // CMTSTv4i16
2221 70834166U, // CMTSTv4i32
2222 2218842102U, // CMTSTv8i16
2223 2219366390U, // CMTSTv8i8
2224 546763U, // CNOT_ZPmZ_B
2225 2148038603U, // CNOT_ZPmZ_D
2226 34641867U, // CNOT_ZPmZ_H
2227 571339U, // CNOT_ZPmZ_S
2228 772286482U, // CNTB_XPiI
2229 772286999U, // CNTD_XPiI
2230 772288075U, // CNTH_XPiI
2231 2517119704U, // CNTP_XPP_B
2232 2517119704U, // CNTP_XPP_D
2233 2517119704U, // CNTP_XPP_H
2234 2517119704U, // CNTP_XPP_S
2235 772291099U, // CNTW_XPiI
2236 546605U, // CNT_ZPmZ_B
2237 2148038445U, // CNT_ZPmZ_D
2238 34641709U, // CNT_ZPmZ_H
2239 571181U, // CNT_ZPmZ_S
2240 2216220461U, // CNTv16i8
2241 71882541U, // CNTv8i8
2242 2517136891U, // COMPACT_ZPZ_D
2243 2517153275U, // COMPACT_ZPZ_S
2244 2148031160U, // CPY_ZPmI_B
2245 555704U, // CPY_ZPmI_D
2246 806394552U, // CPY_ZPmI_H
2247 2148055736U, // CPY_ZPmI_S
2248 547512U, // CPY_ZPmR_B
2249 555704U, // CPY_ZPmR_D
2250 839948984U, // CPY_ZPmR_H
2251 572088U, // CPY_ZPmR_S
2252 547512U, // CPY_ZPmV_B
2253 555704U, // CPY_ZPmV_D
2254 839948984U, // CPY_ZPmV_H
2255 572088U, // CPY_ZPmV_S
2256 2517129912U, // CPY_ZPzI_B
2257 2517138104U, // CPY_ZPzI_D
2258 2892012216U, // CPY_ZPzI_H
2259 2517154488U, // CPY_ZPzI_S
2260 67647706U, // CPYi16
2261 2215131354U, // CPYi32
2262 67647706U, // CPYi64
2263 2215131354U, // CPYi8
2264 2248680402U, // CRC32Brr
2265 2248680579U, // CRC32CBrr
2266 2248682510U, // CRC32CHrr
2267 2248685932U, // CRC32CWrr
2268 2248686192U, // CRC32CXrr
2269 2248682346U, // CRC32Hrr
2270 2248685874U, // CRC32Wrr
2271 2248686131U, // CRC32Xrr
2272 2248683466U, // CSELWr
2273 2248683466U, // CSELXr
2274 2248681697U, // CSINCWr
2275 2248681697U, // CSINCXr
2276 2248685778U, // CSINVWr
2277 2248685778U, // CSINVXr
2278 2248682254U, // CSNEGWr
2279 2248682254U, // CSNEGXr
2280 101200684U, // CTERMEQ_WW
2281 101200684U, // CTERMEQ_XX
2282 101198447U, // CTERMNE_WW
2283 101198447U, // CTERMNE_XX
2284 106560U, // DCPS1
2285 106988U, // DCPS2
2286 107054U, // DCPS3
2287 872948878U, // DECB_XPiI
2288 872950129U, // DECD_XPiI
2289 872966513U, // DECD_ZPiI
2290 872950809U, // DECH_XPiI
2291 8948761U, // DECH_ZPiI
2292 436744752U, // DECP_XP_B
2293 268972592U, // DECP_XP_D
2294 201863728U, // DECP_XP_H
2295 470299184U, // DECP_XP_S
2296 134771248U, // DECP_ZP_D
2297 545296944U, // DECP_ZP_H
2298 168342064U, // DECP_ZP_S
2299 872954231U, // DECW_XPiI
2300 872986999U, // DECW_ZPiI
2301 149094U, // DMB
2302 7367U, // DRPS
2303 149436U, // DSB
2304 157628U, // DSBnXS
2305 906522919U, // DUPM_ZI
2306 940069612U, // DUP_ZI_B
2307 973632236U, // DUP_ZI_D
2308 9474796U, // DUP_ZI_H
2309 1007203052U, // DUP_ZI_S
2310 101208812U, // DUP_ZR_B
2311 101217004U, // DUP_ZR_D
2312 546869996U, // DUP_ZR_H
2313 101233388U, // DUP_ZR_S
2314 436753132U, // DUP_ZZI_B
2315 268989164U, // DUP_ZZI_D
2316 1047040748U, // DUP_ZZI_H
2317 1050841836U, // DUP_ZZI_Q
2318 470332140U, // DUP_ZZI_S
2319 102290156U, // DUPv16i8gpr
2320 2216219372U, // DUPv16i8lane
2321 102814444U, // DUPv2i32gpr
2322 2216743660U, // DUPv2i32lane
2323 103338732U, // DUPv2i64gpr
2324 69784300U, // DUPv2i64lane
2325 103863020U, // DUPv4i16gpr
2326 70308588U, // DUPv4i16lane
2327 104387308U, // DUPv4i32gpr
2328 2218316524U, // DUPv4i32lane
2329 104911596U, // DUPv8i16gpr
2330 71357164U, // DUPv8i16lane
2331 105435884U, // DUPv8i8gpr
2332 2219365100U, // DUPv8i8lane
2333 2248683900U, // EONWrs
2334 2248683900U, // EONXrs
2335 68731432U, // EOR3
2336 2416468520U, // EOR3_ZZZZ
2337 705189364U, // EORBT_ZZZ_B
2338 2282255860U, // EORBT_ZZZ_D
2339 2390791668U, // EORBT_ZZZ_H
2340 2315826676U, // EORBT_ZZZ_S
2341 2517128603U, // EORS_PPzPP
2342 705185816U, // EORTB_ZZZ_B
2343 2282252312U, // EORTB_ZZZ_D
2344 2390788120U, // EORTB_ZZZ_H
2345 2315823128U, // EORTB_ZZZ_S
2346 71915U, // EORV_VPZ_B
2347 544815339U, // EORV_VPZ_D
2348 545347819U, // EORV_VPZ_H
2349 542734571U, // EORV_VPZ_S
2350 2248684562U, // EORWri
2351 2248684562U, // EORWrs
2352 2248684562U, // EORXri
2353 2248684562U, // EORXrs
2354 2517128210U, // EOR_PPzPP
2355 2416473106U, // EOR_ZI
2356 369644562U, // EOR_ZPmZ_B
2357 369652754U, // EOR_ZPmZ_D
2358 2556466194U, // EOR_ZPmZ_H
2359 369669138U, // EOR_ZPmZ_S
2360 2416473106U, // EOR_ZZZ
2361 68736018U, // EORv16i8
2362 2219365394U, // EORv8i8
2363 7372U, // ERET
2364 7298U, // ERETAA
2365 7305U, // ERETAB
2366 2248684639U, // EXTRWrri
2367 2248684639U, // EXTRXrri
2368 2584238117U, // EXT_ZZI
2369 3221772325U, // EXT_ZZI_B
2370 68737061U, // EXTv16i8
2371 2219366437U, // EXTv8i8
2372 2248681814U, // FABD16
2373 2248681814U, // FABD32
2374 2248681814U, // FABD64
2375 369650006U, // FABD_ZPmZ_D
2376 2556463446U, // FABD_ZPmZ_H
2377 369666390U, // FABD_ZPmZ_S
2378 2216741206U, // FABDv2f32
2379 2217265494U, // FABDv2f64
2380 70306134U, // FABDv4f16
2381 70830422U, // FABDv4f32
2382 2218838358U, // FABDv8f16
2383 101201108U, // FABSDr
2384 101201108U, // FABSHr
2385 101201108U, // FABSSr
2386 2148037844U, // FABS_ZPmZ_D
2387 34641108U, // FABS_ZPmZ_H
2388 570580U, // FABS_ZPmZ_S
2389 2216744148U, // FABSv2f32
2390 69784788U, // FABSv2f64
2391 2217792724U, // FABSv4f16
2392 70833364U, // FABSv4f32
2393 2218841300U, // FABSv8f16
2394 2248682027U, // FACGE16
2395 2248682027U, // FACGE32
2396 2248682027U, // FACGE64
2397 2517133867U, // FACGE_PPzZZ_D
2398 2892007979U, // FACGE_PPzZZ_H
2399 2517150251U, // FACGE_PPzZZ_S
2400 2216741419U, // FACGEv2f32
2401 2217265707U, // FACGEv2f64
2402 70306347U, // FACGEv4f16
2403 70830635U, // FACGEv4f32
2404 2218838571U, // FACGEv8f16
2405 2248685078U, // FACGT16
2406 2248685078U, // FACGT32
2407 2248685078U, // FACGT64
2408 2517136918U, // FACGT_PPzZZ_D
2409 2892011030U, // FACGT_PPzZZ_H
2410 2517153302U, // FACGT_PPzZZ_S
2411 2216744470U, // FACGTv2f32
2412 2217268758U, // FACGTv2f64
2413 70309398U, // FACGTv4f16
2414 70833686U, // FACGTv4f32
2415 2218841622U, // FACGTv8f16
2416 11084450U, // FADDA_VPZ_D
2417 11616930U, // FADDA_VPZ_H
2418 12149410U, // FADDA_VPZ_S
2419 2248681893U, // FADDDrr
2420 2248681893U, // FADDHrr
2421 369652302U, // FADDP_ZPmZZ_D
2422 2556465742U, // FADDP_ZPmZZ_H
2423 369668686U, // FADDP_ZPmZZ_S
2424 2216743502U, // FADDPv2f32
2425 2217267790U, // FADDPv2f64
2426 67646030U, // FADDPv2i16p
2427 2215129678U, // FADDPv2i32p
2428 67646030U, // FADDPv2i64p
2429 70308430U, // FADDPv4f16
2430 70832718U, // FADDPv4f32
2431 2218840654U, // FADDPv8f16
2432 2248681893U, // FADDSrr
2433 544815209U, // FADDV_VPZ_D
2434 545347689U, // FADDV_VPZ_H
2435 542734441U, // FADDV_VPZ_S
2436 369650085U, // FADD_ZPmI_D
2437 2556463525U, // FADD_ZPmI_H
2438 369666469U, // FADD_ZPmI_S
2439 369650085U, // FADD_ZPmZ_D
2440 2556463525U, // FADD_ZPmZ_H
2441 369666469U, // FADD_ZPmZ_S
2442 2416470437U, // FADD_ZZZ_D
2443 2389215653U, // FADD_ZZZ_H
2444 2617813413U, // FADD_ZZZ_S
2445 2216741285U, // FADDv2f32
2446 2217265573U, // FADDv2f64
2447 70306213U, // FADDv4f16
2448 70830501U, // FADDv4f32
2449 2218838437U, // FADDv8f16
2450 369650063U, // FCADD_ZPmZ_D
2451 2556463503U, // FCADD_ZPmZ_H
2452 369666447U, // FCADD_ZPmZ_S
2453 2216741263U, // FCADDv2f32
2454 2217265551U, // FCADDv2f64
2455 70306191U, // FCADDv4f16
2456 70830479U, // FCADDv4f32
2457 2218838415U, // FCADDv8f16
2458 2248684166U, // FCCMPDrr
2459 2248682127U, // FCCMPEDrr
2460 2248682127U, // FCCMPEHrr
2461 2248682127U, // FCCMPESrr
2462 2248684166U, // FCCMPHrr
2463 2248684166U, // FCCMPSrr
2464 2248684325U, // FCMEQ16
2465 2248684325U, // FCMEQ32
2466 2248684325U, // FCMEQ64
2467 2517136165U, // FCMEQ_PPzZ0_D
2468 2892010277U, // FCMEQ_PPzZ0_H
2469 2517152549U, // FCMEQ_PPzZ0_S
2470 2517136165U, // FCMEQ_PPzZZ_D
2471 2892010277U, // FCMEQ_PPzZZ_H
2472 2517152549U, // FCMEQ_PPzZZ_S
2473 2248684325U, // FCMEQv1i16rz
2474 2248684325U, // FCMEQv1i32rz
2475 2248684325U, // FCMEQv1i64rz
2476 2216743717U, // FCMEQv2f32
2477 2217268005U, // FCMEQv2f64
2478 69260069U, // FCMEQv2i32rz
2479 2217268005U, // FCMEQv2i64rz
2480 70308645U, // FCMEQv4f16
2481 70832933U, // FCMEQv4f32
2482 70308645U, // FCMEQv4i16rz
2483 2218316581U, // FCMEQv4i32rz
2484 2218840869U, // FCMEQv8f16
2485 71357221U, // FCMEQv8i16rz
2486 2248682043U, // FCMGE16
2487 2248682043U, // FCMGE32
2488 2248682043U, // FCMGE64
2489 2517133883U, // FCMGE_PPzZ0_D
2490 2892007995U, // FCMGE_PPzZ0_H
2491 2517150267U, // FCMGE_PPzZ0_S
2492 2517133883U, // FCMGE_PPzZZ_D
2493 2892007995U, // FCMGE_PPzZZ_H
2494 2517150267U, // FCMGE_PPzZZ_S
2495 2248682043U, // FCMGEv1i16rz
2496 2248682043U, // FCMGEv1i32rz
2497 2248682043U, // FCMGEv1i64rz
2498 2216741435U, // FCMGEv2f32
2499 2217265723U, // FCMGEv2f64
2500 69257787U, // FCMGEv2i32rz
2501 2217265723U, // FCMGEv2i64rz
2502 70306363U, // FCMGEv4f16
2503 70830651U, // FCMGEv4f32
2504 70306363U, // FCMGEv4i16rz
2505 2218314299U, // FCMGEv4i32rz
2506 2218838587U, // FCMGEv8f16
2507 71354939U, // FCMGEv8i16rz
2508 2248685094U, // FCMGT16
2509 2248685094U, // FCMGT32
2510 2248685094U, // FCMGT64
2511 2517136934U, // FCMGT_PPzZ0_D
2512 2892011046U, // FCMGT_PPzZ0_H
2513 2517153318U, // FCMGT_PPzZ0_S
2514 2517136934U, // FCMGT_PPzZZ_D
2515 2892011046U, // FCMGT_PPzZZ_H
2516 2517153318U, // FCMGT_PPzZZ_S
2517 2248685094U, // FCMGTv1i16rz
2518 2248685094U, // FCMGTv1i32rz
2519 2248685094U, // FCMGTv1i64rz
2520 2216744486U, // FCMGTv2f32
2521 2217268774U, // FCMGTv2f64
2522 69260838U, // FCMGTv2i32rz
2523 2217268774U, // FCMGTv2i64rz
2524 70309414U, // FCMGTv4f16
2525 70833702U, // FCMGTv4f32
2526 70309414U, // FCMGTv4i16rz
2527 2218317350U, // FCMGTv4i32rz
2528 2218841638U, // FCMGTv8f16
2529 71357990U, // FCMGTv8i16rz
2530 369648331U, // FCMLA_ZPmZZ_D
2531 2556461771U, // FCMLA_ZPmZZ_H
2532 369664715U, // FCMLA_ZPmZZ_S
2533 2390786763U, // FCMLA_ZZZI_H
2534 2315821771U, // FCMLA_ZZZI_S
2535 2485183179U, // FCMLAv2f32
2536 2485707467U, // FCMLAv2f64
2537 338748107U, // FCMLAv4f16
2538 338748107U, // FCMLAv4f16_indexed
2539 339272395U, // FCMLAv4f32
2540 339272395U, // FCMLAv4f32_indexed
2541 2487280331U, // FCMLAv8f16
2542 2487280331U, // FCMLAv8f16_indexed
2543 2517133914U, // FCMLE_PPzZ0_D
2544 2892008026U, // FCMLE_PPzZ0_H
2545 2517150298U, // FCMLE_PPzZ0_S
2546 2248682074U, // FCMLEv1i16rz
2547 2248682074U, // FCMLEv1i32rz
2548 2248682074U, // FCMLEv1i64rz
2549 69257818U, // FCMLEv2i32rz
2550 2217265754U, // FCMLEv2i64rz
2551 70306394U, // FCMLEv4i16rz
2552 2218314330U, // FCMLEv4i32rz
2553 71354970U, // FCMLEv8i16rz
2554 2517137137U, // FCMLT_PPzZ0_D
2555 2892011249U, // FCMLT_PPzZ0_H
2556 2517153521U, // FCMLT_PPzZ0_S
2557 2248685297U, // FCMLTv1i16rz
2558 2248685297U, // FCMLTv1i32rz
2559 2248685297U, // FCMLTv1i64rz
2560 69261041U, // FCMLTv2i32rz
2561 2217268977U, // FCMLTv2i64rz
2562 70309617U, // FCMLTv4i16rz
2563 2218317553U, // FCMLTv4i32rz
2564 71358193U, // FCMLTv8i16rz
2565 2517133928U, // FCMNE_PPzZ0_D
2566 2892008040U, // FCMNE_PPzZ0_H
2567 2517150312U, // FCMNE_PPzZ0_S
2568 2517133928U, // FCMNE_PPzZZ_D
2569 2892008040U, // FCMNE_PPzZZ_H
2570 2517150312U, // FCMNE_PPzZZ_S
2571 12595853U, // FCMPDri
2572 101200525U, // FCMPDrr
2573 12593815U, // FCMPEDri
2574 101198487U, // FCMPEDrr
2575 12593815U, // FCMPEHri
2576 101198487U, // FCMPEHrr
2577 12593815U, // FCMPESri
2578 101198487U, // FCMPESrr
2579 12595853U, // FCMPHri
2580 101200525U, // FCMPHrr
2581 12595853U, // FCMPSri
2582 101200525U, // FCMPSrr
2583 2517135898U, // FCMUO_PPzZZ_D
2584 2892010010U, // FCMUO_PPzZZ_H
2585 2517152282U, // FCMUO_PPzZZ_S
2586 2148039351U, // FCPY_ZPmI_D
2587 1108384439U, // FCPY_ZPmI_H
2588 2148055735U, // FCPY_ZPmI_S
2589 2248683465U, // FCSELDrrr
2590 2248683465U, // FCSELHrrr
2591 2248683465U, // FCSELSrrr
2592 101201100U, // FCVTASUWDr
2593 101201100U, // FCVTASUWHr
2594 101201100U, // FCVTASUWSr
2595 101201100U, // FCVTASUXDr
2596 101201100U, // FCVTASUXHr
2597 101201100U, // FCVTASUXSr
2598 101201100U, // FCVTASv1f16
2599 101201100U, // FCVTASv1i32
2600 101201100U, // FCVTASv1i64
2601 2216744140U, // FCVTASv2f32
2602 69784780U, // FCVTASv2f64
2603 2217792716U, // FCVTASv4f16
2604 70833356U, // FCVTASv4f32
2605 2218841292U, // FCVTASv8f16
2606 101201969U, // FCVTAUUWDr
2607 101201969U, // FCVTAUUWHr
2608 101201969U, // FCVTAUUWSr
2609 101201969U, // FCVTAUUXDr
2610 101201969U, // FCVTAUUXHr
2611 101201969U, // FCVTAUUXSr
2612 101201969U, // FCVTAUv1f16
2613 101201969U, // FCVTAUv1i32
2614 101201969U, // FCVTAUv1i64
2615 2216745009U, // FCVTAUv2f32
2616 69785649U, // FCVTAUv2f64
2617 2217793585U, // FCVTAUv4f16
2618 70834225U, // FCVTAUv4f32
2619 2218842161U, // FCVTAUv8f16
2620 101201918U, // FCVTDHr
2621 101201918U, // FCVTDSr
2622 101201918U, // FCVTHDr
2623 101201918U, // FCVTHSr
2624 2148054817U, // FCVTLT_ZPmZ_HtoS
2625 554785U, // FCVTLT_ZPmZ_StoD
2626 2217267370U, // FCVTLv2i32
2627 2218315946U, // FCVTLv4i16
2628 69779802U, // FCVTLv4i32
2629 2218312026U, // FCVTLv8i16
2630 101201237U, // FCVTMSUWDr
2631 101201237U, // FCVTMSUWHr
2632 101201237U, // FCVTMSUWSr
2633 101201237U, // FCVTMSUXDr
2634 101201237U, // FCVTMSUXHr
2635 101201237U, // FCVTMSUXSr
2636 101201237U, // FCVTMSv1f16
2637 101201237U, // FCVTMSv1i32
2638 101201237U, // FCVTMSv1i64
2639 2216744277U, // FCVTMSv2f32
2640 69784917U, // FCVTMSv2f64
2641 2217792853U, // FCVTMSv4f16
2642 70833493U, // FCVTMSv4f32
2643 2218841429U, // FCVTMSv8f16
2644 101201985U, // FCVTMUUWDr
2645 101201985U, // FCVTMUUWHr
2646 101201985U, // FCVTMUUWSr
2647 101201985U, // FCVTMUUXDr
2648 101201985U, // FCVTMUUXHr
2649 101201985U, // FCVTMUUXSr
2650 101201985U, // FCVTMUv1f16
2651 101201985U, // FCVTMUv1i32
2652 101201985U, // FCVTMUv1i64
2653 2216745025U, // FCVTMUv2f32
2654 69785665U, // FCVTMUv2f64
2655 2217793601U, // FCVTMUv4f16
2656 70834241U, // FCVTMUv4f32
2657 2218842177U, // FCVTMUv8f16
2658 101201263U, // FCVTNSUWDr
2659 101201263U, // FCVTNSUWHr
2660 101201263U, // FCVTNSUWSr
2661 101201263U, // FCVTNSUXDr
2662 101201263U, // FCVTNSUXHr
2663 101201263U, // FCVTNSUXSr
2664 101201263U, // FCVTNSv1f16
2665 101201263U, // FCVTNSv1i32
2666 101201263U, // FCVTNSv1i64
2667 2216744303U, // FCVTNSv2f32
2668 69784943U, // FCVTNSv2f64
2669 2217792879U, // FCVTNSv4f16
2670 70833519U, // FCVTNSv4f32
2671 2218841455U, // FCVTNSv8f16
2672 2148054897U, // FCVTNT_ZPmZ_DtoS
2673 571512689U, // FCVTNT_ZPmZ_StoH
2674 101201993U, // FCVTNUUWDr
2675 101201993U, // FCVTNUUWHr
2676 101201993U, // FCVTNUUWSr
2677 101201993U, // FCVTNUUXDr
2678 101201993U, // FCVTNUUXHr
2679 101201993U, // FCVTNUUXSr
2680 101201993U, // FCVTNUv1f16
2681 101201993U, // FCVTNUv1i32
2682 101201993U, // FCVTNUv1i64
2683 2216745033U, // FCVTNUv2f32
2684 69785673U, // FCVTNUv2f64
2685 2217793609U, // FCVTNUv4f16
2686 70834249U, // FCVTNUv4f32
2687 2218842185U, // FCVTNUv8f16
2688 69259697U, // FCVTNv2i32
2689 70308273U, // FCVTNv4i16
2690 339272097U, // FCVTNv4i32
2691 339796385U, // FCVTNv8i16
2692 101201286U, // FCVTPSUWDr
2693 101201286U, // FCVTPSUWHr
2694 101201286U, // FCVTPSUWSr
2695 101201286U, // FCVTPSUXDr
2696 101201286U, // FCVTPSUXHr
2697 101201286U, // FCVTPSUXSr
2698 101201286U, // FCVTPSv1f16
2699 101201286U, // FCVTPSv1i32
2700 101201286U, // FCVTPSv1i64
2701 2216744326U, // FCVTPSv2f32
2702 69784966U, // FCVTPSv2f64
2703 2217792902U, // FCVTPSv4f16
2704 70833542U, // FCVTPSv4f32
2705 2218841478U, // FCVTPSv8f16
2706 101202001U, // FCVTPUUWDr
2707 101202001U, // FCVTPUUWHr
2708 101202001U, // FCVTPUUWSr
2709 101202001U, // FCVTPUUXDr
2710 101202001U, // FCVTPUUXHr
2711 101202001U, // FCVTPUUXSr
2712 101202001U, // FCVTPUv1f16
2713 101202001U, // FCVTPUv1i32
2714 101202001U, // FCVTPUv1i64
2715 2216745041U, // FCVTPUv2f32
2716 69785681U, // FCVTPUv2f64
2717 2217793617U, // FCVTPUv4f16
2718 70834257U, // FCVTPUv4f32
2719 2218842193U, // FCVTPUv8f16
2720 101201918U, // FCVTSDr
2721 101201918U, // FCVTSHr
2722 2148054951U, // FCVTXNT_ZPmZ_DtoS
2723 101200359U, // FCVTXNv1i64
2724 69259751U, // FCVTXNv2f32
2725 339272151U, // FCVTXNv4f32
2726 2148055719U, // FCVTX_ZPmZ_DtoS
2727 2248684987U, // FCVTZSSWDri
2728 2248684987U, // FCVTZSSWHri
2729 2248684987U, // FCVTZSSWSri
2730 2248684987U, // FCVTZSSXDri
2731 2248684987U, // FCVTZSSXHri
2732 2248684987U, // FCVTZSSXSri
2733 101201339U, // FCVTZSUWDr
2734 101201339U, // FCVTZSUWHr
2735 101201339U, // FCVTZSUWSr
2736 101201339U, // FCVTZSUXDr
2737 101201339U, // FCVTZSUXHr
2738 101201339U, // FCVTZSUXSr
2739 2148038075U, // FCVTZS_ZPmZ_DtoD
2740 2148054459U, // FCVTZS_ZPmZ_DtoS
2741 2148038075U, // FCVTZS_ZPmZ_HtoD
2742 34641339U, // FCVTZS_ZPmZ_HtoH
2743 2148054459U, // FCVTZS_ZPmZ_HtoS
2744 554427U, // FCVTZS_ZPmZ_StoD
2745 570811U, // FCVTZS_ZPmZ_StoS
2746 2248684987U, // FCVTZSd
2747 2248684987U, // FCVTZSh
2748 2248684987U, // FCVTZSs
2749 101201339U, // FCVTZSv1f16
2750 101201339U, // FCVTZSv1i32
2751 101201339U, // FCVTZSv1i64
2752 2216744379U, // FCVTZSv2f32
2753 69785019U, // FCVTZSv2f64
2754 2216744379U, // FCVTZSv2i32_shift
2755 2217268667U, // FCVTZSv2i64_shift
2756 2217792955U, // FCVTZSv4f16
2757 70833595U, // FCVTZSv4f32
2758 70309307U, // FCVTZSv4i16_shift
2759 70833595U, // FCVTZSv4i32_shift
2760 2218841531U, // FCVTZSv8f16
2761 2218841531U, // FCVTZSv8i16_shift
2762 2248685657U, // FCVTZUSWDri
2763 2248685657U, // FCVTZUSWHri
2764 2248685657U, // FCVTZUSWSri
2765 2248685657U, // FCVTZUSXDri
2766 2248685657U, // FCVTZUSXHri
2767 2248685657U, // FCVTZUSXSri
2768 101202009U, // FCVTZUUWDr
2769 101202009U, // FCVTZUUWHr
2770 101202009U, // FCVTZUUWSr
2771 101202009U, // FCVTZUUXDr
2772 101202009U, // FCVTZUUXHr
2773 101202009U, // FCVTZUUXSr
2774 2148038745U, // FCVTZU_ZPmZ_DtoD
2775 2148055129U, // FCVTZU_ZPmZ_DtoS
2776 2148038745U, // FCVTZU_ZPmZ_HtoD
2777 34642009U, // FCVTZU_ZPmZ_HtoH
2778 2148055129U, // FCVTZU_ZPmZ_HtoS
2779 555097U, // FCVTZU_ZPmZ_StoD
2780 571481U, // FCVTZU_ZPmZ_StoS
2781 2248685657U, // FCVTZUd
2782 2248685657U, // FCVTZUh
2783 2248685657U, // FCVTZUs
2784 101202009U, // FCVTZUv1f16
2785 101202009U, // FCVTZUv1i32
2786 101202009U, // FCVTZUv1i64
2787 2216745049U, // FCVTZUv2f32
2788 69785689U, // FCVTZUv2f64
2789 2216745049U, // FCVTZUv2i32_shift
2790 2217269337U, // FCVTZUv2i64_shift
2791 2217793625U, // FCVTZUv4f16
2792 70834265U, // FCVTZUv4f32
2793 70309977U, // FCVTZUv4i16_shift
2794 70834265U, // FCVTZUv4i32_shift
2795 2218842201U, // FCVTZUv8f16
2796 2218842201U, // FCVTZUv8i16_shift
2797 1141938174U, // FCVT_ZPmZ_DtoH
2798 2148055038U, // FCVT_ZPmZ_DtoS
2799 2148038654U, // FCVT_ZPmZ_HtoD
2800 2148055038U, // FCVT_ZPmZ_HtoS
2801 555006U, // FCVT_ZPmZ_StoD
2802 571512830U, // FCVT_ZPmZ_StoH
2803 2248685705U, // FDIVDrr
2804 2248685705U, // FDIVHrr
2805 369652864U, // FDIVR_ZPmZ_D
2806 2556466304U, // FDIVR_ZPmZ_H
2807 369669248U, // FDIVR_ZPmZ_S
2808 2248685705U, // FDIVSrr
2809 369653897U, // FDIV_ZPmZ_D
2810 2556467337U, // FDIV_ZPmZ_H
2811 369670281U, // FDIV_ZPmZ_S
2812 2216745097U, // FDIVv2f32
2813 2217269385U, // FDIVv2f64
2814 70310025U, // FDIVv4f16
2815 70834313U, // FDIVv4f32
2816 2218842249U, // FDIVv8f16
2817 1174958827U, // FDUP_ZI_D
2818 13144811U, // FDUP_ZI_H
2819 1174975211U, // FDUP_ZI_S
2820 268985116U, // FEXPA_ZZ_D
2821 543720220U, // FEXPA_ZZ_H
2822 470328092U, // FEXPA_ZZ_S
2823 101201347U, // FJCVTZS
2824 2148033736U, // FLOGB_ZPmZ_D
2825 34637000U, // FLOGB_ZPmZ_H
2826 566472U, // FLOGB_ZPmZ_S
2827 2248681929U, // FMADDDrrr
2828 2248681929U, // FMADDHrrr
2829 2248681929U, // FMADDSrrr
2830 369649986U, // FMAD_ZPmZZ_D
2831 2556463426U, // FMAD_ZPmZZ_H
2832 369666370U, // FMAD_ZPmZZ_S
2833 2248686165U, // FMAXDrr
2834 2248686165U, // FMAXHrr
2835 2248683807U, // FMAXNMDrr
2836 2248683807U, // FMAXNMHrr
2837 369652380U, // FMAXNMP_ZPmZZ_D
2838 2556465820U, // FMAXNMP_ZPmZZ_H
2839 369668764U, // FMAXNMP_ZPmZZ_S
2840 2216743580U, // FMAXNMPv2f32
2841 2217267868U, // FMAXNMPv2f64
2842 67646108U, // FMAXNMPv2i16p
2843 2215129756U, // FMAXNMPv2i32p
2844 67646108U, // FMAXNMPv2i64p
2845 70308508U, // FMAXNMPv4f16
2846 70832796U, // FMAXNMPv4f32
2847 2218840732U, // FMAXNMPv8f16
2848 2248683807U, // FMAXNMSrr
2849 544815284U, // FMAXNMV_VPZ_D
2850 545347764U, // FMAXNMV_VPZ_H
2851 542734516U, // FMAXNMV_VPZ_S
2852 2215131316U, // FMAXNMVv4i16v
2853 67647668U, // FMAXNMVv4i32v
2854 2215131316U, // FMAXNMVv8i16v
2855 369651999U, // FMAXNM_ZPmI_D
2856 2556465439U, // FMAXNM_ZPmI_H
2857 369668383U, // FMAXNM_ZPmI_S
2858 369651999U, // FMAXNM_ZPmZ_D
2859 2556465439U, // FMAXNM_ZPmZ_H
2860 369668383U, // FMAXNM_ZPmZ_S
2861 2216743199U, // FMAXNMv2f32
2862 2217267487U, // FMAXNMv2f64
2863 70308127U, // FMAXNMv4f16
2864 70832415U, // FMAXNMv4f32
2865 2218840351U, // FMAXNMv8f16
2866 369652477U, // FMAXP_ZPmZZ_D
2867 2556465917U, // FMAXP_ZPmZZ_H
2868 369668861U, // FMAXP_ZPmZZ_S
2869 2216743677U, // FMAXPv2f32
2870 2217267965U, // FMAXPv2f64
2871 67646205U, // FMAXPv2i16p
2872 2215129853U, // FMAXPv2i32p
2873 67646205U, // FMAXPv2i64p
2874 70308605U, // FMAXPv4f16
2875 70832893U, // FMAXPv4f32
2876 2218840829U, // FMAXPv8f16
2877 2248686165U, // FMAXSrr
2878 544815345U, // FMAXV_VPZ_D
2879 545347825U, // FMAXV_VPZ_H
2880 542734577U, // FMAXV_VPZ_S
2881 2215131377U, // FMAXVv4i16v
2882 67647729U, // FMAXVv4i32v
2883 2215131377U, // FMAXVv8i16v
2884 369654357U, // FMAX_ZPmI_D
2885 2556467797U, // FMAX_ZPmI_H
2886 369670741U, // FMAX_ZPmI_S
2887 369654357U, // FMAX_ZPmZ_D
2888 2556467797U, // FMAX_ZPmZ_H
2889 369670741U, // FMAX_ZPmZ_S
2890 2216745557U, // FMAXv2f32
2891 2217269845U, // FMAXv2f64
2892 70310485U, // FMAXv4f16
2893 70834773U, // FMAXv4f32
2894 2218842709U, // FMAXv8f16
2895 2248683866U, // FMINDrr
2896 2248683866U, // FMINHrr
2897 2248683799U, // FMINNMDrr
2898 2248683799U, // FMINNMHrr
2899 369652371U, // FMINNMP_ZPmZZ_D
2900 2556465811U, // FMINNMP_ZPmZZ_H
2901 369668755U, // FMINNMP_ZPmZZ_S
2902 2216743571U, // FMINNMPv2f32
2903 2217267859U, // FMINNMPv2f64
2904 67646099U, // FMINNMPv2i16p
2905 2215129747U, // FMINNMPv2i32p
2906 67646099U, // FMINNMPv2i64p
2907 70308499U, // FMINNMPv4f16
2908 70832787U, // FMINNMPv4f32
2909 2218840723U, // FMINNMPv8f16
2910 2248683799U, // FMINNMSrr
2911 544815275U, // FMINNMV_VPZ_D
2912 545347755U, // FMINNMV_VPZ_H
2913 542734507U, // FMINNMV_VPZ_S
2914 2215131307U, // FMINNMVv4i16v
2915 67647659U, // FMINNMVv4i32v
2916 2215131307U, // FMINNMVv8i16v
2917 369651991U, // FMINNM_ZPmI_D
2918 2556465431U, // FMINNM_ZPmI_H
2919 369668375U, // FMINNM_ZPmI_S
2920 369651991U, // FMINNM_ZPmZ_D
2921 2556465431U, // FMINNM_ZPmZ_H
2922 369668375U, // FMINNM_ZPmZ_S
2923 2216743191U, // FMINNMv2f32
2924 2217267479U, // FMINNMv2f64
2925 70308119U, // FMINNMv4f16
2926 70832407U, // FMINNMv4f32
2927 2218840343U, // FMINNMv8f16
2928 369652395U, // FMINP_ZPmZZ_D
2929 2556465835U, // FMINP_ZPmZZ_H
2930 369668779U, // FMINP_ZPmZZ_S
2931 2216743595U, // FMINPv2f32
2932 2217267883U, // FMINPv2f64
2933 67646123U, // FMINPv2i16p
2934 2215129771U, // FMINPv2i32p
2935 67646123U, // FMINPv2i64p
2936 70308523U, // FMINPv4f16
2937 70832811U, // FMINPv4f32
2938 2218840747U, // FMINPv8f16
2939 2248683866U, // FMINSrr
2940 544815293U, // FMINV_VPZ_D
2941 545347773U, // FMINV_VPZ_H
2942 542734525U, // FMINV_VPZ_S
2943 2215131325U, // FMINVv4i16v
2944 67647677U, // FMINVv4i32v
2945 2215131325U, // FMINVv8i16v
2946 369652058U, // FMIN_ZPmI_D
2947 2556465498U, // FMIN_ZPmI_H
2948 369668442U, // FMIN_ZPmI_S
2949 369652058U, // FMIN_ZPmZ_D
2950 2556465498U, // FMIN_ZPmZ_H
2951 369668442U, // FMIN_ZPmZ_S
2952 2216743258U, // FMINv2f32
2953 2217267546U, // FMINv2f64
2954 70308186U, // FMINv4f16
2955 70832474U, // FMINv4f32
2956 2218840410U, // FMINv8f16
2957 337699006U, // FMLAL2lanev4f16
2958 339271870U, // FMLAL2lanev8f16
2959 337699006U, // FMLAL2v4f16
2960 339271870U, // FMLAL2v8f16
2961 2450040072U, // FMLALB_ZZZI_SHH
2962 2450040072U, // FMLALB_ZZZ_SHH
2963 2450044507U, // FMLALT_ZZZI_SHH
2964 2450044507U, // FMLALT_ZZZ_SHH
2965 337702651U, // FMLALlanev4f16
2966 339275515U, // FMLALlanev8f16
2967 337702651U, // FMLALv4f16
2968 339275515U, // FMLALv8f16
2969 369648338U, // FMLA_ZPmZZ_D
2970 2556461778U, // FMLA_ZPmZZ_H
2971 369664722U, // FMLA_ZPmZZ_S
2972 2282250962U, // FMLA_ZZZI_D
2973 2390786770U, // FMLA_ZZZI_H
2974 2315821778U, // FMLA_ZZZI_S
2975 2752111314U, // FMLAv1i16_indexed
2976 2752111314U, // FMLAv1i32_indexed
2977 2752111314U, // FMLAv1i64_indexed
2978 2485183186U, // FMLAv2f32
2979 2485707474U, // FMLAv2f64
2980 2485183186U, // FMLAv2i32_indexed
2981 2485707474U, // FMLAv2i64_indexed
2982 338748114U, // FMLAv4f16
2983 339272402U, // FMLAv4f32
2984 338748114U, // FMLAv4i16_indexed
2985 339272402U, // FMLAv4i32_indexed
2986 2487280338U, // FMLAv8f16
2987 2487280338U, // FMLAv8i16_indexed
2988 337699138U, // FMLSL2lanev4f16
2989 339272002U, // FMLSL2lanev8f16
2990 337699138U, // FMLSL2v4f16
2991 339272002U, // FMLSL2v8f16
2992 2450040369U, // FMLSLB_ZZZI_SHH
2993 2450040369U, // FMLSLB_ZZZ_SHH
2994 2450044681U, // FMLSLT_ZZZI_SHH
2995 2450044681U, // FMLSLT_ZZZ_SHH
2996 337703047U, // FMLSLlanev4f16
2997 339275911U, // FMLSLlanev8f16
2998 337703047U, // FMLSLv4f16
2999 339275911U, // FMLSLv8f16
3000 369653057U, // FMLS_ZPmZZ_D
3001 2556466497U, // FMLS_ZPmZZ_H
3002 369669441U, // FMLS_ZPmZZ_S
3003 2282255681U, // FMLS_ZZZI_D
3004 2390791489U, // FMLS_ZZZI_H
3005 2315826497U, // FMLS_ZZZI_S
3006 2752116033U, // FMLSv1i16_indexed
3007 2752116033U, // FMLSv1i32_indexed
3008 2752116033U, // FMLSv1i64_indexed
3009 2485187905U, // FMLSv2f32
3010 2485712193U, // FMLSv2f64
3011 2485187905U, // FMLSv2i32_indexed
3012 2485712193U, // FMLSv2i64_indexed
3013 338752833U, // FMLSv4f16
3014 339277121U, // FMLSv4f32
3015 338752833U, // FMLSv4i16_indexed
3016 339277121U, // FMLSv4i32_indexed
3017 2487285057U, // FMLSv8f16
3018 2487285057U, // FMLSv8i16_indexed
3019 2282250969U, // FMMLA_ZZZ_D
3020 2315821785U, // FMMLA_ZZZ_S
3021 67647705U, // FMOVDXHighr
3022 101202137U, // FMOVDXr
3023 1174943961U, // FMOVDi
3024 101202137U, // FMOVDr
3025 101202137U, // FMOVHWr
3026 101202137U, // FMOVHXr
3027 1174943961U, // FMOVHi
3028 101202137U, // FMOVHr
3029 101202137U, // FMOVSWr
3030 1174943961U, // FMOVSi
3031 101202137U, // FMOVSr
3032 101202137U, // FMOVWHr
3033 101202137U, // FMOVWSr
3034 114350297U, // FMOVXDHighr
3035 101202137U, // FMOVXDr
3036 101202137U, // FMOVXHr
3037 1176557785U, // FMOVv2f32_ns
3038 1177082073U, // FMOVv2f64_ns
3039 1177606361U, // FMOVv4f16_ns
3040 1178130649U, // FMOVv4f32_ns
3041 1178654937U, // FMOVv8f16_ns
3042 369649606U, // FMSB_ZPmZZ_D
3043 2556463046U, // FMSB_ZPmZZ_H
3044 369665990U, // FMSB_ZPmZZ_S
3045 2248681543U, // FMSUBDrrr
3046 2248681543U, // FMSUBHrrr
3047 2248681543U, // FMSUBSrrr
3048 2248683697U, // FMULDrr
3049 2248683697U, // FMULHrr
3050 2248683697U, // FMULSrr
3051 2248686224U, // FMULX16
3052 2248686224U, // FMULX32
3053 2248686224U, // FMULX64
3054 369654416U, // FMULX_ZPmZ_D
3055 2556467856U, // FMULX_ZPmZ_H
3056 369670800U, // FMULX_ZPmZ_S
3057 2248686224U, // FMULXv1i16_indexed
3058 2248686224U, // FMULXv1i32_indexed
3059 2248686224U, // FMULXv1i64_indexed
3060 2216745616U, // FMULXv2f32
3061 2217269904U, // FMULXv2f64
3062 2216745616U, // FMULXv2i32_indexed
3063 2217269904U, // FMULXv2i64_indexed
3064 70310544U, // FMULXv4f16
3065 70834832U, // FMULXv4f32
3066 70310544U, // FMULXv4i16_indexed
3067 70834832U, // FMULXv4i32_indexed
3068 2218842768U, // FMULXv8f16
3069 2218842768U, // FMULXv8i16_indexed
3070 369651889U, // FMUL_ZPmI_D
3071 2556465329U, // FMUL_ZPmI_H
3072 369668273U, // FMUL_ZPmI_S
3073 369651889U, // FMUL_ZPmZ_D
3074 2556465329U, // FMUL_ZPmZ_H
3075 369668273U, // FMUL_ZPmZ_S
3076 2416472241U, // FMUL_ZZZI_D
3077 2389217457U, // FMUL_ZZZI_H
3078 2617815217U, // FMUL_ZZZI_S
3079 2416472241U, // FMUL_ZZZ_D
3080 2389217457U, // FMUL_ZZZ_H
3081 2617815217U, // FMUL_ZZZ_S
3082 2248683697U, // FMULv1i16_indexed
3083 2248683697U, // FMULv1i32_indexed
3084 2248683697U, // FMULv1i64_indexed
3085 2216743089U, // FMULv2f32
3086 2217267377U, // FMULv2f64
3087 2216743089U, // FMULv2i32_indexed
3088 2217267377U, // FMULv2i64_indexed
3089 70308017U, // FMULv4f16
3090 70832305U, // FMULv4f32
3091 70308017U, // FMULv4i16_indexed
3092 70832305U, // FMULv4i32_indexed
3093 2218840241U, // FMULv8f16
3094 2218840241U, // FMULv8i16_indexed
3095 101198593U, // FNEGDr
3096 101198593U, // FNEGHr
3097 101198593U, // FNEGSr
3098 2148035329U, // FNEG_ZPmZ_D
3099 34638593U, // FNEG_ZPmZ_H
3100 568065U, // FNEG_ZPmZ_S
3101 2216741633U, // FNEGv2f32
3102 69782273U, // FNEGv2f64
3103 2217790209U, // FNEGv4f16
3104 70830849U, // FNEGv4f32
3105 2218838785U, // FNEGv8f16
3106 2248681936U, // FNMADDDrrr
3107 2248681936U, // FNMADDHrrr
3108 2248681936U, // FNMADDSrrr
3109 369649992U, // FNMAD_ZPmZZ_D
3110 2556463432U, // FNMAD_ZPmZZ_H
3111 369666376U, // FNMAD_ZPmZZ_S
3112 369648367U, // FNMLA_ZPmZZ_D
3113 2556461807U, // FNMLA_ZPmZZ_H
3114 369664751U, // FNMLA_ZPmZZ_S
3115 369653063U, // FNMLS_ZPmZZ_D
3116 2556466503U, // FNMLS_ZPmZZ_H
3117 369669447U, // FNMLS_ZPmZZ_S
3118 369649612U, // FNMSB_ZPmZZ_D
3119 2556463052U, // FNMSB_ZPmZZ_H
3120 369665996U, // FNMSB_ZPmZZ_S
3121 2248681550U, // FNMSUBDrrr
3122 2248681550U, // FNMSUBHrrr
3123 2248681550U, // FNMSUBSrrr
3124 2248683703U, // FNMULDrr
3125 2248683703U, // FNMULHrr
3126 2248683703U, // FNMULSrr
3127 268987007U, // FRECPE_ZZ_D
3128 543722111U, // FRECPE_ZZ_H
3129 470329983U, // FRECPE_ZZ_S
3130 101198463U, // FRECPEv1f16
3131 101198463U, // FRECPEv1i32
3132 101198463U, // FRECPEv1i64
3133 2216741503U, // FRECPEv2f32
3134 69782143U, // FRECPEv2f64
3135 2217790079U, // FRECPEv4f16
3136 70830719U, // FRECPEv4f32
3137 2218838655U, // FRECPEv8f16
3138 2248684926U, // FRECPS16
3139 2248684926U, // FRECPS32
3140 2248684926U, // FRECPS64
3141 2416473470U, // FRECPS_ZZZ_D
3142 2389218686U, // FRECPS_ZZZ_H
3143 2617816446U, // FRECPS_ZZZ_S
3144 2216744318U, // FRECPSv2f32
3145 2217268606U, // FRECPSv2f64
3146 70309246U, // FRECPSv4f16
3147 70833534U, // FRECPSv4f32
3148 2218841470U, // FRECPSv8f16
3149 2148039319U, // FRECPX_ZPmZ_D
3150 34642583U, // FRECPX_ZPmZ_H
3151 572055U, // FRECPX_ZPmZ_S
3152 101202583U, // FRECPXv1f16
3153 101202583U, // FRECPXv1i32
3154 101202583U, // FRECPXv1i64
3155 101202491U, // FRINT32XDr
3156 101202491U, // FRINT32XSr
3157 2216745531U, // FRINT32Xv2f32
3158 69786171U, // FRINT32Xv2f64
3159 70834747U, // FRINT32Xv4f32
3160 101202621U, // FRINT32ZDr
3161 101202621U, // FRINT32ZSr
3162 2216745661U, // FRINT32Zv2f32
3163 69786301U, // FRINT32Zv2f64
3164 70834877U, // FRINT32Zv4f32
3165 101202501U, // FRINT64XDr
3166 101202501U, // FRINT64XSr
3167 2216745541U, // FRINT64Xv2f32
3168 69786181U, // FRINT64Xv2f64
3169 70834757U, // FRINT64Xv4f32
3170 101202631U, // FRINT64ZDr
3171 101202631U, // FRINT64ZSr
3172 2216745671U, // FRINT64Zv2f32
3173 69786311U, // FRINT64Zv2f64
3174 70834887U, // FRINT64Zv4f32
3175 101196635U, // FRINTADr
3176 101196635U, // FRINTAHr
3177 101196635U, // FRINTASr
3178 2148033371U, // FRINTA_ZPmZ_D
3179 34636635U, // FRINTA_ZPmZ_H
3180 566107U, // FRINTA_ZPmZ_S
3181 2216739675U, // FRINTAv2f32
3182 69780315U, // FRINTAv2f64
3183 2217788251U, // FRINTAv4f16
3184 70828891U, // FRINTAv4f32
3185 2218836827U, // FRINTAv8f16
3186 101199554U, // FRINTIDr
3187 101199554U, // FRINTIHr
3188 101199554U, // FRINTISr
3189 2148036290U, // FRINTI_ZPmZ_D
3190 34639554U, // FRINTI_ZPmZ_H
3191 569026U, // FRINTI_ZPmZ_S
3192 2216742594U, // FRINTIv2f32
3193 69783234U, // FRINTIv2f64
3194 2217791170U, // FRINTIv4f16
3195 70831810U, // FRINTIv4f32
3196 2218839746U, // FRINTIv8f16
3197 101200173U, // FRINTMDr
3198 101200173U, // FRINTMHr
3199 101200173U, // FRINTMSr
3200 2148036909U, // FRINTM_ZPmZ_D
3201 34640173U, // FRINTM_ZPmZ_H
3202 569645U, // FRINTM_ZPmZ_S
3203 2216743213U, // FRINTMv2f32
3204 69783853U, // FRINTMv2f64
3205 2217791789U, // FRINTMv4f16
3206 70832429U, // FRINTMv4f32
3207 2218840365U, // FRINTMv8f16
3208 101200296U, // FRINTNDr
3209 101200296U, // FRINTNHr
3210 101200296U, // FRINTNSr
3211 2148037032U, // FRINTN_ZPmZ_D
3212 34640296U, // FRINTN_ZPmZ_H
3213 569768U, // FRINTN_ZPmZ_S
3214 2216743336U, // FRINTNv2f32
3215 69783976U, // FRINTNv2f64
3216 2217791912U, // FRINTNv4f16
3217 70832552U, // FRINTNv4f32
3218 2218840488U, // FRINTNv8f16
3219 101200606U, // FRINTPDr
3220 101200606U, // FRINTPHr
3221 101200606U, // FRINTPSr
3222 2148037342U, // FRINTP_ZPmZ_D
3223 34640606U, // FRINTP_ZPmZ_H
3224 570078U, // FRINTP_ZPmZ_S
3225 2216743646U, // FRINTPv2f32
3226 69784286U, // FRINTPv2f64
3227 2217792222U, // FRINTPv4f16
3228 70832862U, // FRINTPv4f32
3229 2218840798U, // FRINTPv8f16
3230 101202591U, // FRINTXDr
3231 101202591U, // FRINTXHr
3232 101202591U, // FRINTXSr
3233 2148039327U, // FRINTX_ZPmZ_D
3234 34642591U, // FRINTX_ZPmZ_H
3235 572063U, // FRINTX_ZPmZ_S
3236 2216745631U, // FRINTXv2f32
3237 69786271U, // FRINTXv2f64
3238 2217794207U, // FRINTXv4f16
3239 70834847U, // FRINTXv4f32
3240 2218842783U, // FRINTXv8f16
3241 101202698U, // FRINTZDr
3242 101202698U, // FRINTZHr
3243 101202698U, // FRINTZSr
3244 2148039434U, // FRINTZ_ZPmZ_D
3245 34642698U, // FRINTZ_ZPmZ_H
3246 572170U, // FRINTZ_ZPmZ_S
3247 2216745738U, // FRINTZv2f32
3248 69786378U, // FRINTZv2f64
3249 2217794314U, // FRINTZv4f16
3250 70834954U, // FRINTZv4f32
3251 2218842890U, // FRINTZv8f16
3252 268987052U, // FRSQRTE_ZZ_D
3253 543722156U, // FRSQRTE_ZZ_H
3254 470330028U, // FRSQRTE_ZZ_S
3255 101198508U, // FRSQRTEv1f16
3256 101198508U, // FRSQRTEv1i32
3257 101198508U, // FRSQRTEv1i64
3258 2216741548U, // FRSQRTEv2f32
3259 69782188U, // FRSQRTEv2f64
3260 2217790124U, // FRSQRTEv4f16
3261 70830764U, // FRSQRTEv4f32
3262 2218838700U, // FRSQRTEv8f16
3263 2248684973U, // FRSQRTS16
3264 2248684973U, // FRSQRTS32
3265 2248684973U, // FRSQRTS64
3266 2416473517U, // FRSQRTS_ZZZ_D
3267 2389218733U, // FRSQRTS_ZZZ_H
3268 2617816493U, // FRSQRTS_ZZZ_S
3269 2216744365U, // FRSQRTSv2f32
3270 2217268653U, // FRSQRTSv2f64
3271 70309293U, // FRSQRTSv4f16
3272 70833581U, // FRSQRTSv4f32
3273 2218841517U, // FRSQRTSv8f16
3274 369650249U, // FSCALE_ZPmZ_D
3275 2556463689U, // FSCALE_ZPmZ_H
3276 369666633U, // FSCALE_ZPmZ_S
3277 101201881U, // FSQRTDr
3278 101201881U, // FSQRTHr
3279 101201881U, // FSQRTSr
3280 2148038617U, // FSQRT_ZPmZ_D
3281 34641881U, // FSQRT_ZPmZ_H
3282 571353U, // FSQRT_ZPmZ_S
3283 2216744921U, // FSQRTv2f32
3284 69785561U, // FSQRTv2f64
3285 2217793497U, // FSQRTv4f16
3286 70834137U, // FSQRTv4f32
3287 2218842073U, // FSQRTv8f16
3288 2248681523U, // FSUBDrr
3289 2248681523U, // FSUBHrr
3290 369652582U, // FSUBR_ZPmI_D
3291 2556466022U, // FSUBR_ZPmI_H
3292 369668966U, // FSUBR_ZPmI_S
3293 369652582U, // FSUBR_ZPmZ_D
3294 2556466022U, // FSUBR_ZPmZ_H
3295 369668966U, // FSUBR_ZPmZ_S
3296 2248681523U, // FSUBSrr
3297 369649715U, // FSUB_ZPmI_D
3298 2556463155U, // FSUB_ZPmI_H
3299 369666099U, // FSUB_ZPmI_S
3300 369649715U, // FSUB_ZPmZ_D
3301 2556463155U, // FSUB_ZPmZ_H
3302 369666099U, // FSUB_ZPmZ_S
3303 2416470067U, // FSUB_ZZZ_D
3304 2389215283U, // FSUB_ZZZ_H
3305 2617813043U, // FSUB_ZZZ_S
3306 2216740915U, // FSUBv2f32
3307 2217265203U, // FSUBv2f64
3308 70305843U, // FSUBv4f16
3309 70830131U, // FSUBv4f32
3310 2218838067U, // FSUBv8f16
3311 2416470351U, // FTMAD_ZZI_D
3312 2389215567U, // FTMAD_ZZI_H
3313 2617813327U, // FTMAD_ZZI_S
3314 2416472260U, // FTSMUL_ZZZ_D
3315 2389217476U, // FTSMUL_ZZZ_H
3316 2617815236U, // FTSMUL_ZZZ_S
3317 2416472016U, // FTSSEL_ZZZ_D
3318 2389217232U, // FTSSEL_ZZZ_H
3319 2617814992U, // FTSSEL_ZZZ_S
3320 2296030109U, // GLD1B_D_IMM_REAL
3321 2765792157U, // GLD1B_D_REAL
3322 2765792157U, // GLD1B_D_SXTW_REAL
3323 2765792157U, // GLD1B_D_UXTW_REAL
3324 2329592733U, // GLD1B_S_IMM_REAL
3325 2765800349U, // GLD1B_S_SXTW_REAL
3326 2765800349U, // GLD1B_S_UXTW_REAL
3327 2296031474U, // GLD1D_IMM_REAL
3328 2765793522U, // GLD1D_REAL
3329 2765793522U, // GLD1D_SCALED_REAL
3330 2765793522U, // GLD1D_SXTW_REAL
3331 2765793522U, // GLD1D_SXTW_SCALED_REAL
3332 2765793522U, // GLD1D_UXTW_REAL
3333 2765793522U, // GLD1D_UXTW_SCALED_REAL
3334 2296032053U, // GLD1H_D_IMM_REAL
3335 2765794101U, // GLD1H_D_REAL
3336 2765794101U, // GLD1H_D_SCALED_REAL
3337 2765794101U, // GLD1H_D_SXTW_REAL
3338 2765794101U, // GLD1H_D_SXTW_SCALED_REAL
3339 2765794101U, // GLD1H_D_UXTW_REAL
3340 2765794101U, // GLD1H_D_UXTW_SCALED_REAL
3341 2329594677U, // GLD1H_S_IMM_REAL
3342 2765802293U, // GLD1H_S_SXTW_REAL
3343 2765802293U, // GLD1H_S_SXTW_SCALED_REAL
3344 2765802293U, // GLD1H_S_UXTW_REAL
3345 2765802293U, // GLD1H_S_UXTW_SCALED_REAL
3346 2296031124U, // GLD1SB_D_IMM_REAL
3347 2765793172U, // GLD1SB_D_REAL
3348 2765793172U, // GLD1SB_D_SXTW_REAL
3349 2765793172U, // GLD1SB_D_UXTW_REAL
3350 2329593748U, // GLD1SB_S_IMM_REAL
3351 2765801364U, // GLD1SB_S_SXTW_REAL
3352 2765801364U, // GLD1SB_S_UXTW_REAL
3353 2296032744U, // GLD1SH_D_IMM_REAL
3354 2765794792U, // GLD1SH_D_REAL
3355 2765794792U, // GLD1SH_D_SCALED_REAL
3356 2765794792U, // GLD1SH_D_SXTW_REAL
3357 2765794792U, // GLD1SH_D_SXTW_SCALED_REAL
3358 2765794792U, // GLD1SH_D_UXTW_REAL
3359 2765794792U, // GLD1SH_D_UXTW_SCALED_REAL
3360 2329595368U, // GLD1SH_S_IMM_REAL
3361 2765802984U, // GLD1SH_S_SXTW_REAL
3362 2765802984U, // GLD1SH_S_SXTW_SCALED_REAL
3363 2765802984U, // GLD1SH_S_UXTW_REAL
3364 2765802984U, // GLD1SH_S_UXTW_SCALED_REAL
3365 2296035785U, // GLD1SW_D_IMM_REAL
3366 2765797833U, // GLD1SW_D_REAL
3367 2765797833U, // GLD1SW_D_SCALED_REAL
3368 2765797833U, // GLD1SW_D_SXTW_REAL
3369 2765797833U, // GLD1SW_D_SXTW_SCALED_REAL
3370 2765797833U, // GLD1SW_D_UXTW_REAL
3371 2765797833U, // GLD1SW_D_UXTW_SCALED_REAL
3372 2296035590U, // GLD1W_D_IMM_REAL
3373 2765797638U, // GLD1W_D_REAL
3374 2765797638U, // GLD1W_D_SCALED_REAL
3375 2765797638U, // GLD1W_D_SXTW_REAL
3376 2765797638U, // GLD1W_D_SXTW_SCALED_REAL
3377 2765797638U, // GLD1W_D_UXTW_REAL
3378 2765797638U, // GLD1W_D_UXTW_SCALED_REAL
3379 2329598214U, // GLD1W_IMM_REAL
3380 2765805830U, // GLD1W_SXTW_REAL
3381 2765805830U, // GLD1W_SXTW_SCALED_REAL
3382 2765805830U, // GLD1W_UXTW_REAL
3383 2765805830U, // GLD1W_UXTW_SCALED_REAL
3384 2296030115U, // GLDFF1B_D_IMM_REAL
3385 2765792163U, // GLDFF1B_D_REAL
3386 2765792163U, // GLDFF1B_D_SXTW_REAL
3387 2765792163U, // GLDFF1B_D_UXTW_REAL
3388 2329592739U, // GLDFF1B_S_IMM_REAL
3389 2765800355U, // GLDFF1B_S_SXTW_REAL
3390 2765800355U, // GLDFF1B_S_UXTW_REAL
3391 2296031480U, // GLDFF1D_IMM_REAL
3392 2765793528U, // GLDFF1D_REAL
3393 2765793528U, // GLDFF1D_SCALED_REAL
3394 2765793528U, // GLDFF1D_SXTW_REAL
3395 2765793528U, // GLDFF1D_SXTW_SCALED_REAL
3396 2765793528U, // GLDFF1D_UXTW_REAL
3397 2765793528U, // GLDFF1D_UXTW_SCALED_REAL
3398 2296032059U, // GLDFF1H_D_IMM_REAL
3399 2765794107U, // GLDFF1H_D_REAL
3400 2765794107U, // GLDFF1H_D_SCALED_REAL
3401 2765794107U, // GLDFF1H_D_SXTW_REAL
3402 2765794107U, // GLDFF1H_D_SXTW_SCALED_REAL
3403 2765794107U, // GLDFF1H_D_UXTW_REAL
3404 2765794107U, // GLDFF1H_D_UXTW_SCALED_REAL
3405 2329594683U, // GLDFF1H_S_IMM_REAL
3406 2765802299U, // GLDFF1H_S_SXTW_REAL
3407 2765802299U, // GLDFF1H_S_SXTW_SCALED_REAL
3408 2765802299U, // GLDFF1H_S_UXTW_REAL
3409 2765802299U, // GLDFF1H_S_UXTW_SCALED_REAL
3410 2296031131U, // GLDFF1SB_D_IMM_REAL
3411 2765793179U, // GLDFF1SB_D_REAL
3412 2765793179U, // GLDFF1SB_D_SXTW_REAL
3413 2765793179U, // GLDFF1SB_D_UXTW_REAL
3414 2329593755U, // GLDFF1SB_S_IMM_REAL
3415 2765801371U, // GLDFF1SB_S_SXTW_REAL
3416 2765801371U, // GLDFF1SB_S_UXTW_REAL
3417 2296032751U, // GLDFF1SH_D_IMM_REAL
3418 2765794799U, // GLDFF1SH_D_REAL
3419 2765794799U, // GLDFF1SH_D_SCALED_REAL
3420 2765794799U, // GLDFF1SH_D_SXTW_REAL
3421 2765794799U, // GLDFF1SH_D_SXTW_SCALED_REAL
3422 2765794799U, // GLDFF1SH_D_UXTW_REAL
3423 2765794799U, // GLDFF1SH_D_UXTW_SCALED_REAL
3424 2329595375U, // GLDFF1SH_S_IMM_REAL
3425 2765802991U, // GLDFF1SH_S_SXTW_REAL
3426 2765802991U, // GLDFF1SH_S_SXTW_SCALED_REAL
3427 2765802991U, // GLDFF1SH_S_UXTW_REAL
3428 2765802991U, // GLDFF1SH_S_UXTW_SCALED_REAL
3429 2296035792U, // GLDFF1SW_D_IMM_REAL
3430 2765797840U, // GLDFF1SW_D_REAL
3431 2765797840U, // GLDFF1SW_D_SCALED_REAL
3432 2765797840U, // GLDFF1SW_D_SXTW_REAL
3433 2765797840U, // GLDFF1SW_D_SXTW_SCALED_REAL
3434 2765797840U, // GLDFF1SW_D_UXTW_REAL
3435 2765797840U, // GLDFF1SW_D_UXTW_SCALED_REAL
3436 2296035596U, // GLDFF1W_D_IMM_REAL
3437 2765797644U, // GLDFF1W_D_REAL
3438 2765797644U, // GLDFF1W_D_SCALED_REAL
3439 2765797644U, // GLDFF1W_D_SXTW_REAL
3440 2765797644U, // GLDFF1W_D_SXTW_SCALED_REAL
3441 2765797644U, // GLDFF1W_D_UXTW_REAL
3442 2765797644U, // GLDFF1W_D_UXTW_SCALED_REAL
3443 2329598220U, // GLDFF1W_IMM_REAL
3444 2765805836U, // GLDFF1W_SXTW_REAL
3445 2765805836U, // GLDFF1W_SXTW_SCALED_REAL
3446 2765805836U, // GLDFF1W_UXTW_REAL
3447 2765805836U, // GLDFF1W_UXTW_SCALED_REAL
3448 2248683186U, // GMI
3449 194372U, // HINT
3450 2517137193U, // HISTCNT_ZPzZZ_D
3451 2517153577U, // HISTCNT_ZPzZZ_S
3452 2584234773U, // HISTSEG_ZZZ
3453 112314U, // HLT
3454 108776U, // HVC
3455 872948894U, // INCB_XPiI
3456 872950145U, // INCD_XPiI
3457 872966529U, // INCD_ZPiI
3458 872950825U, // INCH_XPiI
3459 8948777U, // INCH_ZPiI
3460 436744768U, // INCP_XP_B
3461 268972608U, // INCP_XP_D
3462 201863744U, // INCP_XP_H
3463 470299200U, // INCP_XP_S
3464 134771264U, // INCP_ZP_D
3465 545296960U, // INCP_ZP_H
3466 168342080U, // INCP_ZP_S
3467 872954247U, // INCW_XPiI
3468 872987015U, // INCW_ZPiI
3469 3355990649U, // INDEX_II_B
3470 2248702585U, // INDEX_II_D
3471 1256233593U, // INDEX_II_H
3472 2248718969U, // INDEX_II_S
3473 3355990649U, // INDEX_IR_B
3474 2248702585U, // INDEX_IR_D
3475 618699385U, // INDEX_IR_H
3476 2248718969U, // INDEX_IR_S
3477 2248694393U, // INDEX_RI_B
3478 2248702585U, // INDEX_RI_D
3479 244882041U, // INDEX_RI_H
3480 2248718969U, // INDEX_RI_S
3481 2248694393U, // INDEX_RR_B
3482 2248702585U, // INDEX_RR_D
3483 2392365689U, // INDEX_RR_H
3484 2248718969U, // INDEX_RR_S
3485 604525640U, // INSR_ZR_B
3486 604533832U, // INSR_ZR_D
3487 552113224U, // INSR_ZR_H
3488 604550216U, // INSR_ZR_S
3489 604525640U, // INSR_ZV_B
3490 604533832U, // INSR_ZV_D
3491 552113224U, // INSR_ZV_H
3492 604550216U, // INSR_ZV_S
3493 854652253U, // INSvi16gpr
3494 1290859869U, // INSvi16lane
3495 855176541U, // INSvi32gpr
3496 3438867805U, // INSvi32lane
3497 852555101U, // INSvi64gpr
3498 1288762717U, // INSvi64lane
3499 855700829U, // INSvi8gpr
3500 3439392093U, // INSvi8lane
3501 2248682270U, // IRG
3502 149441U, // ISB
3503 2517115748U, // LASTA_RPZ_B
3504 2517115748U, // LASTA_RPZ_D
3505 2517115748U, // LASTA_RPZ_H
3506 2517115748U, // LASTA_RPZ_S
3507 2517115748U, // LASTA_VPZ_B
3508 2517115748U, // LASTA_VPZ_D
3509 2517115748U, // LASTA_VPZ_H
3510 2517115748U, // LASTA_VPZ_S
3511 2517116960U, // LASTB_RPZ_B
3512 2517116960U, // LASTB_RPZ_D
3513 2517116960U, // LASTB_RPZ_H
3514 2517116960U, // LASTB_RPZ_S
3515 2517116960U, // LASTB_VPZ_B
3516 2517116960U, // LASTB_VPZ_D
3517 2517116960U, // LASTB_VPZ_H
3518 2517116960U, // LASTB_VPZ_S
3519 2765816733U, // LD1B
3520 2765792157U, // LD1B_D
3521 2765792157U, // LD1B_D_IMM_REAL
3522 2765824925U, // LD1B_H
3523 2765824925U, // LD1B_H_IMM_REAL
3524 2765816733U, // LD1B_IMM_REAL
3525 2765800349U, // LD1B_S
3526 2765800349U, // LD1B_S_IMM_REAL
3527 2765793522U, // LD1D
3528 2765793522U, // LD1D_IMM_REAL
3529 213033U, // LD1Fourv16b
3530 17522729U, // LD1Fourv16b_POST
3531 229417U, // LD1Fourv1d
3532 18063401U, // LD1Fourv1d_POST
3533 245801U, // LD1Fourv2d
3534 17555497U, // LD1Fourv2d_POST
3535 262185U, // LD1Fourv2s
3536 18096169U, // LD1Fourv2s_POST
3537 278569U, // LD1Fourv4h
3538 18112553U, // LD1Fourv4h_POST
3539 294953U, // LD1Fourv4s
3540 17604649U, // LD1Fourv4s_POST
3541 311337U, // LD1Fourv8b
3542 18145321U, // LD1Fourv8b_POST
3543 327721U, // LD1Fourv8h
3544 17637417U, // LD1Fourv8h_POST
3545 2765826869U, // LD1H
3546 2765794101U, // LD1H_D
3547 2765794101U, // LD1H_D_IMM_REAL
3548 2765826869U, // LD1H_IMM_REAL
3549 2765802293U, // LD1H_S
3550 2765802293U, // LD1H_S_IMM_REAL
3551 213033U, // LD1Onev16b
3552 18571305U, // LD1Onev16b_POST
3553 229417U, // LD1Onev1d
3554 19111977U, // LD1Onev1d_POST
3555 245801U, // LD1Onev2d
3556 18604073U, // LD1Onev2d_POST
3557 262185U, // LD1Onev2s
3558 19144745U, // LD1Onev2s_POST
3559 278569U, // LD1Onev4h
3560 19161129U, // LD1Onev4h_POST
3561 294953U, // LD1Onev4s
3562 18653225U, // LD1Onev4s_POST
3563 311337U, // LD1Onev8b
3564 19193897U, // LD1Onev8b_POST
3565 327721U, // LD1Onev8h
3566 18685993U, // LD1Onev8h_POST
3567 2765793024U, // LD1RB_D_IMM
3568 2765825792U, // LD1RB_H_IMM
3569 2765817600U, // LD1RB_IMM
3570 2765801216U, // LD1RB_S_IMM
3571 2765793796U, // LD1RD_IMM
3572 2765794644U, // LD1RH_D_IMM
3573 2765827412U, // LD1RH_IMM
3574 2765802836U, // LD1RH_S_IMM
3575 2765817571U, // LD1RO_B
3576 2765817571U, // LD1RO_B_IMM
3577 2765793780U, // LD1RO_D
3578 2765793780U, // LD1RO_D_IMM
3579 2765827390U, // LD1RO_H
3580 2765827390U, // LD1RO_H_IMM
3581 2765805993U, // LD1RO_W
3582 2765805993U, // LD1RO_W_IMM
3583 2765817592U, // LD1RQ_B
3584 2765817592U, // LD1RQ_B_IMM
3585 2765793788U, // LD1RQ_D
3586 2765793788U, // LD1RQ_D_IMM
3587 2765827404U, // LD1RQ_H
3588 2765827404U, // LD1RQ_H_IMM
3589 2765806001U, // LD1RQ_W
3590 2765806001U, // LD1RQ_W_IMM
3591 2765793235U, // LD1RSB_D_IMM
3592 2765826003U, // LD1RSB_H_IMM
3593 2765801427U, // LD1RSB_S_IMM
3594 2765794842U, // LD1RSH_D_IMM
3595 2765803034U, // LD1RSH_S_IMM
3596 2765797874U, // LD1RSW_IMM
3597 2765797817U, // LD1RW_D_IMM
3598 2765806009U, // LD1RW_IMM
3599 217916U, // LD1Rv16b
3600 19624764U, // LD1Rv16b_POST
3601 234300U, // LD1Rv1d
3602 19116860U, // LD1Rv1d_POST
3603 250684U, // LD1Rv2d
3604 19133244U, // LD1Rv2d_POST
3605 267068U, // LD1Rv2s
3606 20198204U, // LD1Rv2s_POST
3607 283452U, // LD1Rv4h
3608 20738876U, // LD1Rv4h_POST
3609 299836U, // LD1Rv4s
3610 20230972U, // LD1Rv4s_POST
3611 316220U, // LD1Rv8b
3612 19723068U, // LD1Rv8b_POST
3613 332604U, // LD1Rv8h
3614 20788028U, // LD1Rv8h_POST
3615 2765793172U, // LD1SB_D
3616 2765793172U, // LD1SB_D_IMM_REAL
3617 2765825940U, // LD1SB_H
3618 2765825940U, // LD1SB_H_IMM_REAL
3619 2765801364U, // LD1SB_S
3620 2765801364U, // LD1SB_S_IMM_REAL
3621 2765794792U, // LD1SH_D
3622 2765794792U, // LD1SH_D_IMM_REAL
3623 2765802984U, // LD1SH_S
3624 2765802984U, // LD1SH_S_IMM_REAL
3625 2765797833U, // LD1SW_D
3626 2765797833U, // LD1SW_D_IMM_REAL
3627 213033U, // LD1Threev16b
3628 21192745U, // LD1Threev16b_POST
3629 229417U, // LD1Threev1d
3630 21733417U, // LD1Threev1d_POST
3631 245801U, // LD1Threev2d
3632 21225513U, // LD1Threev2d_POST
3633 262185U, // LD1Threev2s
3634 21766185U, // LD1Threev2s_POST
3635 278569U, // LD1Threev4h
3636 21782569U, // LD1Threev4h_POST
3637 294953U, // LD1Threev4s
3638 21274665U, // LD1Threev4s_POST
3639 311337U, // LD1Threev8b
3640 21815337U, // LD1Threev8b_POST
3641 327721U, // LD1Threev8h
3642 21307433U, // LD1Threev8h_POST
3643 213033U, // LD1Twov16b
3644 18047017U, // LD1Twov16b_POST
3645 229417U, // LD1Twov1d
3646 18587689U, // LD1Twov1d_POST
3647 245801U, // LD1Twov2d
3648 18079785U, // LD1Twov2d_POST
3649 262185U, // LD1Twov2s
3650 18620457U, // LD1Twov2s_POST
3651 278569U, // LD1Twov4h
3652 18636841U, // LD1Twov4h_POST
3653 294953U, // LD1Twov4s
3654 18128937U, // LD1Twov4s_POST
3655 311337U, // LD1Twov8b
3656 18669609U, // LD1Twov8b_POST
3657 327721U, // LD1Twov8h
3658 18161705U, // LD1Twov8h_POST
3659 2765805830U, // LD1W
3660 2765797638U, // LD1W_D
3661 2765797638U, // LD1W_D_IMM_REAL
3662 2765805830U, // LD1W_IMM_REAL
3663 22364201U, // LD1i16
3664 22896681U, // LD1i16_POST
3665 22380585U, // LD1i32
3666 23437353U, // LD1i32_POST
3667 22396969U, // LD1i64
3668 23978025U, // LD1i64_POST
3669 22413353U, // LD1i8
3670 24518697U, // LD1i8_POST
3671 2765816794U, // LD2B
3672 2765816794U, // LD2B_IMM
3673 2765793566U, // LD2D
3674 2765793566U, // LD2D_IMM
3675 2765826930U, // LD2H
3676 2765826930U, // LD2H_IMM
3677 217922U, // LD2Rv16b
3678 20673346U, // LD2Rv16b_POST
3679 234306U, // LD2Rv1d
3680 18592578U, // LD2Rv1d_POST
3681 250690U, // LD2Rv2d
3682 18608962U, // LD2Rv2d_POST
3683 267074U, // LD2Rv2s
3684 19149634U, // LD2Rv2s_POST
3685 283458U, // LD2Rv4h
3686 20214594U, // LD2Rv4h_POST
3687 299842U, // LD2Rv4s
3688 19182402U, // LD2Rv4s_POST
3689 316226U, // LD2Rv8b
3690 20771650U, // LD2Rv8b_POST
3691 332610U, // LD2Rv8h
3692 20263746U, // LD2Rv8h_POST
3693 213131U, // LD2Twov16b
3694 18047115U, // LD2Twov16b_POST
3695 245899U, // LD2Twov2d
3696 18079883U, // LD2Twov2d_POST
3697 262283U, // LD2Twov2s
3698 18620555U, // LD2Twov2s_POST
3699 278667U, // LD2Twov4h
3700 18636939U, // LD2Twov4h_POST
3701 295051U, // LD2Twov4s
3702 18129035U, // LD2Twov4s_POST
3703 311435U, // LD2Twov8b
3704 18669707U, // LD2Twov8b_POST
3705 327819U, // LD2Twov8h
3706 18161803U, // LD2Twov8h_POST
3707 2765805882U, // LD2W
3708 2765805882U, // LD2W_IMM
3709 22364299U, // LD2i16
3710 23421067U, // LD2i16_POST
3711 22380683U, // LD2i32
3712 23961739U, // LD2i32_POST
3713 22397067U, // LD2i64
3714 25026699U, // LD2i64_POST
3715 22413451U, // LD2i8
3716 22945931U, // LD2i8_POST
3717 2765816815U, // LD3B
3718 2765816815U, // LD3B_IMM
3719 2765793578U, // LD3D
3720 2765793578U, // LD3D_IMM
3721 2765826942U, // LD3H
3722 2765826942U, // LD3H_IMM
3723 217928U, // LD3Rv16b
3724 25391944U, // LD3Rv16b_POST
3725 234312U, // LD3Rv1d
3726 21738312U, // LD3Rv1d_POST
3727 250696U, // LD3Rv2d
3728 21754696U, // LD3Rv2d_POST
3729 267080U, // LD3Rv2s
3730 25965384U, // LD3Rv2s_POST
3731 283464U, // LD3Rv4h
3732 26506056U, // LD3Rv4h_POST
3733 299848U, // LD3Rv4s
3734 25998152U, // LD3Rv4s_POST
3735 316232U, // LD3Rv8b
3736 25490248U, // LD3Rv8b_POST
3737 332616U, // LD3Rv8h
3738 26555208U, // LD3Rv8h_POST
3739 213539U, // LD3Threev16b
3740 21193251U, // LD3Threev16b_POST
3741 246307U, // LD3Threev2d
3742 21226019U, // LD3Threev2d_POST
3743 262691U, // LD3Threev2s
3744 21766691U, // LD3Threev2s_POST
3745 279075U, // LD3Threev4h
3746 21783075U, // LD3Threev4h_POST
3747 295459U, // LD3Threev4s
3748 21275171U, // LD3Threev4s_POST
3749 311843U, // LD3Threev8b
3750 21815843U, // LD3Threev8b_POST
3751 328227U, // LD3Threev8h
3752 21307939U, // LD3Threev8h_POST
3753 2765805894U, // LD3W
3754 2765805894U, // LD3W_IMM
3755 22364707U, // LD3i16
3756 27091491U, // LD3i16_POST
3757 22381091U, // LD3i32
3758 27632163U, // LD3i32_POST
3759 22397475U, // LD3i64
3760 28172835U, // LD3i64_POST
3761 22413859U, // LD3i8
3762 28713507U, // LD3i8_POST
3763 2765816841U, // LD4B
3764 2765816841U, // LD4B_IMM
3765 2765793590U, // LD4D
3766 2765793590U, // LD4D_IMM
3767 213569U, // LD4Fourv16b
3768 17523265U, // LD4Fourv16b_POST
3769 246337U, // LD4Fourv2d
3770 17556033U, // LD4Fourv2d_POST
3771 262721U, // LD4Fourv2s
3772 18096705U, // LD4Fourv2s_POST
3773 279105U, // LD4Fourv4h
3774 18113089U, // LD4Fourv4h_POST
3775 295489U, // LD4Fourv4s
3776 17605185U, // LD4Fourv4s_POST
3777 311873U, // LD4Fourv8b
3778 18145857U, // LD4Fourv8b_POST
3779 328257U, // LD4Fourv8h
3780 17637953U, // LD4Fourv8h_POST
3781 2765826954U, // LD4H
3782 2765826954U, // LD4H_IMM
3783 217934U, // LD4Rv16b
3784 20149070U, // LD4Rv16b_POST
3785 234318U, // LD4Rv1d
3786 18068302U, // LD4Rv1d_POST
3787 250702U, // LD4Rv2d
3788 18084686U, // LD4Rv2d_POST
3789 267086U, // LD4Rv2s
3790 18625358U, // LD4Rv2s_POST
3791 283470U, // LD4Rv4h
3792 19166030U, // LD4Rv4h_POST
3793 299854U, // LD4Rv4s
3794 18658126U, // LD4Rv4s_POST
3795 316238U, // LD4Rv8b
3796 20247374U, // LD4Rv8b_POST
3797 332622U, // LD4Rv8h
3798 19215182U, // LD4Rv8h_POST
3799 2765805906U, // LD4W
3800 2765805906U, // LD4W_IMM
3801 22364737U, // LD4i16
3802 23945793U, // LD4i16_POST
3803 22381121U, // LD4i32
3804 25010753U, // LD4i32_POST
3805 22397505U, // LD4i64
3806 29221441U, // LD4i64_POST
3807 22413889U, // LD4i8
3808 23470657U, // LD4i8_POST
3809 410619U, // LD64B
3810 1309271061U, // LDADDAB
3811 1309272991U, // LDADDAH
3812 1309271283U, // LDADDALB
3813 1309273165U, // LDADDALH
3814 1309273833U, // LDADDALW
3815 1309273833U, // LDADDALX
3816 1309270682U, // LDADDAW
3817 1309270682U, // LDADDAX
3818 1309271219U, // LDADDB
3819 1309273151U, // LDADDH
3820 1309271464U, // LDADDLB
3821 1309273265U, // LDADDLH
3822 1309274010U, // LDADDLW
3823 1309274010U, // LDADDLX
3824 1309272478U, // LDADDW
3825 1309272478U, // LDADDX
3826 2255497019U, // LDAPRB
3827 2255498639U, // LDAPRH
3828 2255500321U, // LDAPRW
3829 2255500321U, // LDAPRX
3830 2255497062U, // LDAPURBi
3831 2255498682U, // LDAPURHi
3832 2255497202U, // LDAPURSBWi
3833 2255497202U, // LDAPURSBXi
3834 2255498809U, // LDAPURSHWi
3835 2255498809U, // LDAPURSHXi
3836 2255501841U, // LDAPURSWi
3837 2255500402U, // LDAPURXi
3838 2255500402U, // LDAPURi
3839 2255496967U, // LDARB
3840 2255498587U, // LDARH
3841 2255500116U, // LDARW
3842 2255500116U, // LDARX
3843 101200630U, // LDAXPW
3844 101200630U, // LDAXPX
3845 2255497078U, // LDAXRB
3846 2255498698U, // LDAXRH
3847 2255500446U, // LDAXRW
3848 2255500446U, // LDAXRX
3849 1309271117U, // LDCLRAB
3850 1309273048U, // LDCLRAH
3851 1309271358U, // LDCLRALB
3852 1309273205U, // LDCLRALH
3853 1309273907U, // LDCLRALW
3854 1309273907U, // LDCLRALX
3855 1309270819U, // LDCLRAW
3856 1309270819U, // LDCLRAX
3857 1309271836U, // LDCLRB
3858 1309273456U, // LDCLRH
3859 1309271566U, // LDCLRLB
3860 1309273301U, // LDCLRLH
3861 1309274210U, // LDCLRLW
3862 1309274210U, // LDCLRLX
3863 1309275076U, // LDCLRW
3864 1309275076U, // LDCLRX
3865 1309271126U, // LDEORAB
3866 1309273057U, // LDEORAH
3867 1309271368U, // LDEORALB
3868 1309273215U, // LDEORALH
3869 1309273916U, // LDEORALW
3870 1309273916U, // LDEORALX
3871 1309270827U, // LDEORAW
3872 1309270827U, // LDEORAX
3873 1309271859U, // LDEORB
3874 1309273479U, // LDEORH
3875 1309271575U, // LDEORLB
3876 1309273310U, // LDEORLH
3877 1309274218U, // LDEORLW
3878 1309274218U, // LDEORLX
3879 1309275152U, // LDEORW
3880 1309275152U, // LDEORX
3881 2765792163U, // LDFF1B_D_REAL
3882 2765824931U, // LDFF1B_H_REAL
3883 2765816739U, // LDFF1B_REAL
3884 2765800355U, // LDFF1B_S_REAL
3885 2765793528U, // LDFF1D_REAL
3886 2765794107U, // LDFF1H_D_REAL
3887 2765826875U, // LDFF1H_REAL
3888 2765802299U, // LDFF1H_S_REAL
3889 2765793179U, // LDFF1SB_D_REAL
3890 2765825947U, // LDFF1SB_H_REAL
3891 2765801371U, // LDFF1SB_S_REAL
3892 2765794799U, // LDFF1SH_D_REAL
3893 2765802991U, // LDFF1SH_S_REAL
3894 2765797840U, // LDFF1SW_D_REAL
3895 2765797644U, // LDFF1W_D_REAL
3896 2765805836U, // LDFF1W_REAL
3897 2758929148U, // LDG
3898 2255499524U, // LDGM
3899 2255496974U, // LDLARB
3900 2255498594U, // LDLARH
3901 2255500122U, // LDLARW
3902 2255500122U, // LDLARX
3903 2765792171U, // LDNF1B_D_IMM_REAL
3904 2765824939U, // LDNF1B_H_IMM_REAL
3905 2765816747U, // LDNF1B_IMM_REAL
3906 2765800363U, // LDNF1B_S_IMM_REAL
3907 2765793536U, // LDNF1D_IMM_REAL
3908 2765794115U, // LDNF1H_D_IMM_REAL
3909 2765826883U, // LDNF1H_IMM_REAL
3910 2765802307U, // LDNF1H_S_IMM_REAL
3911 2765793188U, // LDNF1SB_D_IMM_REAL
3912 2765825956U, // LDNF1SB_H_IMM_REAL
3913 2765801380U, // LDNF1SB_S_IMM_REAL
3914 2765794808U, // LDNF1SH_D_IMM_REAL
3915 2765803000U, // LDNF1SH_S_IMM_REAL
3916 2765797849U, // LDNF1SW_D_IMM_REAL
3917 2765797652U, // LDNF1W_D_IMM_REAL
3918 2765805844U, // LDNF1W_IMM_REAL
3919 101200549U, // LDNPDi
3920 101200549U, // LDNPQi
3921 101200549U, // LDNPSi
3922 101200549U, // LDNPWi
3923 101200549U, // LDNPXi
3924 2765816755U, // LDNT1B_ZRI
3925 2765816755U, // LDNT1B_ZRR
3926 2296030131U, // LDNT1B_ZZR_D_REAL
3927 2329592755U, // LDNT1B_ZZR_S_REAL
3928 2765793544U, // LDNT1D_ZRI
3929 2765793544U, // LDNT1D_ZRR
3930 2296031496U, // LDNT1D_ZZR_D_REAL
3931 2765826891U, // LDNT1H_ZRI
3932 2765826891U, // LDNT1H_ZRR
3933 2296032075U, // LDNT1H_ZZR_D_REAL
3934 2329594699U, // LDNT1H_ZZR_S_REAL
3935 2296031149U, // LDNT1SB_ZZR_D_REAL
3936 2329593773U, // LDNT1SB_ZZR_S_REAL
3937 2296032769U, // LDNT1SH_ZZR_D_REAL
3938 2329595393U, // LDNT1SH_ZZR_S_REAL
3939 2296035810U, // LDNT1SW_ZZR_D_REAL
3940 2765805852U, // LDNT1W_ZRI
3941 2765805852U, // LDNT1W_ZRR
3942 2296035612U, // LDNT1W_ZZR_D_REAL
3943 2329598236U, // LDNT1W_ZZR_S_REAL
3944 101200469U, // LDPDi
3945 604631637U, // LDPDpost
3946 604631637U, // LDPDpre
3947 101200469U, // LDPQi
3948 604631637U, // LDPQpost
3949 604631637U, // LDPQpre
3950 101202411U, // LDPSWi
3951 604633579U, // LDPSWpost
3952 604633579U, // LDPSWpre
3953 101200469U, // LDPSi
3954 604631637U, // LDPSpost
3955 604631637U, // LDPSpre
3956 101200469U, // LDPWi
3957 604631637U, // LDPWpost
3958 604631637U, // LDPWpre
3959 101200469U, // LDPXi
3960 604631637U, // LDPXpost
3961 604631637U, // LDPXpre
3962 2255495801U, // LDRAAindexed
3963 2758926969U, // LDRAAwriteback
3964 2255496255U, // LDRABindexed
3965 2758927423U, // LDRABwriteback
3966 611444502U, // LDRBBpost
3967 2758928150U, // LDRBBpre
3968 2255496982U, // LDRBBroW
3969 2255496982U, // LDRBBroX
3970 2255496982U, // LDRBBui
3971 611447698U, // LDRBpost
3972 2758931346U, // LDRBpre
3973 2255500178U, // LDRBroW
3974 2255500178U, // LDRBroX
3975 2255500178U, // LDRBui
3976 671626130U, // LDRDl
3977 611447698U, // LDRDpost
3978 2758931346U, // LDRDpre
3979 2255500178U, // LDRDroW
3980 2255500178U, // LDRDroX
3981 2255500178U, // LDRDui
3982 611446122U, // LDRHHpost
3983 2758929770U, // LDRHHpre
3984 2255498602U, // LDRHHroW
3985 2255498602U, // LDRHHroX
3986 2255498602U, // LDRHHui
3987 611447698U, // LDRHpost
3988 2758931346U, // LDRHpre
3989 2255500178U, // LDRHroW
3990 2255500178U, // LDRHroX
3991 2255500178U, // LDRHui
3992 671626130U, // LDRQl
3993 611447698U, // LDRQpost
3994 2758931346U, // LDRQpre
3995 2255500178U, // LDRQroW
3996 2255500178U, // LDRQroX
3997 2255500178U, // LDRQui
3998 611444699U, // LDRSBWpost
3999 2758928347U, // LDRSBWpre
4000 2255497179U, // LDRSBWroW
4001 2255497179U, // LDRSBWroX
4002 2255497179U, // LDRSBWui
4003 611444699U, // LDRSBXpost
4004 2758928347U, // LDRSBXpre
4005 2255497179U, // LDRSBXroW
4006 2255497179U, // LDRSBXroX
4007 2255497179U, // LDRSBXui
4008 611446306U, // LDRSHWpost
4009 2758929954U, // LDRSHWpre
4010 2255498786U, // LDRSHWroW
4011 2255498786U, // LDRSHWroX
4012 2255498786U, // LDRSHWui
4013 611446306U, // LDRSHXpost
4014 2758929954U, // LDRSHXpre
4015 2255498786U, // LDRSHXroW
4016 2255498786U, // LDRSHXroX
4017 2255498786U, // LDRSHXui
4018 671627770U, // LDRSWl
4019 611449338U, // LDRSWpost
4020 2758932986U, // LDRSWpre
4021 2255501818U, // LDRSWroW
4022 2255501818U, // LDRSWroX
4023 2255501818U, // LDRSWui
4024 671626130U, // LDRSl
4025 611447698U, // LDRSpost
4026 2758931346U, // LDRSpre
4027 2255500178U, // LDRSroW
4028 2255500178U, // LDRSroX
4029 2255500178U, // LDRSui
4030 671626130U, // LDRWl
4031 611447698U, // LDRWpost
4032 2758931346U, // LDRWpre
4033 2255500178U, // LDRWroW
4034 2255500178U, // LDRWroX
4035 2255500178U, // LDRWui
4036 671626130U, // LDRXl
4037 611447698U, // LDRXpost
4038 2758931346U, // LDRXpre
4039 2255500178U, // LDRXroW
4040 2255500178U, // LDRXroX
4041 2255500178U, // LDRXui
4042 2255909778U, // LDR_PXI
4043 2255909778U, // LDR_ZXI
4044 1309271142U, // LDSETAB
4045 1309273073U, // LDSETAH
4046 1309271386U, // LDSETALB
4047 1309273233U, // LDSETALH
4048 1309273932U, // LDSETALW
4049 1309273932U, // LDSETALX
4050 1309270867U, // LDSETAW
4051 1309270867U, // LDSETAX
4052 1309272065U, // LDSETB
4053 1309273667U, // LDSETH
4054 1309271625U, // LDSETLB
4055 1309273326U, // LDSETLH
4056 1309274274U, // LDSETLW
4057 1309274274U, // LDSETLX
4058 1309275663U, // LDSETW
4059 1309275663U, // LDSETX
4060 1309271151U, // LDSMAXAB
4061 1309273082U, // LDSMAXAH
4062 1309271396U, // LDSMAXALB
4063 1309273243U, // LDSMAXALH
4064 1309273941U, // LDSMAXALW
4065 1309273941U, // LDSMAXALX
4066 1309270891U, // LDSMAXAW
4067 1309270891U, // LDSMAXAX
4068 1309272202U, // LDSMAXB
4069 1309273699U, // LDSMAXH
4070 1309271634U, // LDSMAXLB
4071 1309273368U, // LDSMAXLH
4072 1309274329U, // LDSMAXLW
4073 1309274329U, // LDSMAXLX
4074 1309276763U, // LDSMAXW
4075 1309276763U, // LDSMAXX
4076 1309271070U, // LDSMINAB
4077 1309273021U, // LDSMINAH
4078 1309271328U, // LDSMINALB
4079 1309273175U, // LDSMINALH
4080 1309273872U, // LDSMINALW
4081 1309273872U, // LDSMINALX
4082 1309270774U, // LDSMINAW
4083 1309270774U, // LDSMINAX
4084 1309271677U, // LDSMINB
4085 1309273388U, // LDSMINH
4086 1309271539U, // LDSMINLB
4087 1309273274U, // LDSMINLH
4088 1309274172U, // LDSMINLW
4089 1309274172U, // LDSMINLX
4090 1309274464U, // LDSMINW
4091 1309274464U, // LDSMINX
4092 2255497027U, // LDTRBi
4093 2255498647U, // LDTRHi
4094 2255497186U, // LDTRSBWi
4095 2255497186U, // LDTRSBXi
4096 2255498793U, // LDTRSHWi
4097 2255498793U, // LDTRSHXi
4098 2255501825U, // LDTRSWi
4099 2255500366U, // LDTRWi
4100 2255500366U, // LDTRXi
4101 1309271161U, // LDUMAXAB
4102 1309273092U, // LDUMAXAH
4103 1309271407U, // LDUMAXALB
4104 1309273254U, // LDUMAXALH
4105 1309273951U, // LDUMAXALW
4106 1309273951U, // LDUMAXALX
4107 1309270900U, // LDUMAXAW
4108 1309270900U, // LDUMAXAX
4109 1309272211U, // LDUMAXB
4110 1309273708U, // LDUMAXH
4111 1309271644U, // LDUMAXLB
4112 1309273378U, // LDUMAXLH
4113 1309274338U, // LDUMAXLW
4114 1309274338U, // LDUMAXLX
4115 1309276771U, // LDUMAXW
4116 1309276771U, // LDUMAXX
4117 1309271080U, // LDUMINAB
4118 1309273031U, // LDUMINAH
4119 1309271339U, // LDUMINALB
4120 1309273186U, // LDUMINALH
4121 1309273882U, // LDUMINALW
4122 1309273882U, // LDUMINALX
4123 1309270783U, // LDUMINAW
4124 1309270783U, // LDUMINAX
4125 1309271686U, // LDUMINB
4126 1309273397U, // LDUMINH
4127 1309271549U, // LDUMINLB
4128 1309273284U, // LDUMINLH
4129 1309274181U, // LDUMINLW
4130 1309274181U, // LDUMINLX
4131 1309274472U, // LDUMINW
4132 1309274472U, // LDUMINX
4133 2255497047U, // LDURBBi
4134 2255500389U, // LDURBi
4135 2255500389U, // LDURDi
4136 2255498667U, // LDURHHi
4137 2255500389U, // LDURHi
4138 2255500389U, // LDURQi
4139 2255497194U, // LDURSBWi
4140 2255497194U, // LDURSBXi
4141 2255498801U, // LDURSHWi
4142 2255498801U, // LDURSHXi
4143 2255501833U, // LDURSWi
4144 2255500389U, // LDURSi
4145 2255500389U, // LDURWi
4146 2255500389U, // LDURXi
4147 101200658U, // LDXPW
4148 101200658U, // LDXPX
4149 2255497086U, // LDXRB
4150 2255498706U, // LDXRH
4151 2255500453U, // LDXRW
4152 2255500453U, // LDXRX
4153 369644548U, // LSLR_ZPmZ_B
4154 369652740U, // LSLR_ZPmZ_D
4155 2556466180U, // LSLR_ZPmZ_H
4156 369669124U, // LSLR_ZPmZ_S
4157 2248683650U, // LSLVWr
4158 2248683650U, // LSLVXr
4159 369643650U, // LSL_WIDE_ZPmZ_B
4160 2556465282U, // LSL_WIDE_ZPmZ_H
4161 369668226U, // LSL_WIDE_ZPmZ_S
4162 2584236162U, // LSL_WIDE_ZZZ_B
4163 241733762U, // LSL_WIDE_ZZZ_H
4164 2617815170U, // LSL_WIDE_ZZZ_S
4165 369643650U, // LSL_ZPmI_B
4166 369651842U, // LSL_ZPmI_D
4167 2556465282U, // LSL_ZPmI_H
4168 369668226U, // LSL_ZPmI_S
4169 369643650U, // LSL_ZPmZ_B
4170 369651842U, // LSL_ZPmZ_D
4171 2556465282U, // LSL_ZPmZ_H
4172 369668226U, // LSL_ZPmZ_S
4173 2584236162U, // LSL_ZZI_B
4174 2416472194U, // LSL_ZZI_D
4175 2389217410U, // LSL_ZZI_H
4176 2617815170U, // LSL_ZZI_S
4177 369644595U, // LSRR_ZPmZ_B
4178 369652787U, // LSRR_ZPmZ_D
4179 2556466227U, // LSRR_ZPmZ_H
4180 369669171U, // LSRR_ZPmZ_S
4181 2248684606U, // LSRVWr
4182 2248684606U, // LSRVXr
4183 369644606U, // LSR_WIDE_ZPmZ_B
4184 2556466238U, // LSR_WIDE_ZPmZ_H
4185 369669182U, // LSR_WIDE_ZPmZ_S
4186 2584237118U, // LSR_WIDE_ZZZ_B
4187 241734718U, // LSR_WIDE_ZZZ_H
4188 2617816126U, // LSR_WIDE_ZZZ_S
4189 369644606U, // LSR_ZPmI_B
4190 369652798U, // LSR_ZPmI_D
4191 2556466238U, // LSR_ZPmI_H
4192 369669182U, // LSR_ZPmI_S
4193 369644606U, // LSR_ZPmZ_B
4194 369652798U, // LSR_ZPmZ_D
4195 2556466238U, // LSR_ZPmZ_H
4196 369669182U, // LSR_ZPmZ_S
4197 2584237118U, // LSR_ZZI_B
4198 2416473150U, // LSR_ZZI_D
4199 2389218366U, // LSR_ZZI_H
4200 2617816126U, // LSR_ZZI_S
4201 2248681930U, // MADDWrrr
4202 2248681930U, // MADDXrrr
4203 369641795U, // MAD_ZPmZZ_B
4204 369649987U, // MAD_ZPmZZ_D
4205 2556463427U, // MAD_ZPmZZ_H
4206 369666371U, // MAD_ZPmZZ_S
4207 2517126200U, // MATCH_PPzZZ_B
4208 2892008504U, // MATCH_PPzZZ_H
4209 369640141U, // MLA_ZPmZZ_B
4210 369648333U, // MLA_ZPmZZ_D
4211 2556461773U, // MLA_ZPmZZ_H
4212 369664717U, // MLA_ZPmZZ_S
4213 2282250957U, // MLA_ZZZI_D
4214 2390786765U, // MLA_ZZZI_H
4215 2315821773U, // MLA_ZZZI_S
4216 337175245U, // MLAv16i8
4217 2485183181U, // MLAv2i32
4218 2485183181U, // MLAv2i32_indexed
4219 338748109U, // MLAv4i16
4220 338748109U, // MLAv4i16_indexed
4221 339272397U, // MLAv4i32
4222 339272397U, // MLAv4i32_indexed
4223 2487280333U, // MLAv8i16
4224 2487280333U, // MLAv8i16_indexed
4225 2487804621U, // MLAv8i8
4226 369644866U, // MLS_ZPmZZ_B
4227 369653058U, // MLS_ZPmZZ_D
4228 2556466498U, // MLS_ZPmZZ_H
4229 369669442U, // MLS_ZPmZZ_S
4230 2282255682U, // MLS_ZZZI_D
4231 2390791490U, // MLS_ZZZI_H
4232 2315826498U, // MLS_ZZZI_S
4233 337179970U, // MLSv16i8
4234 2485187906U, // MLSv2i32
4235 2485187906U, // MLSv2i32_indexed
4236 338752834U, // MLSv4i16
4237 338752834U, // MLSv4i16_indexed
4238 339277122U, // MLSv4i32
4239 339277122U, // MLSv4i32_indexed
4240 2487285058U, // MLSv8i16
4241 2487285058U, // MLSv8i16_indexed
4242 2487809346U, // MLSv8i8
4243 1342713546U, // MOVID
4244 1377357514U, // MOVIv16b_ns
4245 1344851658U, // MOVIv2d_ns
4246 3525365450U, // MOVIv2i32
4247 3525365450U, // MOVIv2s_msl
4248 3526414026U, // MOVIv4i16
4249 3526938314U, // MOVIv4i32
4250 3526938314U, // MOVIv4s_msl
4251 1380503242U, // MOVIv8b_ns
4252 3527462602U, // MOVIv8i16
4253 638070485U, // MOVKWi
4254 638070485U, // MOVKXi
4255 3523752417U, // MOVNWi
4256 3523752417U, // MOVNXi
4257 547463U, // MOVPRFX_ZPmZ_B
4258 2148039303U, // MOVPRFX_ZPmZ_D
4259 34642567U, // MOVPRFX_ZPmZ_H
4260 572039U, // MOVPRFX_ZPmZ_S
4261 2517129863U, // MOVPRFX_ZPzZ_B
4262 2517138055U, // MOVPRFX_ZPzZ_D
4263 2892012167U, // MOVPRFX_ZPzZ_H
4264 2517154439U, // MOVPRFX_ZPzZ_S
4265 370047623U, // MOVPRFX_ZZ
4266 3523754770U, // MOVZWi
4267 3523754770U, // MOVZXi
4268 1409824150U, // MRS
4269 369641415U, // MSB_ZPmZZ_B
4270 369649607U, // MSB_ZPmZZ_D
4271 2556463047U, // MSB_ZPmZZ_H
4272 369665991U, // MSB_ZPmZZ_S
4273 431171U, // MSR
4274 439363U, // MSRpstateImm1
4275 439363U, // MSRpstateImm4
4276 2248681544U, // MSUBWrrr
4277 2248681544U, // MSUBXrrr
4278 2584236210U, // MUL_ZI_B
4279 2416472242U, // MUL_ZI_D
4280 2389217458U, // MUL_ZI_H
4281 2617815218U, // MUL_ZI_S
4282 369643698U, // MUL_ZPmZ_B
4283 369651890U, // MUL_ZPmZ_D
4284 2556465330U, // MUL_ZPmZ_H
4285 369668274U, // MUL_ZPmZ_S
4286 2416472242U, // MUL_ZZZI_D
4287 2389217458U, // MUL_ZZZI_H
4288 2617815218U, // MUL_ZZZI_S
4289 2584236210U, // MUL_ZZZ_B
4290 2416472242U, // MUL_ZZZ_D
4291 2389217458U, // MUL_ZZZ_H
4292 2617815218U, // MUL_ZZZ_S
4293 68735154U, // MULv16i8
4294 2216743090U, // MULv2i32
4295 2216743090U, // MULv2i32_indexed
4296 70308018U, // MULv4i16
4297 70308018U, // MULv4i16_indexed
4298 70832306U, // MULv4i32
4299 70832306U, // MULv4i32_indexed
4300 2218840242U, // MULv8i16
4301 2218840242U, // MULv8i16_indexed
4302 2219364530U, // MULv8i8
4303 3525365431U, // MVNIv2i32
4304 3525365431U, // MVNIv2s_msl
4305 3526414007U, // MVNIv4i16
4306 3526938295U, // MVNIv4i32
4307 3526938295U, // MVNIv4s_msl
4308 3527462583U, // MVNIv8i16
4309 2517128462U, // NANDS_PPzPP
4310 2517125614U, // NAND_PPzPP
4311 2416472184U, // NBSL_ZZZZ
4312 543490U, // NEG_ZPmZ_B
4313 2148035330U, // NEG_ZPmZ_D
4314 34638594U, // NEG_ZPmZ_H
4315 568066U, // NEG_ZPmZ_S
4316 2216217346U, // NEGv16i8
4317 101198594U, // NEGv1i64
4318 2216741634U, // NEGv2i32
4319 69782274U, // NEGv2i64
4320 2217790210U, // NEGv4i16
4321 70830850U, // NEGv4i32
4322 2218838786U, // NEGv8i16
4323 71879426U, // NEGv8i8
4324 2517126199U, // NMATCH_PPzZZ_B
4325 2892008503U, // NMATCH_PPzZZ_H
4326 2517128609U, // NORS_PPzPP
4327 2517128215U, // NOR_PPzPP
4328 546764U, // NOT_ZPmZ_B
4329 2148038604U, // NOT_ZPmZ_D
4330 34641868U, // NOT_ZPmZ_H
4331 571340U, // NOT_ZPmZ_S
4332 2216220620U, // NOTv16i8
4333 71882700U, // NOTv8i8
4334 2517128553U, // ORNS_PPzPP
4335 2248683939U, // ORNWrs
4336 2248683939U, // ORNXrs
4337 2517127587U, // ORN_PPzPP
4338 68735395U, // ORNv16i8
4339 2219364771U, // ORNv8i8
4340 2517128615U, // ORRS_PPzPP
4341 2248684584U, // ORRWri
4342 2248684584U, // ORRWrs
4343 2248684584U, // ORRXri
4344 2248684584U, // ORRXrs
4345 2517128232U, // ORR_PPzPP
4346 2416473128U, // ORR_ZI
4347 369644584U, // ORR_ZPmZ_B
4348 369652776U, // ORR_ZPmZ_D
4349 2556466216U, // ORR_ZPmZ_H
4350 369669160U, // ORR_ZPmZ_S
4351 2416473128U, // ORR_ZZZ
4352 68736040U, // ORRv16i8
4353 639693864U, // ORRv2i32
4354 640742440U, // ORRv4i16
4355 641266728U, // ORRv4i32
4356 641791016U, // ORRv8i16
4357 2219365416U, // ORRv8i8
4358 71916U, // ORV_VPZ_B
4359 544815340U, // ORV_VPZ_D
4360 545347820U, // ORV_VPZ_H
4361 542734572U, // ORV_VPZ_S
4362 101196435U, // PACDA
4363 101196972U, // PACDB
4364 9085U, // PACDZA
4365 10396U, // PACDZB
4366 2248680112U, // PACGA
4367 101196471U, // PACIA
4368 7190U, // PACIA1716
4369 7155U, // PACIASP
4370 7146U, // PACIAZ
4371 101197007U, // PACIB
4372 7101U, // PACIB1716
4373 7181U, // PACIBSP
4374 7164U, // PACIBZ
4375 9101U, // PACIZA
4376 10412U, // PACIZB
4377 19108U, // PFALSE
4378 2517129198U, // PFIRST_B
4379 2617796059U, // PMULLB_ZZZ_D
4380 264275419U, // PMULLB_ZZZ_H
4381 30049755U, // PMULLB_ZZZ_Q
4382 2617800409U, // PMULLT_ZZZ_D
4383 264279769U, // PMULLT_ZZZ_H
4384 30054105U, // PMULLT_ZZZ_Q
4385 71352608U, // PMULLv16i8
4386 1473302567U, // PMULLv1i64
4387 1506853152U, // PMULLv2i64
4388 2218840103U, // PMULLv8i8
4389 2584236222U, // PMUL_ZZZ_B
4390 68735166U, // PMULv16i8
4391 2219364542U, // PMULv8i8
4392 2517129258U, // PNEXT_B
4393 2517137450U, // PNEXT_D
4394 2388695082U, // PNEXT_H
4395 2517153834U, // PNEXT_S
4396 243188930U, // PRFB_D_PZI
4397 2398012610U, // PRFB_D_SCALED
4398 250528962U, // PRFB_D_SXTW_SCALED
4399 2398012610U, // PRFB_D_UXTW_SCALED
4400 250528962U, // PRFB_PRI
4401 250528962U, // PRFB_PRR
4402 241091778U, // PRFB_S_PZI
4403 2398012610U, // PRFB_S_SXTW_SCALED
4404 250528962U, // PRFB_S_UXTW_SCALED
4405 2390673896U, // PRFD_D_PZI
4406 250530280U, // PRFD_D_SCALED
4407 2398013928U, // PRFD_D_SXTW_SCALED
4408 250530280U, // PRFD_D_UXTW_SCALED
4409 250530280U, // PRFD_PRI
4410 2398013928U, // PRFD_PRR
4411 2388576744U, // PRFD_S_PZI
4412 250530280U, // PRFD_S_SXTW_SCALED
4413 2398013928U, // PRFD_S_UXTW_SCALED
4414 243190855U, // PRFH_D_PZI
4415 2398014535U, // PRFH_D_SCALED
4416 250530887U, // PRFH_D_SXTW_SCALED
4417 2398014535U, // PRFH_D_UXTW_SCALED
4418 250530887U, // PRFH_PRI
4419 250530887U, // PRFH_PRR
4420 241093703U, // PRFH_S_PZI
4421 2398014535U, // PRFH_S_SXTW_SCALED
4422 250530887U, // PRFH_S_UXTW_SCALED
4423 672067838U, // PRFMl
4424 2255941886U, // PRFMroW
4425 2255941886U, // PRFMroX
4426 2255941886U, // PRFMui
4427 2398017955U, // PRFS_PRR
4428 2255941941U, // PRFUMi
4429 243194275U, // PRFW_D_PZI
4430 2398017955U, // PRFW_D_SCALED
4431 250534307U, // PRFW_D_SXTW_SCALED
4432 2398017955U, // PRFW_D_UXTW_SCALED
4433 250534307U, // PRFW_PRI
4434 241097123U, // PRFW_S_PZI
4435 250534307U, // PRFW_S_SXTW_SCALED
4436 2398017955U, // PRFW_S_UXTW_SCALED
4437 437155808U, // PTEST_PP
4438 772298005U, // PTRUES_B
4439 772306197U, // PTRUES_D
4440 30971157U, // PTRUES_H
4441 772322581U, // PTRUES_S
4442 772295358U, // PTRUE_B
4443 772303550U, // PTRUE_D
4444 30968510U, // PTRUE_H
4445 772319934U, // PTRUE_S
4446 566267525U, // PUNPKHI_PP
4447 566268408U, // PUNPKLO_PP
4448 2349352564U, // RADDHNB_ZZZ_B
4449 240158324U, // RADDHNB_ZZZ_H
4450 2416486004U, // RADDHNB_ZZZ_S
4451 2450020155U, // RADDHNT_ZZZ_B
4452 240686907U, // RADDHNT_ZZZ_H
4453 2282272571U, // RADDHNT_ZZZ_S
4454 2216743250U, // RADDHNv2i64_v2i32
4455 2486755691U, // RADDHNv2i64_v4i32
4456 70308178U, // RADDHNv4i32_v4i16
4457 339796331U, // RADDHNv4i32_v8i16
4458 2484658539U, // RADDHNv8i16_v16i8
4459 2219364690U, // RADDHNv8i16_v8i8
4460 2217263230U, // RAX1
4461 2416468094U, // RAX1_ZZZ_D
4462 101201460U, // RBITWr
4463 101201460U, // RBITXr
4464 546356U, // RBIT_ZPmZ_B
4465 2148038196U, // RBIT_ZPmZ_D
4466 34641460U, // RBIT_ZPmZ_H
4467 570932U, // RBIT_ZPmZ_S
4468 2216220212U, // RBITv16i8
4469 71882292U, // RBITv8i8
4470 369644942U, // RDFFRS_PPz
4471 369644439U, // RDFFR_PPz_REAL
4472 21399U, // RDFFR_P_REAL
4473 101200083U, // RDVLI_XI
4474 13834U, // RET
4475 7299U, // RETAA
4476 7306U, // RETAB
4477 101196371U, // REV16Wr
4478 101196371U, // REV16Xr
4479 2216215123U, // REV16v16i8
4480 71877203U, // REV16v8i8
4481 101195908U, // REV32Xr
4482 2216214660U, // REV32v16i8
4483 2217787524U, // REV32v4i16
4484 2218836100U, // REV32v8i16
4485 71876740U, // REV32v8i8
4486 2216215098U, // REV64v16i8
4487 2216739386U, // REV64v2i32
4488 2217787962U, // REV64v4i16
4489 70828602U, // REV64v4i32
4490 2218836538U, // REV64v8i16
4491 71877178U, // REV64v8i8
4492 2148034660U, // REVB_ZPmZ_D
4493 34637924U, // REVB_ZPmZ_H
4494 567396U, // REVB_ZPmZ_S
4495 2148036189U, // REVH_ZPmZ_D
4496 568925U, // REVH_ZPmZ_S
4497 2148039213U, // REVW_ZPmZ_D
4498 101202052U, // REVWr
4499 101202052U, // REVXr
4500 436754564U, // REV_PP_B
4501 268990596U, // REV_PP_D
4502 543725700U, // REV_PP_H
4503 470333572U, // REV_PP_S
4504 436754564U, // REV_ZZ_B
4505 268990596U, // REV_ZZ_D
4506 543725700U, // REV_ZZ_H
4507 470333572U, // REV_ZZ_S
4508 2248682191U, // RMIF
4509 2248684572U, // RORVWr
4510 2248684572U, // RORVXr
4511 2349352611U, // RSHRNB_ZZI_B
4512 2387642019U, // RSHRNB_ZZI_H
4513 2416486051U, // RSHRNB_ZZI_S
4514 2450020190U, // RSHRNT_ZZI_B
4515 240686942U, // RSHRNT_ZZI_H
4516 2282272606U, // RSHRNT_ZZI_S
4517 2484658568U, // RSHRNv16i8_shift
4518 2216743315U, // RSHRNv2i32_shift
4519 70308243U, // RSHRNv4i16_shift
4520 2486755720U, // RSHRNv4i32_shift
4521 339796360U, // RSHRNv8i16_shift
4522 2219364755U, // RSHRNv8i8_shift
4523 2349352555U, // RSUBHNB_ZZZ_B
4524 240158315U, // RSUBHNB_ZZZ_H
4525 2416485995U, // RSUBHNB_ZZZ_S
4526 2450020146U, // RSUBHNT_ZZZ_B
4527 240686898U, // RSUBHNT_ZZZ_H
4528 2282272562U, // RSUBHNT_ZZZ_S
4529 2216743242U, // RSUBHNv2i64_v2i32
4530 2486755682U, // RSUBHNv2i64_v4i32
4531 70308170U, // RSUBHNv4i32_v4i16
4532 339796322U, // RSUBHNv4i32_v8i16
4533 2484658530U, // RSUBHNv8i16_v16i8
4534 2219364682U, // RSUBHNv8i16_v8i8
4535 2315805923U, // SABALB_ZZZ_D
4536 266372323U, // SABALB_ZZZ_H
4537 2450040035U, // SABALB_ZZZ_S
4538 2315810368U, // SABALT_ZZZ_D
4539 266376768U, // SABALT_ZZZ_H
4540 2450044480U, // SABALT_ZZZ_S
4541 339796132U, // SABALv16i8_v8i16
4542 2485710555U, // SABALv2i32_v2i64
4543 339275483U, // SABALv4i16_v4i32
4544 338223268U, // SABALv4i32_v2i64
4545 2486755492U, // SABALv8i16_v4i32
4546 2487283419U, // SABALv8i8_v8i16
4547 705184391U, // SABA_ZZZ_B
4548 2282250887U, // SABA_ZZZ_D
4549 2390786695U, // SABA_ZZZ_H
4550 2315821703U, // SABA_ZZZ_S
4551 337175175U, // SABAv16i8
4552 2485183111U, // SABAv2i32
4553 338748039U, // SABAv4i16
4554 339272327U, // SABAv4i32
4555 2487280263U, // SABAv8i16
4556 2487804551U, // SABAv8i8
4557 2617795992U, // SABDLB_ZZZ_D
4558 264275352U, // SABDLB_ZZZ_H
4559 2349376920U, // SABDLB_ZZZ_S
4560 2617800337U, // SABDLT_ZZZ_D
4561 264279697U, // SABDLT_ZZZ_H
4562 2349381265U, // SABDLT_ZZZ_S
4563 71352550U, // SABDLv16i8_v8i16
4564 2217267084U, // SABDLv2i32_v2i64
4565 70832012U, // SABDLv4i16_v4i32
4566 69779686U, // SABDLv4i32_v2i64
4567 2218311910U, // SABDLv8i16_v4i32
4568 2218839948U, // SABDLv8i8_v8i16
4569 369641820U, // SABD_ZPmZ_B
4570 369650012U, // SABD_ZPmZ_D
4571 2556463452U, // SABD_ZPmZ_H
4572 369666396U, // SABD_ZPmZ_S
4573 68733276U, // SABDv16i8
4574 2216741212U, // SABDv2i32
4575 70306140U, // SABDv4i16
4576 70830428U, // SABDv4i32
4577 2218838364U, // SABDv8i16
4578 2219362652U, // SABDv8i8
4579 369652326U, // SADALP_ZPmZ_D
4580 408982118U, // SADALP_ZPmZ_H
4581 369668710U, // SADALP_ZPmZ_S
4582 2487284326U, // SADALPv16i8_v8i16
4583 2515071590U, // SADALPv2i32_v1i64
4584 2485187174U, // SADALPv4i16_v2i32
4585 338227814U, // SADALPv4i32_v2i64
4586 2486760038U, // SADALPv8i16_v4i32
4587 338752102U, // SADALPv8i8_v4i16
4588 2617800160U, // SADDLBT_ZZZ_D
4589 264279520U, // SADDLBT_ZZZ_H
4590 2349381088U, // SADDLBT_ZZZ_S
4591 2617796017U, // SADDLB_ZZZ_D
4592 264275377U, // SADDLB_ZZZ_H
4593 2349376945U, // SADDLB_ZZZ_S
4594 2218840694U, // SADDLPv16i8_v8i16
4595 2246627958U, // SADDLPv2i32_v1i64
4596 2216743542U, // SADDLPv4i16_v2i32
4597 69784182U, // SADDLPv4i32_v2i64
4598 2218316406U, // SADDLPv8i16_v4i32
4599 70308470U, // SADDLPv8i8_v4i16
4600 2617800353U, // SADDLT_ZZZ_D
4601 264279713U, // SADDLT_ZZZ_H
4602 2349381281U, // SADDLT_ZZZ_S
4603 2215131291U, // SADDLVv16i8v
4604 2215131291U, // SADDLVv4i16v
4605 67647643U, // SADDLVv4i32v
4606 2215131291U, // SADDLVv8i16v
4607 67647643U, // SADDLVv8i8v
4608 71352566U, // SADDLv16i8_v8i16
4609 2217267122U, // SADDLv2i32_v2i64
4610 70832050U, // SADDLv4i16_v4i32
4611 69779702U, // SADDLv4i32_v2i64
4612 2218311926U, // SADDLv8i16_v4i32
4613 2218839986U, // SADDLv8i8_v8i16
4614 568408176U, // SADDV_VPZ_B
4615 545339504U, // SADDV_VPZ_H
4616 542718064U, // SADDV_VPZ_S
4617 2416470138U, // SADDWB_ZZZ_D
4618 241731706U, // SADDWB_ZZZ_H
4619 2617813114U, // SADDWB_ZZZ_S
4620 2416474132U, // SADDWT_ZZZ_D
4621 241735700U, // SADDWT_ZZZ_H
4622 2617817108U, // SADDWT_ZZZ_S
4623 2218836488U, // SADDWv16i8_v8i16
4624 2217269653U, // SADDWv2i32_v2i64
4625 70834581U, // SADDWv4i16_v4i32
4626 2217263624U, // SADDWv4i32_v2i64
4627 70828552U, // SADDWv8i16_v4i32
4628 2218842517U, // SADDWv8i8_v8i16
4629 7312U, // SB
4630 2282251658U, // SBCLB_ZZZ_D
4631 2315822474U, // SBCLB_ZZZ_S
4632 2282256003U, // SBCLT_ZZZ_D
4633 2315826819U, // SBCLT_ZZZ_S
4634 2248684790U, // SBCSWr
4635 2248684790U, // SBCSXr
4636 2248681667U, // SBCWr
4637 2248681667U, // SBCXr
4638 2248683762U, // SBFMWri
4639 2248683762U, // SBFMXri
4640 2248682197U, // SCVTFSWDri
4641 2248682197U, // SCVTFSWHri
4642 2248682197U, // SCVTFSWSri
4643 2248682197U, // SCVTFSXDri
4644 2248682197U, // SCVTFSXHri
4645 2248682197U, // SCVTFSXSri
4646 101198549U, // SCVTFUWDri
4647 101198549U, // SCVTFUWHri
4648 101198549U, // SCVTFUWSri
4649 101198549U, // SCVTFUXDri
4650 101198549U, // SCVTFUXHri
4651 101198549U, // SCVTFUXSri
4652 2148035285U, // SCVTF_ZPmZ_DtoD
4653 1141934805U, // SCVTF_ZPmZ_DtoH
4654 2148051669U, // SCVTF_ZPmZ_DtoS
4655 34638549U, // SCVTF_ZPmZ_HtoH
4656 551637U, // SCVTF_ZPmZ_StoD
4657 571509461U, // SCVTF_ZPmZ_StoH
4658 568021U, // SCVTF_ZPmZ_StoS
4659 2248682197U, // SCVTFd
4660 2248682197U, // SCVTFh
4661 2248682197U, // SCVTFs
4662 101198549U, // SCVTFv1i16
4663 101198549U, // SCVTFv1i32
4664 101198549U, // SCVTFv1i64
4665 2216741589U, // SCVTFv2f32
4666 69782229U, // SCVTFv2f64
4667 2216741589U, // SCVTFv2i32_shift
4668 2217265877U, // SCVTFv2i64_shift
4669 2217790165U, // SCVTFv4f16
4670 70830805U, // SCVTFv4f32
4671 70306517U, // SCVTFv4i16_shift
4672 70830805U, // SCVTFv4i32_shift
4673 2218838741U, // SCVTFv8f16
4674 2218838741U, // SCVTFv8i16_shift
4675 369652871U, // SDIVR_ZPmZ_D
4676 369669255U, // SDIVR_ZPmZ_S
4677 2248685711U, // SDIVWr
4678 2248685711U, // SDIVXr
4679 369653903U, // SDIV_ZPmZ_D
4680 369670287U, // SDIV_ZPmZ_S
4681 2450028478U, // SDOT_ZZZI_D
4682 705214398U, // SDOT_ZZZI_S
4683 2450028478U, // SDOT_ZZZ_D
4684 705214398U, // SDOT_ZZZ_S
4685 339277758U, // SDOTlanev16i8
4686 2485188542U, // SDOTlanev8i8
4687 339277758U, // SDOTv16i8
4688 2485188542U, // SDOTv8i8
4689 2517127115U, // SEL_PPPP
4690 2517127115U, // SEL_ZPZZ_B
4691 2517135307U, // SEL_ZPZZ_D
4692 2388692939U, // SEL_ZPZZ_H
4693 2517151691U, // SEL_ZPZZ_S
4694 8779U, // SETF16
4695 8794U, // SETF8
4696 7360U, // SETFFR
4697 2752112828U, // SHA1Crrr
4698 101198638U, // SHA1Hrr
4699 2752114923U, // SHA1Mrrr
4700 2752115233U, // SHA1Prrr
4701 339271681U, // SHA1SU0rrr
4702 339271764U, // SHA1SU1rr
4703 2752110746U, // SHA256H2rrr
4704 2752113558U, // SHA256Hrrr
4705 339271701U, // SHA256SU0rr
4706 339271784U, // SHA256SU1rrr
4707 2752113505U, // SHA512H
4708 2752110736U, // SHA512H2
4709 69779466U, // SHA512SU0
4710 2485706845U, // SHA512SU1
4711 369641915U, // SHADD_ZPmZ_B
4712 369650107U, // SHADD_ZPmZ_D
4713 2556463547U, // SHADD_ZPmZ_H
4714 369666491U, // SHADD_ZPmZ_S
4715 68733371U, // SHADDv16i8
4716 2216741307U, // SHADDv2i32
4717 70306235U, // SHADDv4i16
4718 70830523U, // SHADDv4i32
4719 2218838459U, // SHADDv8i16
4720 2219362747U, // SHADDv8i8
4721 2218836231U, // SHLLv16i8
4722 69783569U, // SHLLv2i32
4723 2218315793U, // SHLLv4i16
4724 69779719U, // SHLLv4i32
4725 2218311943U, // SHLLv8i16
4726 71356433U, // SHLLv8i8
4727 2248683482U, // SHLd
4728 68734938U, // SHLv16i8_shift
4729 2216742874U, // SHLv2i32_shift
4730 2217267162U, // SHLv2i64_shift
4731 70307802U, // SHLv4i16_shift
4732 70832090U, // SHLv4i32_shift
4733 2218840026U, // SHLv8i16_shift
4734 2219364314U, // SHLv8i8_shift
4735 2349352593U, // SHRNB_ZZI_B
4736 2387642001U, // SHRNB_ZZI_H
4737 2416486033U, // SHRNB_ZZI_S
4738 2450020172U, // SHRNT_ZZI_B
4739 240686924U, // SHRNT_ZZI_H
4740 2282272588U, // SHRNT_ZZI_S
4741 2484658550U, // SHRNv16i8_shift
4742 2216743299U, // SHRNv2i32_shift
4743 70308227U, // SHRNv4i16_shift
4744 2486755702U, // SHRNv4i32_shift
4745 339796342U, // SHRNv8i16_shift
4746 2219364739U, // SHRNv8i8_shift
4747 369644397U, // SHSUBR_ZPmZ_B
4748 369652589U, // SHSUBR_ZPmZ_D
4749 2556466029U, // SHSUBR_ZPmZ_H
4750 369668973U, // SHSUBR_ZPmZ_S
4751 369641529U, // SHSUB_ZPmZ_B
4752 369649721U, // SHSUB_ZPmZ_D
4753 2556463161U, // SHSUB_ZPmZ_H
4754 369666105U, // SHSUB_ZPmZ_S
4755 68732985U, // SHSUBv16i8
4756 2216740921U, // SHSUBv2i32
4757 70305849U, // SHSUBv4i16
4758 70830137U, // SHSUBv4i32
4759 2218838073U, // SHSUBv8i16
4760 2219362361U, // SHSUBv8i8
4761 705187501U, // SLI_ZZI_B
4762 2282253997U, // SLI_ZZI_D
4763 243306157U, // SLI_ZZI_H
4764 2315824813U, // SLI_ZZI_S
4765 2752114349U, // SLId
4766 337178285U, // SLIv16i8_shift
4767 2485186221U, // SLIv2i32_shift
4768 2485710509U, // SLIv2i64_shift
4769 338751149U, // SLIv4i16_shift
4770 339275437U, // SLIv4i32_shift
4771 2487283373U, // SLIv8i16_shift
4772 2487807661U, // SLIv8i8_shift
4773 339271795U, // SM3PARTW1
4774 339272216U, // SM3PARTW2
4775 70828103U, // SM3SS1
4776 339272289U, // SM3TT1A
4777 339272649U, // SM3TT1B
4778 339272298U, // SM3TT2A
4779 339272678U, // SM3TT2B
4780 70830621U, // SM4E
4781 2617817774U, // SM4EKEY_ZZZ_S
4782 70834862U, // SM4ENCKEY
4783 2617813533U, // SM4E_ZZZ_S
4784 2248683426U, // SMADDLrrr
4785 369644292U, // SMAXP_ZPmZ_B
4786 369652484U, // SMAXP_ZPmZ_D
4787 2556465924U, // SMAXP_ZPmZ_H
4788 369668868U, // SMAXP_ZPmZ_S
4789 68735748U, // SMAXPv16i8
4790 2216743684U, // SMAXPv2i32
4791 70308612U, // SMAXPv4i16
4792 70832900U, // SMAXPv4i32
4793 2218840836U, // SMAXPv8i16
4794 2219365124U, // SMAXPv8i8
4795 71928U, // SMAXV_VPZ_B
4796 544815352U, // SMAXV_VPZ_D
4797 545347832U, // SMAXV_VPZ_H
4798 542734584U, // SMAXV_VPZ_S
4799 2215131384U, // SMAXVv16i8v
4800 2215131384U, // SMAXVv4i16v
4801 67647736U, // SMAXVv4i32v
4802 2215131384U, // SMAXVv8i16v
4803 67647736U, // SMAXVv8i8v
4804 2584238685U, // SMAX_ZI_B
4805 2416474717U, // SMAX_ZI_D
4806 2389219933U, // SMAX_ZI_H
4807 2617817693U, // SMAX_ZI_S
4808 369646173U, // SMAX_ZPmZ_B
4809 369654365U, // SMAX_ZPmZ_D
4810 2556467805U, // SMAX_ZPmZ_H
4811 369670749U, // SMAX_ZPmZ_S
4812 68737629U, // SMAXv16i8
4813 2216745565U, // SMAXv2i32
4814 70310493U, // SMAXv4i16
4815 70834781U, // SMAXv4i32
4816 2218842717U, // SMAXv8i16
4817 2219367005U, // SMAXv8i8
4818 108764U, // SMC
4819 369644210U, // SMINP_ZPmZ_B
4820 369652402U, // SMINP_ZPmZ_D
4821 2556465842U, // SMINP_ZPmZ_H
4822 369668786U, // SMINP_ZPmZ_S
4823 68735666U, // SMINPv16i8
4824 2216743602U, // SMINPv2i32
4825 70308530U, // SMINPv4i16
4826 70832818U, // SMINPv4i32
4827 2218840754U, // SMINPv8i16
4828 2219365042U, // SMINPv8i8
4829 71876U, // SMINV_VPZ_B
4830 544815300U, // SMINV_VPZ_D
4831 545347780U, // SMINV_VPZ_H
4832 542734532U, // SMINV_VPZ_S
4833 2215131332U, // SMINVv16i8v
4834 2215131332U, // SMINVv4i16v
4835 67647684U, // SMINVv4i32v
4836 2215131332U, // SMINVv8i16v
4837 67647684U, // SMINVv8i8v
4838 2584236386U, // SMIN_ZI_B
4839 2416472418U, // SMIN_ZI_D
4840 2389217634U, // SMIN_ZI_H
4841 2617815394U, // SMIN_ZI_S
4842 369643874U, // SMIN_ZPmZ_B
4843 369652066U, // SMIN_ZPmZ_D
4844 2556465506U, // SMIN_ZPmZ_H
4845 369668450U, // SMIN_ZPmZ_S
4846 68735330U, // SMINv16i8
4847 2216743266U, // SMINv2i32
4848 70308194U, // SMINv4i16
4849 70832482U, // SMINv4i32
4850 2218840418U, // SMINv8i16
4851 2219364706U, // SMINv8i8
4852 2315805968U, // SMLALB_ZZZI_D
4853 2450040080U, // SMLALB_ZZZI_S
4854 2315805968U, // SMLALB_ZZZ_D
4855 266372368U, // SMLALB_ZZZ_H
4856 2450040080U, // SMLALB_ZZZ_S
4857 2315810403U, // SMLALT_ZZZI_D
4858 2450044515U, // SMLALT_ZZZI_S
4859 2315810403U, // SMLALT_ZZZ_D
4860 266376803U, // SMLALT_ZZZ_H
4861 2450044515U, // SMLALT_ZZZ_S
4862 339796166U, // SMLALv16i8_v8i16
4863 2485710594U, // SMLALv2i32_indexed
4864 2485710594U, // SMLALv2i32_v2i64
4865 339275522U, // SMLALv4i16_indexed
4866 339275522U, // SMLALv4i16_v4i32
4867 338223302U, // SMLALv4i32_indexed
4868 338223302U, // SMLALv4i32_v2i64
4869 2486755526U, // SMLALv8i16_indexed
4870 2486755526U, // SMLALv8i16_v4i32
4871 2487283458U, // SMLALv8i8_v8i16
4872 2315806265U, // SMLSLB_ZZZI_D
4873 2450040377U, // SMLSLB_ZZZI_S
4874 2315806265U, // SMLSLB_ZZZ_D
4875 266372665U, // SMLSLB_ZZZ_H
4876 2450040377U, // SMLSLB_ZZZ_S
4877 2315810577U, // SMLSLT_ZZZI_D
4878 2450044689U, // SMLSLT_ZZZI_S
4879 2315810577U, // SMLSLT_ZZZ_D
4880 266376977U, // SMLSLT_ZZZ_H
4881 2450044689U, // SMLSLT_ZZZ_S
4882 339796298U, // SMLSLv16i8_v8i16
4883 2485710990U, // SMLSLv2i32_indexed
4884 2485710990U, // SMLSLv2i32_v2i64
4885 339275918U, // SMLSLv4i16_indexed
4886 339275918U, // SMLSLv4i16_v4i32
4887 338223434U, // SMLSLv4i32_indexed
4888 338223434U, // SMLSLv4i32_v2i64
4889 2486755658U, // SMLSLv8i16_indexed
4890 2486755658U, // SMLSLv8i16_v4i32
4891 2487283854U, // SMLSLv8i8_v8i16
4892 339272417U, // SMMLA
4893 705209057U, // SMMLA_ZZZ
4894 67647711U, // SMOVvi16to32
4895 67647711U, // SMOVvi16to64
4896 2215131359U, // SMOVvi32to64
4897 2215131359U, // SMOVvi8to32
4898 2215131359U, // SMOVvi8to64
4899 2248683374U, // SMSUBLrrr
4900 369642762U, // SMULH_ZPmZ_B
4901 369650954U, // SMULH_ZPmZ_D
4902 2556464394U, // SMULH_ZPmZ_H
4903 369667338U, // SMULH_ZPmZ_S
4904 2584235274U, // SMULH_ZZZ_B
4905 2416471306U, // SMULH_ZZZ_D
4906 2389216522U, // SMULH_ZZZ_H
4907 2617814282U, // SMULH_ZZZ_S
4908 2248682762U, // SMULHrr
4909 2617796067U, // SMULLB_ZZZI_D
4910 2349376995U, // SMULLB_ZZZI_S
4911 2617796067U, // SMULLB_ZZZ_D
4912 264275427U, // SMULLB_ZZZ_H
4913 2349376995U, // SMULLB_ZZZ_S
4914 2617800417U, // SMULLT_ZZZI_D
4915 2349381345U, // SMULLT_ZZZI_S
4916 2617800417U, // SMULLT_ZZZ_D
4917 264279777U, // SMULLT_ZZZ_H
4918 2349381345U, // SMULLT_ZZZ_S
4919 71352616U, // SMULLv16i8_v8i16
4920 2217267246U, // SMULLv2i32_indexed
4921 2217267246U, // SMULLv2i32_v2i64
4922 70832174U, // SMULLv4i16_indexed
4923 70832174U, // SMULLv4i16_v4i32
4924 69779752U, // SMULLv4i32_indexed
4925 69779752U, // SMULLv4i32_v2i64
4926 2218311976U, // SMULLv8i16_indexed
4927 2218311976U, // SMULLv8i16_v4i32
4928 2218840110U, // SMULLv8i8_v8i16
4929 2517125667U, // SPLICE_ZPZZ_B
4930 2517133859U, // SPLICE_ZPZZ_D
4931 2388691491U, // SPLICE_ZPZZ_H
4932 2517150243U, // SPLICE_ZPZZ_S
4933 2517125667U, // SPLICE_ZPZ_B
4934 2517133859U, // SPLICE_ZPZ_D
4935 2388691491U, // SPLICE_ZPZ_H
4936 2517150243U, // SPLICE_ZPZ_S
4937 546010U, // SQABS_ZPmZ_B
4938 2148037850U, // SQABS_ZPmZ_D
4939 34641114U, // SQABS_ZPmZ_H
4940 570586U, // SQABS_ZPmZ_S
4941 2216219866U, // SQABSv16i8
4942 101201114U, // SQABSv1i16
4943 101201114U, // SQABSv1i32
4944 101201114U, // SQABSv1i64
4945 101201114U, // SQABSv1i8
4946 2216744154U, // SQABSv2i32
4947 69784794U, // SQABSv2i64
4948 2217792730U, // SQABSv4i16
4949 70833370U, // SQABSv4i32
4950 2218841306U, // SQABSv8i16
4951 71881946U, // SQABSv8i8
4952 2584234457U, // SQADD_ZI_B
4953 2416470489U, // SQADD_ZI_D
4954 241732057U, // SQADD_ZI_H
4955 2617813465U, // SQADD_ZI_S
4956 369641945U, // SQADD_ZPmZ_B
4957 369650137U, // SQADD_ZPmZ_D
4958 2556463577U, // SQADD_ZPmZ_H
4959 369666521U, // SQADD_ZPmZ_S
4960 2584234457U, // SQADD_ZZZ_B
4961 2416470489U, // SQADD_ZZZ_D
4962 2389215705U, // SQADD_ZZZ_H
4963 2617813465U, // SQADD_ZZZ_S
4964 68733401U, // SQADDv16i8
4965 2248681945U, // SQADDv1i16
4966 2248681945U, // SQADDv1i32
4967 2248681945U, // SQADDv1i64
4968 2248681945U, // SQADDv1i8
4969 2216741337U, // SQADDv2i32
4970 2217265625U, // SQADDv2i64
4971 70306265U, // SQADDv4i16
4972 70830553U, // SQADDv4i32
4973 2218838489U, // SQADDv8i16
4974 2219362777U, // SQADDv8i8
4975 2584234390U, // SQCADD_ZZI_B
4976 2416470422U, // SQCADD_ZZI_D
4977 2389215638U, // SQCADD_ZZI_H
4978 2617813398U, // SQCADD_ZZI_S
4979 872948876U, // SQDECB_XPiI
4980 1510483084U, // SQDECB_XPiWdI
4981 872950127U, // SQDECD_XPiI
4982 1510484335U, // SQDECD_XPiWdI
4983 872966511U, // SQDECD_ZPiI
4984 872950807U, // SQDECH_XPiI
4985 1510485015U, // SQDECH_XPiWdI
4986 8948759U, // SQDECH_ZPiI
4987 2584228398U, // SQDECP_XPWd_B
4988 2416456238U, // SQDECP_XPWd_D
4989 2349347374U, // SQDECP_XPWd_H
4990 2617782830U, // SQDECP_XPWd_S
4991 436744750U, // SQDECP_XP_B
4992 268972590U, // SQDECP_XP_D
4993 201863726U, // SQDECP_XP_H
4994 470299182U, // SQDECP_XP_S
4995 134771246U, // SQDECP_ZP_D
4996 545296942U, // SQDECP_ZP_H
4997 168342062U, // SQDECP_ZP_S
4998 872954229U, // SQDECW_XPiI
4999 1510488437U, // SQDECW_XPiWdI
5000 872986997U, // SQDECW_ZPiI
5001 2315810252U, // SQDMLALBT_ZZZ_D
5002 266376652U, // SQDMLALBT_ZZZ_H
5003 2450044364U, // SQDMLALBT_ZZZ_S
5004 2315805949U, // SQDMLALB_ZZZI_D
5005 2450040061U, // SQDMLALB_ZZZI_S
5006 2315805949U, // SQDMLALB_ZZZ_D
5007 266372349U, // SQDMLALB_ZZZ_H
5008 2450040061U, // SQDMLALB_ZZZ_S
5009 2315810384U, // SQDMLALT_ZZZI_D
5010 2450044496U, // SQDMLALT_ZZZI_S
5011 2315810384U, // SQDMLALT_ZZZ_D
5012 266376784U, // SQDMLALT_ZZZ_H
5013 2450044496U, // SQDMLALT_ZZZ_S
5014 2752114418U, // SQDMLALi16
5015 2752114418U, // SQDMLALi32
5016 2752114418U, // SQDMLALv1i32_indexed
5017 2752114418U, // SQDMLALv1i64_indexed
5018 2485710578U, // SQDMLALv2i32_indexed
5019 2485710578U, // SQDMLALv2i32_v2i64
5020 339275506U, // SQDMLALv4i16_indexed
5021 339275506U, // SQDMLALv4i16_v4i32
5022 338223284U, // SQDMLALv4i32_indexed
5023 338223284U, // SQDMLALv4i32_v2i64
5024 2486755508U, // SQDMLALv8i16_indexed
5025 2486755508U, // SQDMLALv8i16_v4i32
5026 2315810281U, // SQDMLSLBT_ZZZ_D
5027 266376681U, // SQDMLSLBT_ZZZ_H
5028 2450044393U, // SQDMLSLBT_ZZZ_S
5029 2315806247U, // SQDMLSLB_ZZZI_D
5030 2450040359U, // SQDMLSLB_ZZZI_S
5031 2315806247U, // SQDMLSLB_ZZZ_D
5032 266372647U, // SQDMLSLB_ZZZ_H
5033 2450040359U, // SQDMLSLB_ZZZ_S
5034 2315810559U, // SQDMLSLT_ZZZI_D
5035 2450044671U, // SQDMLSLT_ZZZI_S
5036 2315810559U, // SQDMLSLT_ZZZ_D
5037 266376959U, // SQDMLSLT_ZZZ_H
5038 2450044671U, // SQDMLSLT_ZZZ_S
5039 2752114814U, // SQDMLSLi16
5040 2752114814U, // SQDMLSLi32
5041 2752114814U, // SQDMLSLv1i32_indexed
5042 2752114814U, // SQDMLSLv1i64_indexed
5043 2485710974U, // SQDMLSLv2i32_indexed
5044 2485710974U, // SQDMLSLv2i32_v2i64
5045 339275902U, // SQDMLSLv4i16_indexed
5046 339275902U, // SQDMLSLv4i16_v4i32
5047 338223416U, // SQDMLSLv4i32_indexed
5048 338223416U, // SQDMLSLv4i32_v2i64
5049 2486755640U, // SQDMLSLv8i16_indexed
5050 2486755640U, // SQDMLSLv8i16_v4i32
5051 2416471287U, // SQDMULH_ZZZI_D
5052 2389216503U, // SQDMULH_ZZZI_H
5053 2617814263U, // SQDMULH_ZZZI_S
5054 2584235255U, // SQDMULH_ZZZ_B
5055 2416471287U, // SQDMULH_ZZZ_D
5056 2389216503U, // SQDMULH_ZZZ_H
5057 2617814263U, // SQDMULH_ZZZ_S
5058 2248682743U, // SQDMULHv1i16
5059 2248682743U, // SQDMULHv1i16_indexed
5060 2248682743U, // SQDMULHv1i32
5061 2248682743U, // SQDMULHv1i32_indexed
5062 2216742135U, // SQDMULHv2i32
5063 2216742135U, // SQDMULHv2i32_indexed
5064 70307063U, // SQDMULHv4i16
5065 70307063U, // SQDMULHv4i16_indexed
5066 70831351U, // SQDMULHv4i32
5067 70831351U, // SQDMULHv4i32_indexed
5068 2218839287U, // SQDMULHv8i16
5069 2218839287U, // SQDMULHv8i16_indexed
5070 2617796049U, // SQDMULLB_ZZZI_D
5071 2349376977U, // SQDMULLB_ZZZI_S
5072 2617796049U, // SQDMULLB_ZZZ_D
5073 264275409U, // SQDMULLB_ZZZ_H
5074 2349376977U, // SQDMULLB_ZZZ_S
5075 2617800399U, // SQDMULLT_ZZZI_D
5076 2349381327U, // SQDMULLT_ZZZI_S
5077 2617800399U, // SQDMULLT_ZZZ_D
5078 264279759U, // SQDMULLT_ZZZ_H
5079 2349381327U, // SQDMULLT_ZZZ_S
5080 2248683550U, // SQDMULLi16
5081 2248683550U, // SQDMULLi32
5082 2248683550U, // SQDMULLv1i32_indexed
5083 2248683550U, // SQDMULLv1i64_indexed
5084 2217267230U, // SQDMULLv2i32_indexed
5085 2217267230U, // SQDMULLv2i32_v2i64
5086 70832158U, // SQDMULLv4i16_indexed
5087 70832158U, // SQDMULLv4i16_v4i32
5088 69779734U, // SQDMULLv4i32_indexed
5089 69779734U, // SQDMULLv4i32_v2i64
5090 2218311958U, // SQDMULLv8i16_indexed
5091 2218311958U, // SQDMULLv8i16_v4i32
5092 872948892U, // SQINCB_XPiI
5093 1510483100U, // SQINCB_XPiWdI
5094 872950143U, // SQINCD_XPiI
5095 1510484351U, // SQINCD_XPiWdI
5096 872966527U, // SQINCD_ZPiI
5097 872950823U, // SQINCH_XPiI
5098 1510485031U, // SQINCH_XPiWdI
5099 8948775U, // SQINCH_ZPiI
5100 2584228414U, // SQINCP_XPWd_B
5101 2416456254U, // SQINCP_XPWd_D
5102 2349347390U, // SQINCP_XPWd_H
5103 2617782846U, // SQINCP_XPWd_S
5104 436744766U, // SQINCP_XP_B
5105 268972606U, // SQINCP_XP_D
5106 201863742U, // SQINCP_XP_H
5107 470299198U, // SQINCP_XP_S
5108 134771262U, // SQINCP_ZP_D
5109 545296958U, // SQINCP_ZP_H
5110 168342078U, // SQINCP_ZP_S
5111 872954245U, // SQINCW_XPiI
5112 1510488453U, // SQINCW_XPiWdI
5113 872987013U, // SQINCW_ZPiI
5114 543495U, // SQNEG_ZPmZ_B
5115 2148035335U, // SQNEG_ZPmZ_D
5116 34638599U, // SQNEG_ZPmZ_H
5117 568071U, // SQNEG_ZPmZ_S
5118 2216217351U, // SQNEGv16i8
5119 101198599U, // SQNEGv1i16
5120 101198599U, // SQNEGv1i32
5121 101198599U, // SQNEGv1i64
5122 101198599U, // SQNEGv1i8
5123 2216741639U, // SQNEGv2i32
5124 69782279U, // SQNEGv2i64
5125 2217790215U, // SQNEGv4i16
5126 70830855U, // SQNEGv4i32
5127 2218838791U, // SQNEGv8i16
5128 71879431U, // SQNEGv8i8
5129 2390789032U, // SQRDCMLAH_ZZZI_H
5130 2315824040U, // SQRDCMLAH_ZZZI_S
5131 705186728U, // SQRDCMLAH_ZZZ_B
5132 2282253224U, // SQRDCMLAH_ZZZ_D
5133 2390789032U, // SQRDCMLAH_ZZZ_H
5134 2315824040U, // SQRDCMLAH_ZZZ_S
5135 2282253235U, // SQRDMLAH_ZZZI_D
5136 2390789043U, // SQRDMLAH_ZZZI_H
5137 2315824051U, // SQRDMLAH_ZZZI_S
5138 705186739U, // SQRDMLAH_ZZZ_B
5139 2282253235U, // SQRDMLAH_ZZZ_D
5140 2390789043U, // SQRDMLAH_ZZZ_H
5141 2315824051U, // SQRDMLAH_ZZZ_S
5142 2752113587U, // SQRDMLAHi16_indexed
5143 2752113587U, // SQRDMLAHi32_indexed
5144 2752113587U, // SQRDMLAHv1i16
5145 2752113587U, // SQRDMLAHv1i32
5146 2485185459U, // SQRDMLAHv2i32
5147 2485185459U, // SQRDMLAHv2i32_indexed
5148 338750387U, // SQRDMLAHv4i16
5149 338750387U, // SQRDMLAHv4i16_indexed
5150 339274675U, // SQRDMLAHv4i32
5151 339274675U, // SQRDMLAHv4i32_indexed
5152 2487282611U, // SQRDMLAHv8i16
5153 2487282611U, // SQRDMLAHv8i16_indexed
5154 2282253840U, // SQRDMLSH_ZZZI_D
5155 2390789648U, // SQRDMLSH_ZZZI_H
5156 2315824656U, // SQRDMLSH_ZZZI_S
5157 705187344U, // SQRDMLSH_ZZZ_B
5158 2282253840U, // SQRDMLSH_ZZZ_D
5159 2390789648U, // SQRDMLSH_ZZZ_H
5160 2315824656U, // SQRDMLSH_ZZZ_S
5161 2752114192U, // SQRDMLSHi16_indexed
5162 2752114192U, // SQRDMLSHi32_indexed
5163 2752114192U, // SQRDMLSHv1i16
5164 2752114192U, // SQRDMLSHv1i32
5165 2485186064U, // SQRDMLSHv2i32
5166 2485186064U, // SQRDMLSHv2i32_indexed
5167 338750992U, // SQRDMLSHv4i16
5168 338750992U, // SQRDMLSHv4i16_indexed
5169 339275280U, // SQRDMLSHv4i32
5170 339275280U, // SQRDMLSHv4i32_indexed
5171 2487283216U, // SQRDMLSHv8i16
5172 2487283216U, // SQRDMLSHv8i16_indexed
5173 2416471296U, // SQRDMULH_ZZZI_D
5174 2389216512U, // SQRDMULH_ZZZI_H
5175 2617814272U, // SQRDMULH_ZZZI_S
5176 2584235264U, // SQRDMULH_ZZZ_B
5177 2416471296U, // SQRDMULH_ZZZ_D
5178 2389216512U, // SQRDMULH_ZZZ_H
5179 2617814272U, // SQRDMULH_ZZZ_S
5180 2248682752U, // SQRDMULHv1i16
5181 2248682752U, // SQRDMULHv1i16_indexed
5182 2248682752U, // SQRDMULHv1i32
5183 2248682752U, // SQRDMULHv1i32_indexed
5184 2216742144U, // SQRDMULHv2i32
5185 2216742144U, // SQRDMULHv2i32_indexed
5186 70307072U, // SQRDMULHv4i16
5187 70307072U, // SQRDMULHv4i16_indexed
5188 70831360U, // SQRDMULHv4i32
5189 70831360U, // SQRDMULHv4i32_indexed
5190 2218839296U, // SQRDMULHv8i16
5191 2218839296U, // SQRDMULHv8i16_indexed
5192 369644507U, // SQRSHLR_ZPmZ_B
5193 369652699U, // SQRSHLR_ZPmZ_D
5194 2556466139U, // SQRSHLR_ZPmZ_H
5195 369669083U, // SQRSHLR_ZPmZ_S
5196 369643494U, // SQRSHL_ZPmZ_B
5197 369651686U, // SQRSHL_ZPmZ_D
5198 2556465126U, // SQRSHL_ZPmZ_H
5199 369668070U, // SQRSHL_ZPmZ_S
5200 68734950U, // SQRSHLv16i8
5201 2248683494U, // SQRSHLv1i16
5202 2248683494U, // SQRSHLv1i32
5203 2248683494U, // SQRSHLv1i64
5204 2248683494U, // SQRSHLv1i8
5205 2216742886U, // SQRSHLv2i32
5206 2217267174U, // SQRSHLv2i64
5207 70307814U, // SQRSHLv4i16
5208 70832102U, // SQRSHLv4i32
5209 2218840038U, // SQRSHLv8i16
5210 2219364326U, // SQRSHLv8i8
5211 2349352609U, // SQRSHRNB_ZZI_B
5212 2387642017U, // SQRSHRNB_ZZI_H
5213 2416486049U, // SQRSHRNB_ZZI_S
5214 2450020188U, // SQRSHRNT_ZZI_B
5215 240686940U, // SQRSHRNT_ZZI_H
5216 2282272604U, // SQRSHRNT_ZZI_S
5217 2248683921U, // SQRSHRNb
5218 2248683921U, // SQRSHRNh
5219 2248683921U, // SQRSHRNs
5220 2484658566U, // SQRSHRNv16i8_shift
5221 2216743313U, // SQRSHRNv2i32_shift
5222 70308241U, // SQRSHRNv4i16_shift
5223 2486755718U, // SQRSHRNv4i32_shift
5224 339796358U, // SQRSHRNv8i16_shift
5225 2219364753U, // SQRSHRNv8i8_shift
5226 2349352655U, // SQRSHRUNB_ZZI_B
5227 2387642063U, // SQRSHRUNB_ZZI_H
5228 2416486095U, // SQRSHRUNB_ZZI_S
5229 2450020243U, // SQRSHRUNT_ZZI_B
5230 240686995U, // SQRSHRUNT_ZZI_H
5231 2282272659U, // SQRSHRUNT_ZZI_S
5232 2248683983U, // SQRSHRUNb
5233 2248683983U, // SQRSHRUNh
5234 2248683983U, // SQRSHRUNs
5235 2484658627U, // SQRSHRUNv16i8_shift
5236 2216743375U, // SQRSHRUNv2i32_shift
5237 70308303U, // SQRSHRUNv4i16_shift
5238 2486755779U, // SQRSHRUNv4i32_shift
5239 339796419U, // SQRSHRUNv8i16_shift
5240 2219364815U, // SQRSHRUNv8i8_shift
5241 369644491U, // SQSHLR_ZPmZ_B
5242 369652683U, // SQSHLR_ZPmZ_D
5243 2556466123U, // SQSHLR_ZPmZ_H
5244 369669067U, // SQSHLR_ZPmZ_S
5245 369645625U, // SQSHLU_ZPmI_B
5246 369653817U, // SQSHLU_ZPmI_D
5247 2556467257U, // SQSHLU_ZPmI_H
5248 369670201U, // SQSHLU_ZPmI_S
5249 2248685625U, // SQSHLUb
5250 2248685625U, // SQSHLUd
5251 2248685625U, // SQSHLUh
5252 2248685625U, // SQSHLUs
5253 68737081U, // SQSHLUv16i8_shift
5254 2216745017U, // SQSHLUv2i32_shift
5255 2217269305U, // SQSHLUv2i64_shift
5256 70309945U, // SQSHLUv4i16_shift
5257 70834233U, // SQSHLUv4i32_shift
5258 2218842169U, // SQSHLUv8i16_shift
5259 2219366457U, // SQSHLUv8i8_shift
5260 369643480U, // SQSHL_ZPmI_B
5261 369651672U, // SQSHL_ZPmI_D
5262 2556465112U, // SQSHL_ZPmI_H
5263 369668056U, // SQSHL_ZPmI_S
5264 369643480U, // SQSHL_ZPmZ_B
5265 369651672U, // SQSHL_ZPmZ_D
5266 2556465112U, // SQSHL_ZPmZ_H
5267 369668056U, // SQSHL_ZPmZ_S
5268 2248683480U, // SQSHLb
5269 2248683480U, // SQSHLd
5270 2248683480U, // SQSHLh
5271 2248683480U, // SQSHLs
5272 68734936U, // SQSHLv16i8
5273 68734936U, // SQSHLv16i8_shift
5274 2248683480U, // SQSHLv1i16
5275 2248683480U, // SQSHLv1i32
5276 2248683480U, // SQSHLv1i64
5277 2248683480U, // SQSHLv1i8
5278 2216742872U, // SQSHLv2i32
5279 2216742872U, // SQSHLv2i32_shift
5280 2217267160U, // SQSHLv2i64
5281 2217267160U, // SQSHLv2i64_shift
5282 70307800U, // SQSHLv4i16
5283 70307800U, // SQSHLv4i16_shift
5284 70832088U, // SQSHLv4i32
5285 70832088U, // SQSHLv4i32_shift
5286 2218840024U, // SQSHLv8i16
5287 2218840024U, // SQSHLv8i16_shift
5288 2219364312U, // SQSHLv8i8
5289 2219364312U, // SQSHLv8i8_shift
5290 2349352591U, // SQSHRNB_ZZI_B
5291 2387641999U, // SQSHRNB_ZZI_H
5292 2416486031U, // SQSHRNB_ZZI_S
5293 2450020170U, // SQSHRNT_ZZI_B
5294 240686922U, // SQSHRNT_ZZI_H
5295 2282272586U, // SQSHRNT_ZZI_S
5296 2248683905U, // SQSHRNb
5297 2248683905U, // SQSHRNh
5298 2248683905U, // SQSHRNs
5299 2484658548U, // SQSHRNv16i8_shift
5300 2216743297U, // SQSHRNv2i32_shift
5301 70308225U, // SQSHRNv4i16_shift
5302 2486755700U, // SQSHRNv4i32_shift
5303 339796340U, // SQSHRNv8i16_shift
5304 2219364737U, // SQSHRNv8i8_shift
5305 2349352645U, // SQSHRUNB_ZZI_B
5306 2387642053U, // SQSHRUNB_ZZI_H
5307 2416486085U, // SQSHRUNB_ZZI_S
5308 2450020233U, // SQSHRUNT_ZZI_B
5309 240686985U, // SQSHRUNT_ZZI_H
5310 2282272649U, // SQSHRUNT_ZZI_S
5311 2248683974U, // SQSHRUNb
5312 2248683974U, // SQSHRUNh
5313 2248683974U, // SQSHRUNs
5314 2484658617U, // SQSHRUNv16i8_shift
5315 2216743366U, // SQSHRUNv2i32_shift
5316 70308294U, // SQSHRUNv4i16_shift
5317 2486755769U, // SQSHRUNv4i32_shift
5318 339796409U, // SQSHRUNv8i16_shift
5319 2219364806U, // SQSHRUNv8i8_shift
5320 369644413U, // SQSUBR_ZPmZ_B
5321 369652605U, // SQSUBR_ZPmZ_D
5322 2556466045U, // SQSUBR_ZPmZ_H
5323 369668989U, // SQSUBR_ZPmZ_S
5324 2584234070U, // SQSUB_ZI_B
5325 2416470102U, // SQSUB_ZI_D
5326 241731670U, // SQSUB_ZI_H
5327 2617813078U, // SQSUB_ZI_S
5328 369641558U, // SQSUB_ZPmZ_B
5329 369649750U, // SQSUB_ZPmZ_D
5330 2556463190U, // SQSUB_ZPmZ_H
5331 369666134U, // SQSUB_ZPmZ_S
5332 2584234070U, // SQSUB_ZZZ_B
5333 2416470102U, // SQSUB_ZZZ_D
5334 2389215318U, // SQSUB_ZZZ_H
5335 2617813078U, // SQSUB_ZZZ_S
5336 68733014U, // SQSUBv16i8
5337 2248681558U, // SQSUBv1i16
5338 2248681558U, // SQSUBv1i32
5339 2248681558U, // SQSUBv1i64
5340 2248681558U, // SQSUBv1i8
5341 2216740950U, // SQSUBv2i32
5342 2217265238U, // SQSUBv2i64
5343 70305878U, // SQSUBv4i16
5344 70830166U, // SQSUBv4i32
5345 2218838102U, // SQSUBv8i16
5346 2219362390U, // SQSUBv8i8
5347 201868981U, // SQXTNB_ZZ_B
5348 542148277U, // SQXTNB_ZZ_H
5349 269002421U, // SQXTNB_ZZ_S
5350 302536569U, // SQXTNT_ZZ_B
5351 542676857U, // SQXTNT_ZZ_H
5352 134788985U, // SQXTNT_ZZ_S
5353 2484658601U, // SQXTNv16i8
5354 101200312U, // SQXTNv1i16
5355 101200312U, // SQXTNv1i32
5356 101200312U, // SQXTNv1i8
5357 69259704U, // SQXTNv2i32
5358 70308280U, // SQXTNv4i16
5359 339272105U, // SQXTNv4i32
5360 339796393U, // SQXTNv8i16
5361 2219364792U, // SQXTNv8i8
5362 201869018U, // SQXTUNB_ZZ_B
5363 542148314U, // SQXTUNB_ZZ_H
5364 269002458U, // SQXTUNB_ZZ_S
5365 302536606U, // SQXTUNT_ZZ_B
5366 542676894U, // SQXTUNT_ZZ_H
5367 134789022U, // SQXTUNT_ZZ_S
5368 2484658638U, // SQXTUNv16i8
5369 101200345U, // SQXTUNv1i16
5370 101200345U, // SQXTUNv1i32
5371 101200345U, // SQXTUNv1i8
5372 69259737U, // SQXTUNv2i32
5373 70308313U, // SQXTUNv4i16
5374 339272142U, // SQXTUNv4i32
5375 339796430U, // SQXTUNv8i16
5376 2219364825U, // SQXTUNv8i8
5377 369641899U, // SRHADD_ZPmZ_B
5378 369650091U, // SRHADD_ZPmZ_D
5379 2556463531U, // SRHADD_ZPmZ_H
5380 369666475U, // SRHADD_ZPmZ_S
5381 68733355U, // SRHADDv16i8
5382 2216741291U, // SRHADDv2i32
5383 70306219U, // SRHADDv4i16
5384 70830507U, // SRHADDv4i32
5385 2218838443U, // SRHADDv8i16
5386 2219362731U, // SRHADDv8i8
5387 705187517U, // SRI_ZZI_B
5388 2282254013U, // SRI_ZZI_D
5389 243306173U, // SRI_ZZI_H
5390 2315824829U, // SRI_ZZI_S
5391 2752114365U, // SRId
5392 337178301U, // SRIv16i8_shift
5393 2485186237U, // SRIv2i32_shift
5394 2485710525U, // SRIv2i64_shift
5395 338751165U, // SRIv4i16_shift
5396 339275453U, // SRIv4i32_shift
5397 2487283389U, // SRIv8i16_shift
5398 2487807677U, // SRIv8i8_shift
5399 369644525U, // SRSHLR_ZPmZ_B
5400 369652717U, // SRSHLR_ZPmZ_D
5401 2556466157U, // SRSHLR_ZPmZ_H
5402 369669101U, // SRSHLR_ZPmZ_S
5403 369643510U, // SRSHL_ZPmZ_B
5404 369651702U, // SRSHL_ZPmZ_D
5405 2556465142U, // SRSHL_ZPmZ_H
5406 369668086U, // SRSHL_ZPmZ_S
5407 68734966U, // SRSHLv16i8
5408 2248683510U, // SRSHLv1i64
5409 2216742902U, // SRSHLv2i32
5410 2217267190U, // SRSHLv2i64
5411 70307830U, // SRSHLv4i16
5412 70832118U, // SRSHLv4i32
5413 2218840054U, // SRSHLv8i16
5414 2219364342U, // SRSHLv8i8
5415 369644453U, // SRSHR_ZPmI_B
5416 369652645U, // SRSHR_ZPmI_D
5417 2556466085U, // SRSHR_ZPmI_H
5418 369669029U, // SRSHR_ZPmI_S
5419 2248684453U, // SRSHRd
5420 68735909U, // SRSHRv16i8_shift
5421 2216743845U, // SRSHRv2i32_shift
5422 2217268133U, // SRSHRv2i64_shift
5423 70308773U, // SRSHRv4i16_shift
5424 70833061U, // SRSHRv4i32_shift
5425 2218840997U, // SRSHRv8i16_shift
5426 2219365285U, // SRSHRv8i8_shift
5427 705184563U, // SRSRA_ZZI_B
5428 2282251059U, // SRSRA_ZZI_D
5429 243303219U, // SRSRA_ZZI_H
5430 2315821875U, // SRSRA_ZZI_S
5431 2752111411U, // SRSRAd
5432 337175347U, // SRSRAv16i8_shift
5433 2485183283U, // SRSRAv2i32_shift
5434 2485707571U, // SRSRAv2i64_shift
5435 338748211U, // SRSRAv4i16_shift
5436 339272499U, // SRSRAv4i32_shift
5437 2487280435U, // SRSRAv8i16_shift
5438 2487804723U, // SRSRAv8i8_shift
5439 2617796033U, // SSHLLB_ZZI_D
5440 2411759041U, // SSHLLB_ZZI_H
5441 2349376961U, // SSHLLB_ZZI_S
5442 2617800383U, // SSHLLT_ZZI_D
5443 2411763391U, // SSHLLT_ZZI_H
5444 2349381311U, // SSHLLT_ZZI_S
5445 71352582U, // SSHLLv16i8_shift
5446 2217267216U, // SSHLLv2i32_shift
5447 70832144U, // SSHLLv4i16_shift
5448 69779718U, // SSHLLv4i32_shift
5449 2218311942U, // SSHLLv8i16_shift
5450 2218840080U, // SSHLLv8i8_shift
5451 68734980U, // SSHLv16i8
5452 2248683524U, // SSHLv1i64
5453 2216742916U, // SSHLv2i32
5454 2217267204U, // SSHLv2i64
5455 70307844U, // SSHLv4i16
5456 70832132U, // SSHLv4i32
5457 2218840068U, // SSHLv8i16
5458 2219364356U, // SSHLv8i8
5459 2248684467U, // SSHRd
5460 68735923U, // SSHRv16i8_shift
5461 2216743859U, // SSHRv2i32_shift
5462 2217268147U, // SSHRv2i64_shift
5463 70308787U, // SSHRv4i16_shift
5464 70833075U, // SSHRv4i32_shift
5465 2218841011U, // SSHRv8i16_shift
5466 2219365299U, // SSHRv8i8_shift
5467 705184577U, // SSRA_ZZI_B
5468 2282251073U, // SSRA_ZZI_D
5469 243303233U, // SSRA_ZZI_H
5470 2315821889U, // SSRA_ZZI_S
5471 2752111425U, // SSRAd
5472 337175361U, // SSRAv16i8_shift
5473 2485183297U, // SSRAv2i32_shift
5474 2485707585U, // SSRAv2i64_shift
5475 338748225U, // SSRAv4i16_shift
5476 339272513U, // SSRAv4i32_shift
5477 2487280449U, // SSRAv8i16_shift
5478 2487804737U, // SSRAv8i8_shift
5479 2289214403U, // SST1B_D_IMM
5480 2758976451U, // SST1B_D_REAL
5481 2758976451U, // SST1B_D_SXTW
5482 2758976451U, // SST1B_D_UXTW
5483 2322777027U, // SST1B_S_IMM
5484 2758984643U, // SST1B_S_SXTW
5485 2758984643U, // SST1B_S_UXTW
5486 2289215768U, // SST1D_IMM
5487 2758977816U, // SST1D_REAL
5488 2758977816U, // SST1D_SCALED_SCALED_REAL
5489 2758977816U, // SST1D_SXTW
5490 2758977816U, // SST1D_SXTW_SCALED
5491 2758977816U, // SST1D_UXTW
5492 2758977816U, // SST1D_UXTW_SCALED
5493 2289216347U, // SST1H_D_IMM
5494 2758978395U, // SST1H_D_REAL
5495 2758978395U, // SST1H_D_SCALED_SCALED_REAL
5496 2758978395U, // SST1H_D_SXTW
5497 2758978395U, // SST1H_D_SXTW_SCALED
5498 2758978395U, // SST1H_D_UXTW
5499 2758978395U, // SST1H_D_UXTW_SCALED
5500 2322778971U, // SST1H_S_IMM
5501 2758986587U, // SST1H_S_SXTW
5502 2758986587U, // SST1H_S_SXTW_SCALED
5503 2758986587U, // SST1H_S_UXTW
5504 2758986587U, // SST1H_S_UXTW_SCALED
5505 2289219884U, // SST1W_D_IMM
5506 2758981932U, // SST1W_D_REAL
5507 2758981932U, // SST1W_D_SCALED_SCALED_REAL
5508 2758981932U, // SST1W_D_SXTW
5509 2758981932U, // SST1W_D_SXTW_SCALED
5510 2758981932U, // SST1W_D_UXTW
5511 2758981932U, // SST1W_D_UXTW_SCALED
5512 2322782508U, // SST1W_IMM
5513 2758990124U, // SST1W_SXTW
5514 2758990124U, // SST1W_SXTW_SCALED
5515 2758990124U, // SST1W_UXTW
5516 2758990124U, // SST1W_UXTW_SCALED
5517 2617800151U, // SSUBLBT_ZZZ_D
5518 264279511U, // SSUBLBT_ZZZ_H
5519 2349381079U, // SSUBLBT_ZZZ_S
5520 2617795962U, // SSUBLB_ZZZ_D
5521 264275322U, // SSUBLB_ZZZ_H
5522 2349376890U, // SSUBLB_ZZZ_S
5523 2617796617U, // SSUBLTB_ZZZ_D
5524 264275977U, // SSUBLTB_ZZZ_H
5525 2349377545U, // SSUBLTB_ZZZ_S
5526 2617800307U, // SSUBLT_ZZZ_D
5527 264279667U, // SSUBLT_ZZZ_H
5528 2349381235U, // SSUBLT_ZZZ_S
5529 71352534U, // SSUBLv16i8_v8i16
5530 2217267070U, // SSUBLv2i32_v2i64
5531 70831998U, // SSUBLv4i16_v4i32
5532 69779670U, // SSUBLv4i32_v2i64
5533 2218311894U, // SSUBLv8i16_v4i32
5534 2218839934U, // SSUBLv8i8_v8i16
5535 2416470122U, // SSUBWB_ZZZ_D
5536 241731690U, // SSUBWB_ZZZ_H
5537 2617813098U, // SSUBWB_ZZZ_S
5538 2416474116U, // SSUBWT_ZZZ_D
5539 241735684U, // SSUBWT_ZZZ_H
5540 2617817092U, // SSUBWT_ZZZ_S
5541 2218836472U, // SSUBWv16i8_v8i16
5542 2217269598U, // SSUBWv2i32_v2i64
5543 70834526U, // SSUBWv4i16_v4i32
5544 2217263608U, // SSUBWv4i32_v2i64
5545 70828536U, // SSUBWv8i16_v4i32
5546 2218842462U, // SSUBWv8i8_v8i16
5547 2759001027U, // ST1B
5548 2758976451U, // ST1B_D
5549 2758976451U, // ST1B_D_IMM
5550 2759009219U, // ST1B_H
5551 2759009219U, // ST1B_H_IMM
5552 2759001027U, // ST1B_IMM
5553 2758984643U, // ST1B_S
5554 2758984643U, // ST1B_S_IMM
5555 2758977816U, // ST1D
5556 2758977816U, // ST1D_IMM
5557 213071U, // ST1Fourv16b
5558 17522767U, // ST1Fourv16b_POST
5559 229455U, // ST1Fourv1d
5560 18063439U, // ST1Fourv1d_POST
5561 245839U, // ST1Fourv2d
5562 17555535U, // ST1Fourv2d_POST
5563 262223U, // ST1Fourv2s
5564 18096207U, // ST1Fourv2s_POST
5565 278607U, // ST1Fourv4h
5566 18112591U, // ST1Fourv4h_POST
5567 294991U, // ST1Fourv4s
5568 17604687U, // ST1Fourv4s_POST
5569 311375U, // ST1Fourv8b
5570 18145359U, // ST1Fourv8b_POST
5571 327759U, // ST1Fourv8h
5572 17637455U, // ST1Fourv8h_POST
5573 2759011163U, // ST1H
5574 2758978395U, // ST1H_D
5575 2758978395U, // ST1H_D_IMM
5576 2759011163U, // ST1H_IMM
5577 2758986587U, // ST1H_S
5578 2758986587U, // ST1H_S_IMM
5579 213071U, // ST1Onev16b
5580 18571343U, // ST1Onev16b_POST
5581 229455U, // ST1Onev1d
5582 19112015U, // ST1Onev1d_POST
5583 245839U, // ST1Onev2d
5584 18604111U, // ST1Onev2d_POST
5585 262223U, // ST1Onev2s
5586 19144783U, // ST1Onev2s_POST
5587 278607U, // ST1Onev4h
5588 19161167U, // ST1Onev4h_POST
5589 294991U, // ST1Onev4s
5590 18653263U, // ST1Onev4s_POST
5591 311375U, // ST1Onev8b
5592 19193935U, // ST1Onev8b_POST
5593 327759U, // ST1Onev8h
5594 18686031U, // ST1Onev8h_POST
5595 213071U, // ST1Threev16b
5596 21192783U, // ST1Threev16b_POST
5597 229455U, // ST1Threev1d
5598 21733455U, // ST1Threev1d_POST
5599 245839U, // ST1Threev2d
5600 21225551U, // ST1Threev2d_POST
5601 262223U, // ST1Threev2s
5602 21766223U, // ST1Threev2s_POST
5603 278607U, // ST1Threev4h
5604 21782607U, // ST1Threev4h_POST
5605 294991U, // ST1Threev4s
5606 21274703U, // ST1Threev4s_POST
5607 311375U, // ST1Threev8b
5608 21815375U, // ST1Threev8b_POST
5609 327759U, // ST1Threev8h
5610 21307471U, // ST1Threev8h_POST
5611 213071U, // ST1Twov16b
5612 18047055U, // ST1Twov16b_POST
5613 229455U, // ST1Twov1d
5614 18587727U, // ST1Twov1d_POST
5615 245839U, // ST1Twov2d
5616 18079823U, // ST1Twov2d_POST
5617 262223U, // ST1Twov2s
5618 18620495U, // ST1Twov2s_POST
5619 278607U, // ST1Twov4h
5620 18636879U, // ST1Twov4h_POST
5621 294991U, // ST1Twov4s
5622 18128975U, // ST1Twov4s_POST
5623 311375U, // ST1Twov8b
5624 18669647U, // ST1Twov8b_POST
5625 327759U, // ST1Twov8h
5626 18161743U, // ST1Twov8h_POST
5627 2758990124U, // ST1W
5628 2758981932U, // ST1W_D
5629 2758981932U, // ST1W_D_IMM
5630 2758990124U, // ST1W_IMM
5631 458831U, // ST1i16
5632 1576353871U, // ST1i16_POST
5633 467023U, // ST1i32
5634 1609924687U, // ST1i32_POST
5635 475215U, // ST1i64
5636 1643495503U, // ST1i64_POST
5637 483407U, // ST1i8
5638 1677066319U, // ST1i8_POST
5639 2759001056U, // ST2B
5640 2759001056U, // ST2B_IMM
5641 2758977828U, // ST2D
5642 2758977828U, // ST2D_IMM
5643 2255497955U, // ST2GOffset
5644 611445475U, // ST2GPostIndex
5645 2758929123U, // ST2GPreIndex
5646 2759011192U, // ST2H
5647 2759011192U, // ST2H_IMM
5648 213491U, // ST2Twov16b
5649 18047475U, // ST2Twov16b_POST
5650 246259U, // ST2Twov2d
5651 18080243U, // ST2Twov2d_POST
5652 262643U, // ST2Twov2s
5653 18620915U, // ST2Twov2s_POST
5654 279027U, // ST2Twov4h
5655 18637299U, // ST2Twov4h_POST
5656 295411U, // ST2Twov4s
5657 18129395U, // ST2Twov4s_POST
5658 311795U, // ST2Twov8b
5659 18670067U, // ST2Twov8b_POST
5660 328179U, // ST2Twov8h
5661 18162163U, // ST2Twov8h_POST
5662 2758990144U, // ST2W
5663 2758990144U, // ST2W_IMM
5664 459251U, // ST2i16
5665 1609908723U, // ST2i16_POST
5666 467443U, // ST2i32
5667 1643479539U, // ST2i32_POST
5668 475635U, // ST2i64
5669 1710604787U, // ST2i64_POST
5670 483827U, // ST2i8
5671 1576403443U, // ST2i8_POST
5672 2759001077U, // ST3B
5673 2759001077U, // ST3B_IMM
5674 2758977840U, // ST3D
5675 2758977840U, // ST3D_IMM
5676 2759011204U, // ST3H
5677 2759011204U, // ST3H_IMM
5678 213557U, // ST3Threev16b
5679 21193269U, // ST3Threev16b_POST
5680 246325U, // ST3Threev2d
5681 21226037U, // ST3Threev2d_POST
5682 262709U, // ST3Threev2s
5683 21766709U, // ST3Threev2s_POST
5684 279093U, // ST3Threev4h
5685 21783093U, // ST3Threev4h_POST
5686 295477U, // ST3Threev4s
5687 21275189U, // ST3Threev4s_POST
5688 311861U, // ST3Threev8b
5689 21815861U, // ST3Threev8b_POST
5690 328245U, // ST3Threev8h
5691 21307957U, // ST3Threev8h_POST
5692 2758990156U, // ST3W
5693 2758990156U, // ST3W_IMM
5694 459317U, // ST3i16
5695 1744126517U, // ST3i16_POST
5696 467509U, // ST3i32
5697 1777697333U, // ST3i32_POST
5698 475701U, // ST3i64
5699 1811268149U, // ST3i64_POST
5700 483893U, // ST3i8
5701 1844838965U, // ST3i8_POST
5702 2759001103U, // ST4B
5703 2759001103U, // ST4B_IMM
5704 2758977852U, // ST4D
5705 2758977852U, // ST4D_IMM
5706 213574U, // ST4Fourv16b
5707 17523270U, // ST4Fourv16b_POST
5708 246342U, // ST4Fourv2d
5709 17556038U, // ST4Fourv2d_POST
5710 262726U, // ST4Fourv2s
5711 18096710U, // ST4Fourv2s_POST
5712 279110U, // ST4Fourv4h
5713 18113094U, // ST4Fourv4h_POST
5714 295494U, // ST4Fourv4s
5715 17605190U, // ST4Fourv4s_POST
5716 311878U, // ST4Fourv8b
5717 18145862U, // ST4Fourv8b_POST
5718 328262U, // ST4Fourv8h
5719 17637958U, // ST4Fourv8h_POST
5720 2759011216U, // ST4H
5721 2759011216U, // ST4H_IMM
5722 2758990168U, // ST4W
5723 2758990168U, // ST4W_IMM
5724 459334U, // ST4i16
5725 1643463238U, // ST4i16_POST
5726 467526U, // ST4i32
5727 1710588486U, // ST4i32_POST
5728 475718U, // ST4i64
5729 1878377030U, // ST4i64_POST
5730 483910U, // ST4i8
5731 1609957958U, // ST4i8_POST
5732 410626U, // ST64B
5733 1879586913U, // ST64BV
5734 1879580704U, // ST64BV0
5735 2255499530U, // STGM
5736 2255498019U, // STGOffset
5737 101200480U, // STGPi
5738 611445539U, // STGPostIndex
5739 604631648U, // STGPpost
5740 604631648U, // STGPpre
5741 2758929187U, // STGPreIndex
5742 2255496996U, // STLLRB
5743 2255498616U, // STLLRH
5744 2255500285U, // STLLRW
5745 2255500285U, // STLLRX
5746 2255497004U, // STLRB
5747 2255498624U, // STLRH
5748 2255500298U, // STLRW
5749 2255500298U, // STLRX
5750 2255497054U, // STLURBi
5751 2255498674U, // STLURHi
5752 2255500395U, // STLURWi
5753 2255500395U, // STLURXi
5754 2248684312U, // STLXPW
5755 2248684312U, // STLXPX
5756 101197701U, // STLXRB
5757 101199321U, // STLXRH
5758 101201067U, // STLXRW
5759 101201067U, // STLXRX
5760 101200576U, // STNPDi
5761 101200576U, // STNPQi
5762 101200576U, // STNPSi
5763 101200576U, // STNPWi
5764 101200576U, // STNPXi
5765 2759001019U, // STNT1B_ZRI
5766 2759001019U, // STNT1B_ZRR
5767 2289214395U, // STNT1B_ZZR_D_REAL
5768 2322777019U, // STNT1B_ZZR_S_REAL
5769 2758977808U, // STNT1D_ZRI
5770 2758977808U, // STNT1D_ZRR
5771 2289215760U, // STNT1D_ZZR_D_REAL
5772 2759011155U, // STNT1H_ZRI
5773 2759011155U, // STNT1H_ZRR
5774 2289216339U, // STNT1H_ZZR_D_REAL
5775 2322778963U, // STNT1H_ZZR_S_REAL
5776 2758990116U, // STNT1W_ZRI
5777 2758990116U, // STNT1W_ZRR
5778 2289219876U, // STNT1W_ZZR_D_REAL
5779 2322782500U, // STNT1W_ZZR_S_REAL
5780 101200614U, // STPDi
5781 604631782U, // STPDpost
5782 604631782U, // STPDpre
5783 101200614U, // STPQi
5784 604631782U, // STPQpost
5785 604631782U, // STPQpre
5786 101200614U, // STPSi
5787 604631782U, // STPSpost
5788 604631782U, // STPSpre
5789 101200614U, // STPWi
5790 604631782U, // STPWpost
5791 604631782U, // STPWpre
5792 101200614U, // STPXi
5793 604631782U, // STPXpost
5794 604631782U, // STPXpre
5795 611444554U, // STRBBpost
5796 2758928202U, // STRBBpre
5797 2255497034U, // STRBBroW
5798 2255497034U, // STRBBroX
5799 2255497034U, // STRBBui
5800 611447892U, // STRBpost
5801 2758931540U, // STRBpre
5802 2255500372U, // STRBroW
5803 2255500372U, // STRBroX
5804 2255500372U, // STRBui
5805 611447892U, // STRDpost
5806 2758931540U, // STRDpre
5807 2255500372U, // STRDroW
5808 2255500372U, // STRDroX
5809 2255500372U, // STRDui
5810 611446174U, // STRHHpost
5811 2758929822U, // STRHHpre
5812 2255498654U, // STRHHroW
5813 2255498654U, // STRHHroX
5814 2255498654U, // STRHHui
5815 611447892U, // STRHpost
5816 2758931540U, // STRHpre
5817 2255500372U, // STRHroW
5818 2255500372U, // STRHroX
5819 2255500372U, // STRHui
5820 611447892U, // STRQpost
5821 2758931540U, // STRQpre
5822 2255500372U, // STRQroW
5823 2255500372U, // STRQroX
5824 2255500372U, // STRQui
5825 611447892U, // STRSpost
5826 2758931540U, // STRSpre
5827 2255500372U, // STRSroW
5828 2255500372U, // STRSroX
5829 2255500372U, // STRSui
5830 611447892U, // STRWpost
5831 2758931540U, // STRWpre
5832 2255500372U, // STRWroW
5833 2255500372U, // STRWroX
5834 2255500372U, // STRWui
5835 611447892U, // STRXpost
5836 2758931540U, // STRXpre
5837 2255500372U, // STRXroW
5838 2255500372U, // STRXroX
5839 2255500372U, // STRXui
5840 2255909972U, // STR_PXI
5841 2255909972U, // STR_ZXI
5842 2255497040U, // STTRBi
5843 2255498660U, // STTRHi
5844 2255500377U, // STTRWi
5845 2255500377U, // STTRXi
5846 2255497071U, // STURBBi
5847 2255500410U, // STURBi
5848 2255500410U, // STURDi
5849 2255498691U, // STURHHi
5850 2255500410U, // STURHi
5851 2255500410U, // STURQi
5852 2255500410U, // STURSi
5853 2255500410U, // STURWi
5854 2255500410U, // STURXi
5855 2248684319U, // STXPW
5856 2248684319U, // STXPX
5857 101197709U, // STXRB
5858 101199329U, // STXRH
5859 101201074U, // STXRW
5860 101201074U, // STXRX
5861 2255497961U, // STZ2GOffset
5862 611445481U, // STZ2GPostIndex
5863 2758929129U, // STZ2GPreIndex
5864 2255499536U, // STZGM
5865 2255498024U, // STZGOffset
5866 611445544U, // STZGPostIndex
5867 2758929192U, // STZGPreIndex
5868 2248682224U, // SUBG
5869 2349352556U, // SUBHNB_ZZZ_B
5870 240158316U, // SUBHNB_ZZZ_H
5871 2416485996U, // SUBHNB_ZZZ_S
5872 2450020147U, // SUBHNT_ZZZ_B
5873 240686899U, // SUBHNT_ZZZ_H
5874 2282272563U, // SUBHNT_ZZZ_S
5875 2216743243U, // SUBHNv2i64_v2i32
5876 2486755683U, // SUBHNv2i64_v4i32
5877 70308171U, // SUBHNv4i32_v4i16
5878 339796323U, // SUBHNv4i32_v8i16
5879 2484658531U, // SUBHNv8i16_v16i8
5880 2219364683U, // SUBHNv8i16_v8i8
5881 2248684072U, // SUBP
5882 2248684919U, // SUBPS
5883 2584236903U, // SUBR_ZI_B
5884 2416472935U, // SUBR_ZI_D
5885 241734503U, // SUBR_ZI_H
5886 2617815911U, // SUBR_ZI_S
5887 369644391U, // SUBR_ZPmZ_B
5888 369652583U, // SUBR_ZPmZ_D
5889 2556466023U, // SUBR_ZPmZ_H
5890 369668967U, // SUBR_ZPmZ_S
5891 2248684784U, // SUBSWri
5892 2248684784U, // SUBSWrs
5893 2248684784U, // SUBSWrx
5894 2248684784U, // SUBSXri
5895 2248684784U, // SUBSXrs
5896 2248684784U, // SUBSXrx
5897 2248684784U, // SUBSXrx64
5898 2248681524U, // SUBWri
5899 2248681524U, // SUBWrs
5900 2248681524U, // SUBWrx
5901 2248681524U, // SUBXri
5902 2248681524U, // SUBXrs
5903 2248681524U, // SUBXrx
5904 2248681524U, // SUBXrx64
5905 2584234036U, // SUB_ZI_B
5906 2416470068U, // SUB_ZI_D
5907 241731636U, // SUB_ZI_H
5908 2617813044U, // SUB_ZI_S
5909 369641524U, // SUB_ZPmZ_B
5910 369649716U, // SUB_ZPmZ_D
5911 2556463156U, // SUB_ZPmZ_H
5912 369666100U, // SUB_ZPmZ_S
5913 2584234036U, // SUB_ZZZ_B
5914 2416470068U, // SUB_ZZZ_D
5915 2389215284U, // SUB_ZZZ_H
5916 2617813044U, // SUB_ZZZ_S
5917 68732980U, // SUBv16i8
5918 2248681524U, // SUBv1i64
5919 2216740916U, // SUBv2i32
5920 2217265204U, // SUBv2i64
5921 70305844U, // SUBv4i16
5922 70830132U, // SUBv4i32
5923 2218838068U, // SUBv8i16
5924 2219362356U, // SUBv8i8
5925 705214404U, // SUDOT_ZZZI
5926 339277764U, // SUDOTlanev16i8
5927 2485188548U, // SUDOTlanev8i8
5928 470314638U, // SUNPKHI_ZZ_D
5929 566267534U, // SUNPKHI_ZZ_H
5930 201895566U, // SUNPKHI_ZZ_S
5931 470315521U, // SUNPKLO_ZZ_D
5932 566268417U, // SUNPKLO_ZZ_H
5933 201896449U, // SUNPKLO_ZZ_S
5934 369641952U, // SUQADD_ZPmZ_B
5935 369650144U, // SUQADD_ZPmZ_D
5936 2556463584U, // SUQADD_ZPmZ_H
5937 369666528U, // SUQADD_ZPmZ_S
5938 2484660704U, // SUQADDv16i8
5939 604629472U, // SUQADDv1i16
5940 604629472U, // SUQADDv1i32
5941 604629472U, // SUQADDv1i64
5942 604629472U, // SUQADDv1i8
5943 2485184992U, // SUQADDv2i32
5944 338225632U, // SUQADDv2i64
5945 2486233568U, // SUQADDv4i16
5946 339274208U, // SUQADDv4i32
5947 2487282144U, // SUQADDv8i16
5948 340322784U, // SUQADDv8i8
5949 108781U, // SVC
5950 1309271090U, // SWPAB
5951 1309273041U, // SWPAH
5952 1309271350U, // SWPALB
5953 1309273197U, // SWPALH
5954 1309273900U, // SWPALW
5955 1309273900U, // SWPALX
5956 1309270806U, // SWPAW
5957 1309270806U, // SWPAX
5958 1309271794U, // SWPB
5959 1309273414U, // SWPH
5960 1309271559U, // SWPLB
5961 1309273294U, // SWPLH
5962 1309274204U, // SWPLW
5963 1309274204U, // SWPLX
5964 1309274865U, // SWPW
5965 1309274865U, // SWPX
5966 2148034599U, // SXTB_ZPmZ_D
5967 34637863U, // SXTB_ZPmZ_H
5968 567335U, // SXTB_ZPmZ_S
5969 2148036177U, // SXTH_ZPmZ_D
5970 568913U, // SXTH_ZPmZ_S
5971 2148039201U, // SXTW_ZPmZ_D
5972 2248683676U, // SYSLxt
5973 1913140662U, // SYSxt
5974 1074286441U, // TBL_ZZZZ_B
5975 1946709865U, // TBL_ZZZZ_D
5976 33066857U, // TBL_ZZZZ_H
5977 1980280681U, // TBL_ZZZZ_S
5978 1074286441U, // TBL_ZZZ_B
5979 1946709865U, // TBL_ZZZ_D
5980 33066857U, // TBL_ZZZ_H
5981 1980280681U, // TBL_ZZZ_S
5982 4162375529U, // TBLv16i8Four
5983 4162375529U, // TBLv16i8One
5984 4162375529U, // TBLv16i8Three
5985 4162375529U, // TBLv16i8Two
5986 2018037609U, // TBLv8i8Four
5987 2018037609U, // TBLv8i8One
5988 2018037609U, // TBLv8i8Three
5989 2018037609U, // TBLv8i8Two
5990 2248686340U, // TBNZW
5991 2248686340U, // TBNZX
5992 705190507U, // TBX_ZZZ_B
5993 2282257003U, // TBX_ZZZ_D
5994 2390792811U, // TBX_ZZZ_H
5995 2315827819U, // TBX_ZZZ_S
5996 4195940971U, // TBXv16i8Four
5997 4195940971U, // TBXv16i8One
5998 4195940971U, // TBXv16i8Three
5999 4195940971U, // TBXv16i8Two
6000 2051603051U, // TBXv8i8Four
6001 2051603051U, // TBXv8i8One
6002 2051603051U, // TBXv8i8Three
6003 2051603051U, // TBXv8i8Two
6004 2248686324U, // TBZW
6005 2248686324U, // TBZX
6006 110528U, // TCANCEL
6007 7377U, // TCOMMIT
6008 2584231982U, // TRN1_PPP_B
6009 2416468014U, // TRN1_PPP_D
6010 2389213230U, // TRN1_PPP_H
6011 2617810990U, // TRN1_PPP_S
6012 2584231982U, // TRN1_ZZZ_B
6013 2416468014U, // TRN1_ZZZ_D
6014 2389213230U, // TRN1_ZZZ_H
6015 245530670U, // TRN1_ZZZ_Q
6016 2617810990U, // TRN1_ZZZ_S
6017 68730926U, // TRN1v16i8
6018 2216738862U, // TRN1v2i32
6019 2217263150U, // TRN1v2i64
6020 70303790U, // TRN1v4i16
6021 70828078U, // TRN1v4i32
6022 2218836014U, // TRN1v8i16
6023 2219360302U, // TRN1v8i8
6024 2584232346U, // TRN2_PPP_B
6025 2416468378U, // TRN2_PPP_D
6026 2389213594U, // TRN2_PPP_H
6027 2617811354U, // TRN2_PPP_S
6028 2584232346U, // TRN2_ZZZ_B
6029 2416468378U, // TRN2_ZZZ_D
6030 2389213594U, // TRN2_ZZZ_H
6031 245531034U, // TRN2_ZZZ_Q
6032 2617811354U, // TRN2_ZZZ_S
6033 68731290U, // TRN2v16i8
6034 2216739226U, // TRN2v2i32
6035 2217263514U, // TRN2v2i64
6036 70304154U, // TRN2v4i16
6037 70828442U, // TRN2v4i32
6038 2218836378U, // TRN2v8i16
6039 2219360666U, // TRN2v8i8
6040 149500U, // TSB
6041 14289U, // TSTART
6042 14311U, // TTEST
6043 2315805931U, // UABALB_ZZZ_D
6044 266372331U, // UABALB_ZZZ_H
6045 2450040043U, // UABALB_ZZZ_S
6046 2315810376U, // UABALT_ZZZ_D
6047 266376776U, // UABALT_ZZZ_H
6048 2450044488U, // UABALT_ZZZ_S
6049 339796140U, // UABALv16i8_v8i16
6050 2485710562U, // UABALv2i32_v2i64
6051 339275490U, // UABALv4i16_v4i32
6052 338223276U, // UABALv4i32_v2i64
6053 2486755500U, // UABALv8i16_v4i32
6054 2487283426U, // UABALv8i8_v8i16
6055 705184397U, // UABA_ZZZ_B
6056 2282250893U, // UABA_ZZZ_D
6057 2390786701U, // UABA_ZZZ_H
6058 2315821709U, // UABA_ZZZ_S
6059 337175181U, // UABAv16i8
6060 2485183117U, // UABAv2i32
6061 338748045U, // UABAv4i16
6062 339272333U, // UABAv4i32
6063 2487280269U, // UABAv8i16
6064 2487804557U, // UABAv8i8
6065 2617796000U, // UABDLB_ZZZ_D
6066 264275360U, // UABDLB_ZZZ_H
6067 2349376928U, // UABDLB_ZZZ_S
6068 2617800345U, // UABDLT_ZZZ_D
6069 264279705U, // UABDLT_ZZZ_H
6070 2349381273U, // UABDLT_ZZZ_S
6071 71352558U, // UABDLv16i8_v8i16
6072 2217267091U, // UABDLv2i32_v2i64
6073 70832019U, // UABDLv4i16_v4i32
6074 69779694U, // UABDLv4i32_v2i64
6075 2218311918U, // UABDLv8i16_v4i32
6076 2218839955U, // UABDLv8i8_v8i16
6077 369641826U, // UABD_ZPmZ_B
6078 369650018U, // UABD_ZPmZ_D
6079 2556463458U, // UABD_ZPmZ_H
6080 369666402U, // UABD_ZPmZ_S
6081 68733282U, // UABDv16i8
6082 2216741218U, // UABDv2i32
6083 70306146U, // UABDv4i16
6084 70830434U, // UABDv4i32
6085 2218838370U, // UABDv8i16
6086 2219362658U, // UABDv8i8
6087 369652334U, // UADALP_ZPmZ_D
6088 408982126U, // UADALP_ZPmZ_H
6089 369668718U, // UADALP_ZPmZ_S
6090 2487284334U, // UADALPv16i8_v8i16
6091 2515071598U, // UADALPv2i32_v1i64
6092 2485187182U, // UADALPv4i16_v2i32
6093 338227822U, // UADALPv4i32_v2i64
6094 2486760046U, // UADALPv8i16_v4i32
6095 338752110U, // UADALPv8i8_v4i16
6096 2617796025U, // UADDLB_ZZZ_D
6097 264275385U, // UADDLB_ZZZ_H
6098 2349376953U, // UADDLB_ZZZ_S
6099 2218840702U, // UADDLPv16i8_v8i16
6100 2246627966U, // UADDLPv2i32_v1i64
6101 2216743550U, // UADDLPv4i16_v2i32
6102 69784190U, // UADDLPv4i32_v2i64
6103 2218316414U, // UADDLPv8i16_v4i32
6104 70308478U, // UADDLPv8i8_v4i16
6105 2617800361U, // UADDLT_ZZZ_D
6106 264279721U, // UADDLT_ZZZ_H
6107 2349381289U, // UADDLT_ZZZ_S
6108 2215131299U, // UADDLVv16i8v
6109 2215131299U, // UADDLVv4i16v
6110 67647651U, // UADDLVv4i32v
6111 2215131299U, // UADDLVv8i16v
6112 67647651U, // UADDLVv8i8v
6113 71352574U, // UADDLv16i8_v8i16
6114 2217267129U, // UADDLv2i32_v2i64
6115 70832057U, // UADDLv4i16_v4i32
6116 69779710U, // UADDLv4i32_v2i64
6117 2218311934U, // UADDLv8i16_v4i32
6118 2218839993U, // UADDLv8i8_v8i16
6119 568408183U, // UADDV_VPZ_B
6120 544815223U, // UADDV_VPZ_D
6121 545339511U, // UADDV_VPZ_H
6122 542718071U, // UADDV_VPZ_S
6123 2416470146U, // UADDWB_ZZZ_D
6124 241731714U, // UADDWB_ZZZ_H
6125 2617813122U, // UADDWB_ZZZ_S
6126 2416474140U, // UADDWT_ZZZ_D
6127 241735708U, // UADDWT_ZZZ_H
6128 2617817116U, // UADDWT_ZZZ_S
6129 2218836496U, // UADDWv16i8_v8i16
6130 2217269660U, // UADDWv2i32_v2i64
6131 70834588U, // UADDWv4i16_v4i32
6132 2217263632U, // UADDWv4i32_v2i64
6133 70828560U, // UADDWv8i16_v4i32
6134 2218842524U, // UADDWv8i8_v8i16
6135 2248683768U, // UBFMWri
6136 2248683768U, // UBFMXri
6137 2248682204U, // UCVTFSWDri
6138 2248682204U, // UCVTFSWHri
6139 2248682204U, // UCVTFSWSri
6140 2248682204U, // UCVTFSXDri
6141 2248682204U, // UCVTFSXHri
6142 2248682204U, // UCVTFSXSri
6143 101198556U, // UCVTFUWDri
6144 101198556U, // UCVTFUWHri
6145 101198556U, // UCVTFUWSri
6146 101198556U, // UCVTFUXDri
6147 101198556U, // UCVTFUXHri
6148 101198556U, // UCVTFUXSri
6149 2148035292U, // UCVTF_ZPmZ_DtoD
6150 1141934812U, // UCVTF_ZPmZ_DtoH
6151 2148051676U, // UCVTF_ZPmZ_DtoS
6152 34638556U, // UCVTF_ZPmZ_HtoH
6153 551644U, // UCVTF_ZPmZ_StoD
6154 571509468U, // UCVTF_ZPmZ_StoH
6155 568028U, // UCVTF_ZPmZ_StoS
6156 2248682204U, // UCVTFd
6157 2248682204U, // UCVTFh
6158 2248682204U, // UCVTFs
6159 101198556U, // UCVTFv1i16
6160 101198556U, // UCVTFv1i32
6161 101198556U, // UCVTFv1i64
6162 2216741596U, // UCVTFv2f32
6163 69782236U, // UCVTFv2f64
6164 2216741596U, // UCVTFv2i32_shift
6165 2217265884U, // UCVTFv2i64_shift
6166 2217790172U, // UCVTFv4f16
6167 70830812U, // UCVTFv4f32
6168 70306524U, // UCVTFv4i16_shift
6169 70830812U, // UCVTFv4i32_shift
6170 2218838748U, // UCVTFv8f16
6171 2218838748U, // UCVTFv8i16_shift
6172 10949U, // UDF
6173 369652878U, // UDIVR_ZPmZ_D
6174 369669262U, // UDIVR_ZPmZ_S
6175 2248685717U, // UDIVWr
6176 2248685717U, // UDIVXr
6177 369653909U, // UDIV_ZPmZ_D
6178 369670293U, // UDIV_ZPmZ_S
6179 2450028485U, // UDOT_ZZZI_D
6180 705214405U, // UDOT_ZZZI_S
6181 2450028485U, // UDOT_ZZZ_D
6182 705214405U, // UDOT_ZZZ_S
6183 339277765U, // UDOTlanev16i8
6184 2485188549U, // UDOTlanev8i8
6185 339277765U, // UDOTv16i8
6186 2485188549U, // UDOTv8i8
6187 369641922U, // UHADD_ZPmZ_B
6188 369650114U, // UHADD_ZPmZ_D
6189 2556463554U, // UHADD_ZPmZ_H
6190 369666498U, // UHADD_ZPmZ_S
6191 68733378U, // UHADDv16i8
6192 2216741314U, // UHADDv2i32
6193 70306242U, // UHADDv4i16
6194 70830530U, // UHADDv4i32
6195 2218838466U, // UHADDv8i16
6196 2219362754U, // UHADDv8i8
6197 369644405U, // UHSUBR_ZPmZ_B
6198 369652597U, // UHSUBR_ZPmZ_D
6199 2556466037U, // UHSUBR_ZPmZ_H
6200 369668981U, // UHSUBR_ZPmZ_S
6201 369641536U, // UHSUB_ZPmZ_B
6202 369649728U, // UHSUB_ZPmZ_D
6203 2556463168U, // UHSUB_ZPmZ_H
6204 369666112U, // UHSUB_ZPmZ_S
6205 68732992U, // UHSUBv16i8
6206 2216740928U, // UHSUBv2i32
6207 70305856U, // UHSUBv4i16
6208 70830144U, // UHSUBv4i32
6209 2218838080U, // UHSUBv8i16
6210 2219362368U, // UHSUBv8i8
6211 2248683434U, // UMADDLrrr
6212 369644299U, // UMAXP_ZPmZ_B
6213 369652491U, // UMAXP_ZPmZ_D
6214 2556465931U, // UMAXP_ZPmZ_H
6215 369668875U, // UMAXP_ZPmZ_S
6216 68735755U, // UMAXPv16i8
6217 2216743691U, // UMAXPv2i32
6218 70308619U, // UMAXPv4i16
6219 70832907U, // UMAXPv4i32
6220 2218840843U, // UMAXPv8i16
6221 2219365131U, // UMAXPv8i8
6222 71935U, // UMAXV_VPZ_B
6223 544815359U, // UMAXV_VPZ_D
6224 545347839U, // UMAXV_VPZ_H
6225 542734591U, // UMAXV_VPZ_S
6226 2215131391U, // UMAXVv16i8v
6227 2215131391U, // UMAXVv4i16v
6228 67647743U, // UMAXVv4i32v
6229 2215131391U, // UMAXVv8i16v
6230 67647743U, // UMAXVv8i8v
6231 2584238693U, // UMAX_ZI_B
6232 2416474725U, // UMAX_ZI_D
6233 2389219941U, // UMAX_ZI_H
6234 2617817701U, // UMAX_ZI_S
6235 369646181U, // UMAX_ZPmZ_B
6236 369654373U, // UMAX_ZPmZ_D
6237 2556467813U, // UMAX_ZPmZ_H
6238 369670757U, // UMAX_ZPmZ_S
6239 68737637U, // UMAXv16i8
6240 2216745573U, // UMAXv2i32
6241 70310501U, // UMAXv4i16
6242 70834789U, // UMAXv4i32
6243 2218842725U, // UMAXv8i16
6244 2219367013U, // UMAXv8i8
6245 369644217U, // UMINP_ZPmZ_B
6246 369652409U, // UMINP_ZPmZ_D
6247 2556465849U, // UMINP_ZPmZ_H
6248 369668793U, // UMINP_ZPmZ_S
6249 68735673U, // UMINPv16i8
6250 2216743609U, // UMINPv2i32
6251 70308537U, // UMINPv4i16
6252 70832825U, // UMINPv4i32
6253 2218840761U, // UMINPv8i16
6254 2219365049U, // UMINPv8i8
6255 71883U, // UMINV_VPZ_B
6256 544815307U, // UMINV_VPZ_D
6257 545347787U, // UMINV_VPZ_H
6258 542734539U, // UMINV_VPZ_S
6259 2215131339U, // UMINVv16i8v
6260 2215131339U, // UMINVv4i16v
6261 67647691U, // UMINVv4i32v
6262 2215131339U, // UMINVv8i16v
6263 67647691U, // UMINVv8i8v
6264 2584236394U, // UMIN_ZI_B
6265 2416472426U, // UMIN_ZI_D
6266 2389217642U, // UMIN_ZI_H
6267 2617815402U, // UMIN_ZI_S
6268 369643882U, // UMIN_ZPmZ_B
6269 369652074U, // UMIN_ZPmZ_D
6270 2556465514U, // UMIN_ZPmZ_H
6271 369668458U, // UMIN_ZPmZ_S
6272 68735338U, // UMINv16i8
6273 2216743274U, // UMINv2i32
6274 70308202U, // UMINv4i16
6275 70832490U, // UMINv4i32
6276 2218840426U, // UMINv8i16
6277 2219364714U, // UMINv8i8
6278 2315805976U, // UMLALB_ZZZI_D
6279 2450040088U, // UMLALB_ZZZI_S
6280 2315805976U, // UMLALB_ZZZ_D
6281 266372376U, // UMLALB_ZZZ_H
6282 2450040088U, // UMLALB_ZZZ_S
6283 2315810411U, // UMLALT_ZZZI_D
6284 2450044523U, // UMLALT_ZZZI_S
6285 2315810411U, // UMLALT_ZZZ_D
6286 266376811U, // UMLALT_ZZZ_H
6287 2450044523U, // UMLALT_ZZZ_S
6288 339796174U, // UMLALv16i8_v8i16
6289 2485710601U, // UMLALv2i32_indexed
6290 2485710601U, // UMLALv2i32_v2i64
6291 339275529U, // UMLALv4i16_indexed
6292 339275529U, // UMLALv4i16_v4i32
6293 338223310U, // UMLALv4i32_indexed
6294 338223310U, // UMLALv4i32_v2i64
6295 2486755534U, // UMLALv8i16_indexed
6296 2486755534U, // UMLALv8i16_v4i32
6297 2487283465U, // UMLALv8i8_v8i16
6298 2315806273U, // UMLSLB_ZZZI_D
6299 2450040385U, // UMLSLB_ZZZI_S
6300 2315806273U, // UMLSLB_ZZZ_D
6301 266372673U, // UMLSLB_ZZZ_H
6302 2450040385U, // UMLSLB_ZZZ_S
6303 2315810585U, // UMLSLT_ZZZI_D
6304 2450044697U, // UMLSLT_ZZZI_S
6305 2315810585U, // UMLSLT_ZZZ_D
6306 266376985U, // UMLSLT_ZZZ_H
6307 2450044697U, // UMLSLT_ZZZ_S
6308 339796306U, // UMLSLv16i8_v8i16
6309 2485710997U, // UMLSLv2i32_indexed
6310 2485710997U, // UMLSLv2i32_v2i64
6311 339275925U, // UMLSLv4i16_indexed
6312 339275925U, // UMLSLv4i16_v4i32
6313 338223442U, // UMLSLv4i32_indexed
6314 338223442U, // UMLSLv4i32_v2i64
6315 2486755666U, // UMLSLv8i16_indexed
6316 2486755666U, // UMLSLv8i16_v4i32
6317 2487283861U, // UMLSLv8i8_v8i16
6318 339272424U, // UMMLA
6319 705209064U, // UMMLA_ZZZ
6320 67647717U, // UMOVvi16
6321 2215131365U, // UMOVvi32
6322 67647717U, // UMOVvi64
6323 2215131365U, // UMOVvi8
6324 2248683382U, // UMSUBLrrr
6325 369642769U, // UMULH_ZPmZ_B
6326 369650961U, // UMULH_ZPmZ_D
6327 2556464401U, // UMULH_ZPmZ_H
6328 369667345U, // UMULH_ZPmZ_S
6329 2584235281U, // UMULH_ZZZ_B
6330 2416471313U, // UMULH_ZZZ_D
6331 2389216529U, // UMULH_ZZZ_H
6332 2617814289U, // UMULH_ZZZ_S
6333 2248682769U, // UMULHrr
6334 2617796075U, // UMULLB_ZZZI_D
6335 2349377003U, // UMULLB_ZZZI_S
6336 2617796075U, // UMULLB_ZZZ_D
6337 264275435U, // UMULLB_ZZZ_H
6338 2349377003U, // UMULLB_ZZZ_S
6339 2617800425U, // UMULLT_ZZZI_D
6340 2349381353U, // UMULLT_ZZZI_S
6341 2617800425U, // UMULLT_ZZZ_D
6342 264279785U, // UMULLT_ZZZ_H
6343 2349381353U, // UMULLT_ZZZ_S
6344 71352624U, // UMULLv16i8_v8i16
6345 2217267253U, // UMULLv2i32_indexed
6346 2217267253U, // UMULLv2i32_v2i64
6347 70832181U, // UMULLv4i16_indexed
6348 70832181U, // UMULLv4i16_v4i32
6349 69779760U, // UMULLv4i32_indexed
6350 69779760U, // UMULLv4i32_v2i64
6351 2218311984U, // UMULLv8i16_indexed
6352 2218311984U, // UMULLv8i16_v4i32
6353 2218840117U, // UMULLv8i8_v8i16
6354 2584234465U, // UQADD_ZI_B
6355 2416470497U, // UQADD_ZI_D
6356 241732065U, // UQADD_ZI_H
6357 2617813473U, // UQADD_ZI_S
6358 369641953U, // UQADD_ZPmZ_B
6359 369650145U, // UQADD_ZPmZ_D
6360 2556463585U, // UQADD_ZPmZ_H
6361 369666529U, // UQADD_ZPmZ_S
6362 2584234465U, // UQADD_ZZZ_B
6363 2416470497U, // UQADD_ZZZ_D
6364 2389215713U, // UQADD_ZZZ_H
6365 2617813473U, // UQADD_ZZZ_S
6366 68733409U, // UQADDv16i8
6367 2248681953U, // UQADDv1i16
6368 2248681953U, // UQADDv1i32
6369 2248681953U, // UQADDv1i64
6370 2248681953U, // UQADDv1i8
6371 2216741345U, // UQADDv2i32
6372 2217265633U, // UQADDv2i64
6373 70306273U, // UQADDv4i16
6374 70830561U, // UQADDv4i32
6375 2218838497U, // UQADDv8i16
6376 2219362785U, // UQADDv8i8
6377 872948884U, // UQDECB_WPiI
6378 872948884U, // UQDECB_XPiI
6379 872950135U, // UQDECD_WPiI
6380 872950135U, // UQDECD_XPiI
6381 872966519U, // UQDECD_ZPiI
6382 872950815U, // UQDECH_WPiI
6383 872950815U, // UQDECH_XPiI
6384 8948767U, // UQDECH_ZPiI
6385 436744758U, // UQDECP_WP_B
6386 268972598U, // UQDECP_WP_D
6387 201863734U, // UQDECP_WP_H
6388 470299190U, // UQDECP_WP_S
6389 436744758U, // UQDECP_XP_B
6390 268972598U, // UQDECP_XP_D
6391 201863734U, // UQDECP_XP_H
6392 470299190U, // UQDECP_XP_S
6393 134771254U, // UQDECP_ZP_D
6394 545296950U, // UQDECP_ZP_H
6395 168342070U, // UQDECP_ZP_S
6396 872954237U, // UQDECW_WPiI
6397 872954237U, // UQDECW_XPiI
6398 872987005U, // UQDECW_ZPiI
6399 872948900U, // UQINCB_WPiI
6400 872948900U, // UQINCB_XPiI
6401 872950151U, // UQINCD_WPiI
6402 872950151U, // UQINCD_XPiI
6403 872966535U, // UQINCD_ZPiI
6404 872950831U, // UQINCH_WPiI
6405 872950831U, // UQINCH_XPiI
6406 8948783U, // UQINCH_ZPiI
6407 436744774U, // UQINCP_WP_B
6408 268972614U, // UQINCP_WP_D
6409 201863750U, // UQINCP_WP_H
6410 470299206U, // UQINCP_WP_S
6411 436744774U, // UQINCP_XP_B
6412 268972614U, // UQINCP_XP_D
6413 201863750U, // UQINCP_XP_H
6414 470299206U, // UQINCP_XP_S
6415 134771270U, // UQINCP_ZP_D
6416 545296966U, // UQINCP_ZP_H
6417 168342086U, // UQINCP_ZP_S
6418 872954253U, // UQINCW_WPiI
6419 872954253U, // UQINCW_XPiI
6420 872987021U, // UQINCW_ZPiI
6421 369644516U, // UQRSHLR_ZPmZ_B
6422 369652708U, // UQRSHLR_ZPmZ_D
6423 2556466148U, // UQRSHLR_ZPmZ_H
6424 369669092U, // UQRSHLR_ZPmZ_S
6425 369643502U, // UQRSHL_ZPmZ_B
6426 369651694U, // UQRSHL_ZPmZ_D
6427 2556465134U, // UQRSHL_ZPmZ_H
6428 369668078U, // UQRSHL_ZPmZ_S
6429 68734958U, // UQRSHLv16i8
6430 2248683502U, // UQRSHLv1i16
6431 2248683502U, // UQRSHLv1i32
6432 2248683502U, // UQRSHLv1i64
6433 2248683502U, // UQRSHLv1i8
6434 2216742894U, // UQRSHLv2i32
6435 2217267182U, // UQRSHLv2i64
6436 70307822U, // UQRSHLv4i16
6437 70832110U, // UQRSHLv4i32
6438 2218840046U, // UQRSHLv8i16
6439 2219364334U, // UQRSHLv8i8
6440 2349352619U, // UQRSHRNB_ZZI_B
6441 2387642027U, // UQRSHRNB_ZZI_H
6442 2416486059U, // UQRSHRNB_ZZI_S
6443 2450020198U, // UQRSHRNT_ZZI_B
6444 240686950U, // UQRSHRNT_ZZI_H
6445 2282272614U, // UQRSHRNT_ZZI_S
6446 2248683930U, // UQRSHRNb
6447 2248683930U, // UQRSHRNh
6448 2248683930U, // UQRSHRNs
6449 2484658576U, // UQRSHRNv16i8_shift
6450 2216743322U, // UQRSHRNv2i32_shift
6451 70308250U, // UQRSHRNv4i16_shift
6452 2486755728U, // UQRSHRNv4i32_shift
6453 339796368U, // UQRSHRNv8i16_shift
6454 2219364762U, // UQRSHRNv8i8_shift
6455 369644499U, // UQSHLR_ZPmZ_B
6456 369652691U, // UQSHLR_ZPmZ_D
6457 2556466131U, // UQSHLR_ZPmZ_H
6458 369669075U, // UQSHLR_ZPmZ_S
6459 369643487U, // UQSHL_ZPmI_B
6460 369651679U, // UQSHL_ZPmI_D
6461 2556465119U, // UQSHL_ZPmI_H
6462 369668063U, // UQSHL_ZPmI_S
6463 369643487U, // UQSHL_ZPmZ_B
6464 369651679U, // UQSHL_ZPmZ_D
6465 2556465119U, // UQSHL_ZPmZ_H
6466 369668063U, // UQSHL_ZPmZ_S
6467 2248683487U, // UQSHLb
6468 2248683487U, // UQSHLd
6469 2248683487U, // UQSHLh
6470 2248683487U, // UQSHLs
6471 68734943U, // UQSHLv16i8
6472 68734943U, // UQSHLv16i8_shift
6473 2248683487U, // UQSHLv1i16
6474 2248683487U, // UQSHLv1i32
6475 2248683487U, // UQSHLv1i64
6476 2248683487U, // UQSHLv1i8
6477 2216742879U, // UQSHLv2i32
6478 2216742879U, // UQSHLv2i32_shift
6479 2217267167U, // UQSHLv2i64
6480 2217267167U, // UQSHLv2i64_shift
6481 70307807U, // UQSHLv4i16
6482 70307807U, // UQSHLv4i16_shift
6483 70832095U, // UQSHLv4i32
6484 70832095U, // UQSHLv4i32_shift
6485 2218840031U, // UQSHLv8i16
6486 2218840031U, // UQSHLv8i16_shift
6487 2219364319U, // UQSHLv8i8
6488 2219364319U, // UQSHLv8i8_shift
6489 2349352600U, // UQSHRNB_ZZI_B
6490 2387642008U, // UQSHRNB_ZZI_H
6491 2416486040U, // UQSHRNB_ZZI_S
6492 2450020179U, // UQSHRNT_ZZI_B
6493 240686931U, // UQSHRNT_ZZI_H
6494 2282272595U, // UQSHRNT_ZZI_S
6495 2248683913U, // UQSHRNb
6496 2248683913U, // UQSHRNh
6497 2248683913U, // UQSHRNs
6498 2484658557U, // UQSHRNv16i8_shift
6499 2216743305U, // UQSHRNv2i32_shift
6500 70308233U, // UQSHRNv4i16_shift
6501 2486755709U, // UQSHRNv4i32_shift
6502 339796349U, // UQSHRNv8i16_shift
6503 2219364745U, // UQSHRNv8i8_shift
6504 369644421U, // UQSUBR_ZPmZ_B
6505 369652613U, // UQSUBR_ZPmZ_D
6506 2556466053U, // UQSUBR_ZPmZ_H
6507 369668997U, // UQSUBR_ZPmZ_S
6508 2584234077U, // UQSUB_ZI_B
6509 2416470109U, // UQSUB_ZI_D
6510 241731677U, // UQSUB_ZI_H
6511 2617813085U, // UQSUB_ZI_S
6512 369641565U, // UQSUB_ZPmZ_B
6513 369649757U, // UQSUB_ZPmZ_D
6514 2556463197U, // UQSUB_ZPmZ_H
6515 369666141U, // UQSUB_ZPmZ_S
6516 2584234077U, // UQSUB_ZZZ_B
6517 2416470109U, // UQSUB_ZZZ_D
6518 2389215325U, // UQSUB_ZZZ_H
6519 2617813085U, // UQSUB_ZZZ_S
6520 68733021U, // UQSUBv16i8
6521 2248681565U, // UQSUBv1i16
6522 2248681565U, // UQSUBv1i32
6523 2248681565U, // UQSUBv1i64
6524 2248681565U, // UQSUBv1i8
6525 2216740957U, // UQSUBv2i32
6526 2217265245U, // UQSUBv2i64
6527 70305885U, // UQSUBv4i16
6528 70830173U, // UQSUBv4i32
6529 2218838109U, // UQSUBv8i16
6530 2219362397U, // UQSUBv8i8
6531 201868989U, // UQXTNB_ZZ_B
6532 542148285U, // UQXTNB_ZZ_H
6533 269002429U, // UQXTNB_ZZ_S
6534 302536577U, // UQXTNT_ZZ_B
6535 542676865U, // UQXTNT_ZZ_H
6536 134788993U, // UQXTNT_ZZ_S
6537 2484658609U, // UQXTNv16i8
6538 101200319U, // UQXTNv1i16
6539 101200319U, // UQXTNv1i32
6540 101200319U, // UQXTNv1i8
6541 69259711U, // UQXTNv2i32
6542 70308287U, // UQXTNv4i16
6543 339272113U, // UQXTNv4i32
6544 339796401U, // UQXTNv8i16
6545 2219364799U, // UQXTNv8i8
6546 567943U, // URECPE_ZPmZ_S
6547 2216741511U, // URECPEv2i32
6548 70830727U, // URECPEv4i32
6549 369641907U, // URHADD_ZPmZ_B
6550 369650099U, // URHADD_ZPmZ_D
6551 2556463539U, // URHADD_ZPmZ_H
6552 369666483U, // URHADD_ZPmZ_S
6553 68733363U, // URHADDv16i8
6554 2216741299U, // URHADDv2i32
6555 70306227U, // URHADDv4i16
6556 70830515U, // URHADDv4i32
6557 2218838451U, // URHADDv8i16
6558 2219362739U, // URHADDv8i8
6559 369644533U, // URSHLR_ZPmZ_B
6560 369652725U, // URSHLR_ZPmZ_D
6561 2556466165U, // URSHLR_ZPmZ_H
6562 369669109U, // URSHLR_ZPmZ_S
6563 369643517U, // URSHL_ZPmZ_B
6564 369651709U, // URSHL_ZPmZ_D
6565 2556465149U, // URSHL_ZPmZ_H
6566 369668093U, // URSHL_ZPmZ_S
6567 68734973U, // URSHLv16i8
6568 2248683517U, // URSHLv1i64
6569 2216742909U, // URSHLv2i32
6570 2217267197U, // URSHLv2i64
6571 70307837U, // URSHLv4i16
6572 70832125U, // URSHLv4i32
6573 2218840061U, // URSHLv8i16
6574 2219364349U, // URSHLv8i8
6575 369644460U, // URSHR_ZPmI_B
6576 369652652U, // URSHR_ZPmI_D
6577 2556466092U, // URSHR_ZPmI_H
6578 369669036U, // URSHR_ZPmI_S
6579 2248684460U, // URSHRd
6580 68735916U, // URSHRv16i8_shift
6581 2216743852U, // URSHRv2i32_shift
6582 2217268140U, // URSHRv2i64_shift
6583 70308780U, // URSHRv4i16_shift
6584 70833068U, // URSHRv4i32_shift
6585 2218841004U, // URSHRv8i16_shift
6586 2219365292U, // URSHRv8i8_shift
6587 567989U, // URSQRTE_ZPmZ_S
6588 2216741557U, // URSQRTEv2i32
6589 70830773U, // URSQRTEv4i32
6590 705184570U, // URSRA_ZZI_B
6591 2282251066U, // URSRA_ZZI_D
6592 243303226U, // URSRA_ZZI_H
6593 2315821882U, // URSRA_ZZI_S
6594 2752111418U, // URSRAd
6595 337175354U, // URSRAv16i8_shift
6596 2485183290U, // URSRAv2i32_shift
6597 2485707578U, // URSRAv2i64_shift
6598 338748218U, // URSRAv4i16_shift
6599 339272506U, // URSRAv4i32_shift
6600 2487280442U, // URSRAv8i16_shift
6601 2487804730U, // URSRAv8i8_shift
6602 705214397U, // USDOT_ZZZ
6603 705214397U, // USDOT_ZZZI
6604 339277757U, // USDOTlanev16i8
6605 2485188541U, // USDOTlanev8i8
6606 339277757U, // USDOTv16i8
6607 2485188541U, // USDOTv8i8
6608 2617796041U, // USHLLB_ZZI_D
6609 2411759049U, // USHLLB_ZZI_H
6610 2349376969U, // USHLLB_ZZI_S
6611 2617800391U, // USHLLT_ZZI_D
6612 2411763399U, // USHLLT_ZZI_H
6613 2349381319U, // USHLLT_ZZI_S
6614 71352590U, // USHLLv16i8_shift
6615 2217267223U, // USHLLv2i32_shift
6616 70832151U, // USHLLv4i16_shift
6617 69779726U, // USHLLv4i32_shift
6618 2218311950U, // USHLLv8i16_shift
6619 2218840087U, // USHLLv8i8_shift
6620 68734986U, // USHLv16i8
6621 2248683530U, // USHLv1i64
6622 2216742922U, // USHLv2i32
6623 2217267210U, // USHLv2i64
6624 70307850U, // USHLv4i16
6625 70832138U, // USHLv4i32
6626 2218840074U, // USHLv8i16
6627 2219364362U, // USHLv8i8
6628 2248684473U, // USHRd
6629 68735929U, // USHRv16i8_shift
6630 2216743865U, // USHRv2i32_shift
6631 2217268153U, // USHRv2i64_shift
6632 70308793U, // USHRv4i16_shift
6633 70833081U, // USHRv4i32_shift
6634 2218841017U, // USHRv8i16_shift
6635 2219365305U, // USHRv8i8_shift
6636 339272416U, // USMMLA
6637 705209056U, // USMMLA_ZZZ
6638 369641944U, // USQADD_ZPmZ_B
6639 369650136U, // USQADD_ZPmZ_D
6640 2556463576U, // USQADD_ZPmZ_H
6641 369666520U, // USQADD_ZPmZ_S
6642 2484660696U, // USQADDv16i8
6643 604629464U, // USQADDv1i16
6644 604629464U, // USQADDv1i32
6645 604629464U, // USQADDv1i64
6646 604629464U, // USQADDv1i8
6647 2485184984U, // USQADDv2i32
6648 338225624U, // USQADDv2i64
6649 2486233560U, // USQADDv4i16
6650 339274200U, // USQADDv4i32
6651 2487282136U, // USQADDv8i16
6652 340322776U, // USQADDv8i8
6653 705184583U, // USRA_ZZI_B
6654 2282251079U, // USRA_ZZI_D
6655 243303239U, // USRA_ZZI_H
6656 2315821895U, // USRA_ZZI_S
6657 2752111431U, // USRAd
6658 337175367U, // USRAv16i8_shift
6659 2485183303U, // USRAv2i32_shift
6660 2485707591U, // USRAv2i64_shift
6661 338748231U, // USRAv4i16_shift
6662 339272519U, // USRAv4i32_shift
6663 2487280455U, // USRAv8i16_shift
6664 2487804743U, // USRAv8i8_shift
6665 2617795970U, // USUBLB_ZZZ_D
6666 264275330U, // USUBLB_ZZZ_H
6667 2349376898U, // USUBLB_ZZZ_S
6668 2617800315U, // USUBLT_ZZZ_D
6669 264279675U, // USUBLT_ZZZ_H
6670 2349381243U, // USUBLT_ZZZ_S
6671 71352542U, // USUBLv16i8_v8i16
6672 2217267077U, // USUBLv2i32_v2i64
6673 70832005U, // USUBLv4i16_v4i32
6674 69779678U, // USUBLv4i32_v2i64
6675 2218311902U, // USUBLv8i16_v4i32
6676 2218839941U, // USUBLv8i8_v8i16
6677 2416470130U, // USUBWB_ZZZ_D
6678 241731698U, // USUBWB_ZZZ_H
6679 2617813106U, // USUBWB_ZZZ_S
6680 2416474124U, // USUBWT_ZZZ_D
6681 241735692U, // USUBWT_ZZZ_H
6682 2617817100U, // USUBWT_ZZZ_S
6683 2218836480U, // USUBWv16i8_v8i16
6684 2217269605U, // USUBWv2i32_v2i64
6685 70834533U, // USUBWv4i16_v4i32
6686 2217263616U, // USUBWv4i32_v2i64
6687 70828544U, // USUBWv8i16_v4i32
6688 2218842469U, // USUBWv8i8_v8i16
6689 470314647U, // UUNPKHI_ZZ_D
6690 566267543U, // UUNPKHI_ZZ_H
6691 201895575U, // UUNPKHI_ZZ_S
6692 470315530U, // UUNPKLO_ZZ_D
6693 566268426U, // UUNPKLO_ZZ_H
6694 201896458U, // UUNPKLO_ZZ_S
6695 2148034605U, // UXTB_ZPmZ_D
6696 34637869U, // UXTB_ZPmZ_H
6697 567341U, // UXTB_ZPmZ_S
6698 2148036183U, // UXTH_ZPmZ_D
6699 568919U, // UXTH_ZPmZ_S
6700 2148039207U, // UXTW_ZPmZ_D
6701 2584231994U, // UZP1_PPP_B
6702 2416468026U, // UZP1_PPP_D
6703 2389213242U, // UZP1_PPP_H
6704 2617811002U, // UZP1_PPP_S
6705 2584231994U, // UZP1_ZZZ_B
6706 2416468026U, // UZP1_ZZZ_D
6707 2389213242U, // UZP1_ZZZ_H
6708 245530682U, // UZP1_ZZZ_Q
6709 2617811002U, // UZP1_ZZZ_S
6710 68730938U, // UZP1v16i8
6711 2216738874U, // UZP1v2i32
6712 2217263162U, // UZP1v2i64
6713 70303802U, // UZP1v4i16
6714 70828090U, // UZP1v4i32
6715 2218836026U, // UZP1v8i16
6716 2219360314U, // UZP1v8i8
6717 2584232422U, // UZP2_PPP_B
6718 2416468454U, // UZP2_PPP_D
6719 2389213670U, // UZP2_PPP_H
6720 2617811430U, // UZP2_PPP_S
6721 2584232422U, // UZP2_ZZZ_B
6722 2416468454U, // UZP2_ZZZ_D
6723 2389213670U, // UZP2_ZZZ_H
6724 245531110U, // UZP2_ZZZ_Q
6725 2617811430U, // UZP2_ZZZ_S
6726 68731366U, // UZP2v16i8
6727 2216739302U, // UZP2v2i32
6728 2217263590U, // UZP2v2i64
6729 70304230U, // UZP2v4i16
6730 70828518U, // UZP2v4i32
6731 2218836454U, // UZP2v8i16
6732 2219360742U, // UZP2v8i8
6733 13828U, // WFET
6734 13882U, // WFIT
6735 2248690226U, // WHILEGE_PWW_B
6736 2248698418U, // WHILEGE_PWW_D
6737 2392361522U, // WHILEGE_PWW_H
6738 2248714802U, // WHILEGE_PWW_S
6739 2248690226U, // WHILEGE_PXX_B
6740 2248698418U, // WHILEGE_PXX_D
6741 2392361522U, // WHILEGE_PXX_H
6742 2248714802U, // WHILEGE_PXX_S
6743 2248693277U, // WHILEGT_PWW_B
6744 2248701469U, // WHILEGT_PWW_D
6745 2392364573U, // WHILEGT_PWW_H
6746 2248717853U, // WHILEGT_PWW_S
6747 2248693277U, // WHILEGT_PXX_B
6748 2248701469U, // WHILEGT_PXX_D
6749 2392364573U, // WHILEGT_PXX_H
6750 2248717853U, // WHILEGT_PXX_S
6751 2248691324U, // WHILEHI_PWW_B
6752 2248699516U, // WHILEHI_PWW_D
6753 2392362620U, // WHILEHI_PWW_H
6754 2248715900U, // WHILEHI_PWW_S
6755 2248691324U, // WHILEHI_PXX_B
6756 2248699516U, // WHILEHI_PXX_D
6757 2392362620U, // WHILEHI_PXX_H
6758 2248715900U, // WHILEHI_PXX_S
6759 2248693021U, // WHILEHS_PWW_B
6760 2248701213U, // WHILEHS_PWW_D
6761 2392364317U, // WHILEHS_PWW_H
6762 2248717597U, // WHILEHS_PWW_S
6763 2248693021U, // WHILEHS_PXX_B
6764 2248701213U, // WHILEHS_PXX_D
6765 2392364317U, // WHILEHS_PXX_H
6766 2248717597U, // WHILEHS_PXX_S
6767 2248690257U, // WHILELE_PWW_B
6768 2248698449U, // WHILELE_PWW_D
6769 2392361553U, // WHILELE_PWW_H
6770 2248714833U, // WHILELE_PWW_S
6771 2248690257U, // WHILELE_PXX_B
6772 2248698449U, // WHILELE_PXX_D
6773 2392361553U, // WHILELE_PXX_H
6774 2248714833U, // WHILELE_PXX_S
6775 2248692207U, // WHILELO_PWW_B
6776 2248700399U, // WHILELO_PWW_D
6777 2392363503U, // WHILELO_PWW_H
6778 2248716783U, // WHILELO_PWW_S
6779 2248692207U, // WHILELO_PXX_B
6780 2248700399U, // WHILELO_PXX_D
6781 2392363503U, // WHILELO_PXX_H
6782 2248716783U, // WHILELO_PXX_S
6783 2248693048U, // WHILELS_PWW_B
6784 2248701240U, // WHILELS_PWW_D
6785 2392364344U, // WHILELS_PWW_H
6786 2248717624U, // WHILELS_PWW_S
6787 2248693048U, // WHILELS_PXX_B
6788 2248701240U, // WHILELS_PXX_D
6789 2392364344U, // WHILELS_PXX_H
6790 2248717624U, // WHILELS_PXX_S
6791 2248693425U, // WHILELT_PWW_B
6792 2248701617U, // WHILELT_PWW_D
6793 2392364721U, // WHILELT_PWW_H
6794 2248718001U, // WHILELT_PWW_S
6795 2248693425U, // WHILELT_PXX_B
6796 2248701617U, // WHILELT_PXX_D
6797 2392364721U, // WHILELT_PXX_H
6798 2248718001U, // WHILELT_PXX_S
6799 2248694208U, // WHILERW_PXX_B
6800 2248702400U, // WHILERW_PXX_D
6801 2392365504U, // WHILERW_PXX_H
6802 2248718784U, // WHILERW_PXX_S
6803 2248692885U, // WHILEWR_PXX_B
6804 2248701077U, // WHILEWR_PXX_D
6805 2392364181U, // WHILEWR_PXX_H
6806 2248717461U, // WHILEWR_PXX_S
6807 21406U, // WRFFR
6808 7315U, // XAFLAG
6809 2217268065U, // XAR
6810 2584236897U, // XAR_ZZZI_B
6811 2416472929U, // XAR_ZZZI_D
6812 2389218145U, // XAR_ZZZI_H
6813 2617815905U, // XAR_ZZZI_S
6814 10600U, // XPACD
6815 11893U, // XPACI
6816 7173U, // XPACLRI
6817 2484658603U, // XTNv16i8
6818 69259706U, // XTNv2i32
6819 70308282U, // XTNv4i16
6820 339272107U, // XTNv4i32
6821 339796395U, // XTNv8i16
6822 2219364794U, // XTNv8i8
6823 2584231988U, // ZIP1_PPP_B
6824 2416468020U, // ZIP1_PPP_D
6825 2389213236U, // ZIP1_PPP_H
6826 2617810996U, // ZIP1_PPP_S
6827 2584231988U, // ZIP1_ZZZ_B
6828 2416468020U, // ZIP1_ZZZ_D
6829 2389213236U, // ZIP1_ZZZ_H
6830 245530676U, // ZIP1_ZZZ_Q
6831 2617810996U, // ZIP1_ZZZ_S
6832 68730932U, // ZIP1v16i8
6833 2216738868U, // ZIP1v2i32
6834 2217263156U, // ZIP1v2i64
6835 70303796U, // ZIP1v4i16
6836 70828084U, // ZIP1v4i32
6837 2218836020U, // ZIP1v8i16
6838 2219360308U, // ZIP1v8i8
6839 2584232416U, // ZIP2_PPP_B
6840 2416468448U, // ZIP2_PPP_D
6841 2389213664U, // ZIP2_PPP_H
6842 2617811424U, // ZIP2_PPP_S
6843 2584232416U, // ZIP2_ZZZ_B
6844 2416468448U, // ZIP2_ZZZ_D
6845 2389213664U, // ZIP2_ZZZ_H
6846 245531104U, // ZIP2_ZZZ_Q
6847 2617811424U, // ZIP2_ZZZ_S
6848 68731360U, // ZIP2v16i8
6849 2216739296U, // ZIP2v2i32
6850 2217263584U, // ZIP2v2i64
6851 70304224U, // ZIP2v4i16
6852 70828512U, // ZIP2v4i32
6853 2218836448U, // ZIP2v8i16
6854 2219360736U, // ZIP2v8i8
6855 };
6856
6857 static const uint32_t OpInfo1[] = {
6858 0U, // PHI
6859 0U, // INLINEASM
6860 0U, // INLINEASM_BR
6861 0U, // CFI_INSTRUCTION
6862 0U, // EH_LABEL
6863 0U, // GC_LABEL
6864 0U, // ANNOTATION_LABEL
6865 0U, // KILL
6866 0U, // EXTRACT_SUBREG
6867 0U, // INSERT_SUBREG
6868 0U, // IMPLICIT_DEF
6869 0U, // SUBREG_TO_REG
6870 0U, // COPY_TO_REGCLASS
6871 0U, // DBG_VALUE
6872 0U, // DBG_INSTR_REF
6873 0U, // DBG_LABEL
6874 0U, // REG_SEQUENCE
6875 0U, // COPY
6876 0U, // BUNDLE
6877 0U, // LIFETIME_START
6878 0U, // LIFETIME_END
6879 0U, // PSEUDO_PROBE
6880 0U, // STACKMAP
6881 0U, // FENTRY_CALL
6882 0U, // PATCHPOINT
6883 0U, // LOAD_STACK_GUARD
6884 0U, // PREALLOCATED_SETUP
6885 0U, // PREALLOCATED_ARG
6886 0U, // STATEPOINT
6887 0U, // LOCAL_ESCAPE
6888 0U, // FAULTING_OP
6889 0U, // PATCHABLE_OP
6890 0U, // PATCHABLE_FUNCTION_ENTER
6891 0U, // PATCHABLE_RET
6892 0U, // PATCHABLE_FUNCTION_EXIT
6893 0U, // PATCHABLE_TAIL_CALL
6894 0U, // PATCHABLE_EVENT_CALL
6895 0U, // PATCHABLE_TYPED_EVENT_CALL
6896 0U, // ICALL_BRANCH_FUNNEL
6897 0U, // G_ADD
6898 0U, // G_SUB
6899 0U, // G_MUL
6900 0U, // G_SDIV
6901 0U, // G_UDIV
6902 0U, // G_SREM
6903 0U, // G_UREM
6904 0U, // G_AND
6905 0U, // G_OR
6906 0U, // G_XOR
6907 0U, // G_IMPLICIT_DEF
6908 0U, // G_PHI
6909 0U, // G_FRAME_INDEX
6910 0U, // G_GLOBAL_VALUE
6911 0U, // G_EXTRACT
6912 0U, // G_UNMERGE_VALUES
6913 0U, // G_INSERT
6914 0U, // G_MERGE_VALUES
6915 0U, // G_BUILD_VECTOR
6916 0U, // G_BUILD_VECTOR_TRUNC
6917 0U, // G_CONCAT_VECTORS
6918 0U, // G_PTRTOINT
6919 0U, // G_INTTOPTR
6920 0U, // G_BITCAST
6921 0U, // G_FREEZE
6922 0U, // G_INTRINSIC_TRUNC
6923 0U, // G_INTRINSIC_ROUND
6924 0U, // G_INTRINSIC_LRINT
6925 0U, // G_INTRINSIC_ROUNDEVEN
6926 0U, // G_READCYCLECOUNTER
6927 0U, // G_LOAD
6928 0U, // G_SEXTLOAD
6929 0U, // G_ZEXTLOAD
6930 0U, // G_INDEXED_LOAD
6931 0U, // G_INDEXED_SEXTLOAD
6932 0U, // G_INDEXED_ZEXTLOAD
6933 0U, // G_STORE
6934 0U, // G_INDEXED_STORE
6935 0U, // G_ATOMIC_CMPXCHG_WITH_SUCCESS
6936 0U, // G_ATOMIC_CMPXCHG
6937 0U, // G_ATOMICRMW_XCHG
6938 0U, // G_ATOMICRMW_ADD
6939 0U, // G_ATOMICRMW_SUB
6940 0U, // G_ATOMICRMW_AND
6941 0U, // G_ATOMICRMW_NAND
6942 0U, // G_ATOMICRMW_OR
6943 0U, // G_ATOMICRMW_XOR
6944 0U, // G_ATOMICRMW_MAX
6945 0U, // G_ATOMICRMW_MIN
6946 0U, // G_ATOMICRMW_UMAX
6947 0U, // G_ATOMICRMW_UMIN
6948 0U, // G_ATOMICRMW_FADD
6949 0U, // G_ATOMICRMW_FSUB
6950 0U, // G_FENCE
6951 0U, // G_BRCOND
6952 0U, // G_BRINDIRECT
6953 0U, // G_INTRINSIC
6954 0U, // G_INTRINSIC_W_SIDE_EFFECTS
6955 0U, // G_ANYEXT
6956 0U, // G_TRUNC
6957 0U, // G_CONSTANT
6958 0U, // G_FCONSTANT
6959 0U, // G_VASTART
6960 0U, // G_VAARG
6961 0U, // G_SEXT
6962 0U, // G_SEXT_INREG
6963 0U, // G_ZEXT
6964 0U, // G_SHL
6965 0U, // G_LSHR
6966 0U, // G_ASHR
6967 0U, // G_FSHL
6968 0U, // G_FSHR
6969 0U, // G_ICMP
6970 0U, // G_FCMP
6971 0U, // G_SELECT
6972 0U, // G_UADDO
6973 0U, // G_UADDE
6974 0U, // G_USUBO
6975 0U, // G_USUBE
6976 0U, // G_SADDO
6977 0U, // G_SADDE
6978 0U, // G_SSUBO
6979 0U, // G_SSUBE
6980 0U, // G_UMULO
6981 0U, // G_SMULO
6982 0U, // G_UMULH
6983 0U, // G_SMULH
6984 0U, // G_UADDSAT
6985 0U, // G_SADDSAT
6986 0U, // G_USUBSAT
6987 0U, // G_SSUBSAT
6988 0U, // G_USHLSAT
6989 0U, // G_SSHLSAT
6990 0U, // G_SMULFIX
6991 0U, // G_UMULFIX
6992 0U, // G_SMULFIXSAT
6993 0U, // G_UMULFIXSAT
6994 0U, // G_SDIVFIX
6995 0U, // G_UDIVFIX
6996 0U, // G_SDIVFIXSAT
6997 0U, // G_UDIVFIXSAT
6998 0U, // G_FADD
6999 0U, // G_FSUB
7000 0U, // G_FMUL
7001 0U, // G_FMA
7002 0U, // G_FMAD
7003 0U, // G_FDIV
7004 0U, // G_FREM
7005 0U, // G_FPOW
7006 0U, // G_FPOWI
7007 0U, // G_FEXP
7008 0U, // G_FEXP2
7009 0U, // G_FLOG
7010 0U, // G_FLOG2
7011 0U, // G_FLOG10
7012 0U, // G_FNEG
7013 0U, // G_FPEXT
7014 0U, // G_FPTRUNC
7015 0U, // G_FPTOSI
7016 0U, // G_FPTOUI
7017 0U, // G_SITOFP
7018 0U, // G_UITOFP
7019 0U, // G_FABS
7020 0U, // G_FCOPYSIGN
7021 0U, // G_FCANONICALIZE
7022 0U, // G_FMINNUM
7023 0U, // G_FMAXNUM
7024 0U, // G_FMINNUM_IEEE
7025 0U, // G_FMAXNUM_IEEE
7026 0U, // G_FMINIMUM
7027 0U, // G_FMAXIMUM
7028 0U, // G_PTR_ADD
7029 0U, // G_PTRMASK
7030 0U, // G_SMIN
7031 0U, // G_SMAX
7032 0U, // G_UMIN
7033 0U, // G_UMAX
7034 0U, // G_ABS
7035 0U, // G_BR
7036 0U, // G_BRJT
7037 0U, // G_INSERT_VECTOR_ELT
7038 0U, // G_EXTRACT_VECTOR_ELT
7039 0U, // G_SHUFFLE_VECTOR
7040 0U, // G_CTTZ
7041 0U, // G_CTTZ_ZERO_UNDEF
7042 0U, // G_CTLZ
7043 0U, // G_CTLZ_ZERO_UNDEF
7044 0U, // G_CTPOP
7045 0U, // G_BSWAP
7046 0U, // G_BITREVERSE
7047 0U, // G_FCEIL
7048 0U, // G_FCOS
7049 0U, // G_FSIN
7050 0U, // G_FSQRT
7051 0U, // G_FFLOOR
7052 0U, // G_FRINT
7053 0U, // G_FNEARBYINT
7054 0U, // G_ADDRSPACE_CAST
7055 0U, // G_BLOCK_ADDR
7056 0U, // G_JUMP_TABLE
7057 0U, // G_DYN_STACKALLOC
7058 0U, // G_STRICT_FADD
7059 0U, // G_STRICT_FSUB
7060 0U, // G_STRICT_FMUL
7061 0U, // G_STRICT_FDIV
7062 0U, // G_STRICT_FREM
7063 0U, // G_STRICT_FMA
7064 0U, // G_STRICT_FSQRT
7065 0U, // G_READ_REGISTER
7066 0U, // G_WRITE_REGISTER
7067 0U, // G_MEMCPY
7068 0U, // G_MEMMOVE
7069 0U, // G_MEMSET
7070 0U, // G_VECREDUCE_SEQ_FADD
7071 0U, // G_VECREDUCE_SEQ_FMUL
7072 0U, // G_VECREDUCE_FADD
7073 0U, // G_VECREDUCE_FMUL
7074 0U, // G_VECREDUCE_FMAX
7075 0U, // G_VECREDUCE_FMIN
7076 0U, // G_VECREDUCE_ADD
7077 0U, // G_VECREDUCE_MUL
7078 0U, // G_VECREDUCE_AND
7079 0U, // G_VECREDUCE_OR
7080 0U, // G_VECREDUCE_XOR
7081 0U, // G_VECREDUCE_SMAX
7082 0U, // G_VECREDUCE_SMIN
7083 0U, // G_VECREDUCE_UMAX
7084 0U, // G_VECREDUCE_UMIN
7085 0U, // ADDSWrr
7086 0U, // ADDSXrr
7087 0U, // ADDWrr
7088 0U, // ADDXrr
7089 0U, // ADD_ZPZZ_UNDEF_B
7090 0U, // ADD_ZPZZ_UNDEF_D
7091 0U, // ADD_ZPZZ_UNDEF_H
7092 0U, // ADD_ZPZZ_UNDEF_S
7093 0U, // ADD_ZPZZ_ZERO_B
7094 0U, // ADD_ZPZZ_ZERO_D
7095 0U, // ADD_ZPZZ_ZERO_H
7096 0U, // ADD_ZPZZ_ZERO_S
7097 0U, // ADDlowTLS
7098 0U, // ADJCALLSTACKDOWN
7099 0U, // ADJCALLSTACKUP
7100 0U, // AESIMCrrTied
7101 0U, // AESMCrrTied
7102 0U, // ANDSWrr
7103 0U, // ANDSXrr
7104 0U, // ANDWrr
7105 0U, // ANDXrr
7106 0U, // ASRD_ZPZI_ZERO_B
7107 0U, // ASRD_ZPZI_ZERO_D
7108 0U, // ASRD_ZPZI_ZERO_H
7109 0U, // ASRD_ZPZI_ZERO_S
7110 0U, // ASR_ZPZI_UNDEF_B
7111 0U, // ASR_ZPZI_UNDEF_D
7112 0U, // ASR_ZPZI_UNDEF_H
7113 0U, // ASR_ZPZI_UNDEF_S
7114 0U, // ASR_ZPZZ_UNDEF_B
7115 0U, // ASR_ZPZZ_UNDEF_D
7116 0U, // ASR_ZPZZ_UNDEF_H
7117 0U, // ASR_ZPZZ_UNDEF_S
7118 0U, // ASR_ZPZZ_ZERO_B
7119 0U, // ASR_ZPZZ_ZERO_D
7120 0U, // ASR_ZPZZ_ZERO_H
7121 0U, // ASR_ZPZZ_ZERO_S
7122 0U, // BICSWrr
7123 0U, // BICSXrr
7124 0U, // BICWrr
7125 0U, // BICXrr
7126 0U, // BLRNoIP
7127 0U, // BLR_RVMARKER
7128 0U, // BSPv16i8
7129 0U, // BSPv8i8
7130 0U, // CATCHRET
7131 0U, // CLEANUPRET
7132 0U, // CMP_SWAP_128
7133 0U, // CMP_SWAP_16
7134 0U, // CMP_SWAP_32
7135 0U, // CMP_SWAP_64
7136 0U, // CMP_SWAP_8
7137 0U, // CompilerBarrier
7138 0U, // EMITBKEY
7139 0U, // EONWrr
7140 0U, // EONXrr
7141 0U, // EORWrr
7142 0U, // EORXrr
7143 0U, // F128CSEL
7144 0U, // FABD_ZPZZ_ZERO_D
7145 0U, // FABD_ZPZZ_ZERO_H
7146 0U, // FABD_ZPZZ_ZERO_S
7147 0U, // FADD_ZPZZ_UNDEF_D
7148 0U, // FADD_ZPZZ_UNDEF_H
7149 0U, // FADD_ZPZZ_UNDEF_S
7150 0U, // FADD_ZPZZ_ZERO_D
7151 0U, // FADD_ZPZZ_ZERO_H
7152 0U, // FADD_ZPZZ_ZERO_S
7153 0U, // FDIVR_ZPZZ_ZERO_D
7154 0U, // FDIVR_ZPZZ_ZERO_H
7155 0U, // FDIVR_ZPZZ_ZERO_S
7156 0U, // FDIV_ZPZZ_UNDEF_D
7157 0U, // FDIV_ZPZZ_UNDEF_H
7158 0U, // FDIV_ZPZZ_UNDEF_S
7159 0U, // FDIV_ZPZZ_ZERO_D
7160 0U, // FDIV_ZPZZ_ZERO_H
7161 0U, // FDIV_ZPZZ_ZERO_S
7162 0U, // FMAXNM_ZPZZ_UNDEF_D
7163 0U, // FMAXNM_ZPZZ_UNDEF_H
7164 0U, // FMAXNM_ZPZZ_UNDEF_S
7165 0U, // FMAXNM_ZPZZ_ZERO_D
7166 0U, // FMAXNM_ZPZZ_ZERO_H
7167 0U, // FMAXNM_ZPZZ_ZERO_S
7168 0U, // FMAX_ZPZZ_ZERO_D
7169 0U, // FMAX_ZPZZ_ZERO_H
7170 0U, // FMAX_ZPZZ_ZERO_S
7171 0U, // FMINNM_ZPZZ_UNDEF_D
7172 0U, // FMINNM_ZPZZ_UNDEF_H
7173 0U, // FMINNM_ZPZZ_UNDEF_S
7174 0U, // FMINNM_ZPZZ_ZERO_D
7175 0U, // FMINNM_ZPZZ_ZERO_H
7176 0U, // FMINNM_ZPZZ_ZERO_S
7177 0U, // FMIN_ZPZZ_ZERO_D
7178 0U, // FMIN_ZPZZ_ZERO_H
7179 0U, // FMIN_ZPZZ_ZERO_S
7180 0U, // FMOVD0
7181 0U, // FMOVH0
7182 0U, // FMOVS0
7183 0U, // FMULX_ZPZZ_ZERO_D
7184 0U, // FMULX_ZPZZ_ZERO_H
7185 0U, // FMULX_ZPZZ_ZERO_S
7186 0U, // FMUL_ZPZZ_UNDEF_D
7187 0U, // FMUL_ZPZZ_UNDEF_H
7188 0U, // FMUL_ZPZZ_UNDEF_S
7189 0U, // FMUL_ZPZZ_ZERO_D
7190 0U, // FMUL_ZPZZ_ZERO_H
7191 0U, // FMUL_ZPZZ_ZERO_S
7192 0U, // FSUBR_ZPZZ_ZERO_D
7193 0U, // FSUBR_ZPZZ_ZERO_H
7194 0U, // FSUBR_ZPZZ_ZERO_S
7195 0U, // FSUB_ZPZZ_UNDEF_D
7196 0U, // FSUB_ZPZZ_UNDEF_H
7197 0U, // FSUB_ZPZZ_UNDEF_S
7198 0U, // FSUB_ZPZZ_ZERO_D
7199 0U, // FSUB_ZPZZ_ZERO_H
7200 0U, // FSUB_ZPZZ_ZERO_S
7201 0U, // GLD1B_D
7202 0U, // GLD1B_D_IMM
7203 0U, // GLD1B_D_SXTW
7204 0U, // GLD1B_D_UXTW
7205 0U, // GLD1B_S_IMM
7206 0U, // GLD1B_S_SXTW
7207 0U, // GLD1B_S_UXTW
7208 0U, // GLD1D
7209 0U, // GLD1D_IMM
7210 0U, // GLD1D_SCALED
7211 0U, // GLD1D_SXTW
7212 0U, // GLD1D_SXTW_SCALED
7213 0U, // GLD1D_UXTW
7214 0U, // GLD1D_UXTW_SCALED
7215 0U, // GLD1H_D
7216 0U, // GLD1H_D_IMM
7217 0U, // GLD1H_D_SCALED
7218 0U, // GLD1H_D_SXTW
7219 0U, // GLD1H_D_SXTW_SCALED
7220 0U, // GLD1H_D_UXTW
7221 0U, // GLD1H_D_UXTW_SCALED
7222 0U, // GLD1H_S_IMM
7223 0U, // GLD1H_S_SXTW
7224 0U, // GLD1H_S_SXTW_SCALED
7225 0U, // GLD1H_S_UXTW
7226 0U, // GLD1H_S_UXTW_SCALED
7227 0U, // GLD1SB_D
7228 0U, // GLD1SB_D_IMM
7229 0U, // GLD1SB_D_SXTW
7230 0U, // GLD1SB_D_UXTW
7231 0U, // GLD1SB_S_IMM
7232 0U, // GLD1SB_S_SXTW
7233 0U, // GLD1SB_S_UXTW
7234 0U, // GLD1SH_D
7235 0U, // GLD1SH_D_IMM
7236 0U, // GLD1SH_D_SCALED
7237 0U, // GLD1SH_D_SXTW
7238 0U, // GLD1SH_D_SXTW_SCALED
7239 0U, // GLD1SH_D_UXTW
7240 0U, // GLD1SH_D_UXTW_SCALED
7241 0U, // GLD1SH_S_IMM
7242 0U, // GLD1SH_S_SXTW
7243 0U, // GLD1SH_S_SXTW_SCALED
7244 0U, // GLD1SH_S_UXTW
7245 0U, // GLD1SH_S_UXTW_SCALED
7246 0U, // GLD1SW_D
7247 0U, // GLD1SW_D_IMM
7248 0U, // GLD1SW_D_SCALED
7249 0U, // GLD1SW_D_SXTW
7250 0U, // GLD1SW_D_SXTW_SCALED
7251 0U, // GLD1SW_D_UXTW
7252 0U, // GLD1SW_D_UXTW_SCALED
7253 0U, // GLD1W_D
7254 0U, // GLD1W_D_IMM
7255 0U, // GLD1W_D_SCALED
7256 0U, // GLD1W_D_SXTW
7257 0U, // GLD1W_D_SXTW_SCALED
7258 0U, // GLD1W_D_UXTW
7259 0U, // GLD1W_D_UXTW_SCALED
7260 0U, // GLD1W_IMM
7261 0U, // GLD1W_SXTW
7262 0U, // GLD1W_SXTW_SCALED
7263 0U, // GLD1W_UXTW
7264 0U, // GLD1W_UXTW_SCALED
7265 0U, // GLDFF1B_D
7266 0U, // GLDFF1B_D_IMM
7267 0U, // GLDFF1B_D_SXTW
7268 0U, // GLDFF1B_D_UXTW
7269 0U, // GLDFF1B_S_IMM
7270 0U, // GLDFF1B_S_SXTW
7271 0U, // GLDFF1B_S_UXTW
7272 0U, // GLDFF1D
7273 0U, // GLDFF1D_IMM
7274 0U, // GLDFF1D_SCALED
7275 0U, // GLDFF1D_SXTW
7276 0U, // GLDFF1D_SXTW_SCALED
7277 0U, // GLDFF1D_UXTW
7278 0U, // GLDFF1D_UXTW_SCALED
7279 0U, // GLDFF1H_D
7280 0U, // GLDFF1H_D_IMM
7281 0U, // GLDFF1H_D_SCALED
7282 0U, // GLDFF1H_D_SXTW
7283 0U, // GLDFF1H_D_SXTW_SCALED
7284 0U, // GLDFF1H_D_UXTW
7285 0U, // GLDFF1H_D_UXTW_SCALED
7286 0U, // GLDFF1H_S_IMM
7287 0U, // GLDFF1H_S_SXTW
7288 0U, // GLDFF1H_S_SXTW_SCALED
7289 0U, // GLDFF1H_S_UXTW
7290 0U, // GLDFF1H_S_UXTW_SCALED
7291 0U, // GLDFF1SB_D
7292 0U, // GLDFF1SB_D_IMM
7293 0U, // GLDFF1SB_D_SXTW
7294 0U, // GLDFF1SB_D_UXTW
7295 0U, // GLDFF1SB_S_IMM
7296 0U, // GLDFF1SB_S_SXTW
7297 0U, // GLDFF1SB_S_UXTW
7298 0U, // GLDFF1SH_D
7299 0U, // GLDFF1SH_D_IMM
7300 0U, // GLDFF1SH_D_SCALED
7301 0U, // GLDFF1SH_D_SXTW
7302 0U, // GLDFF1SH_D_SXTW_SCALED
7303 0U, // GLDFF1SH_D_UXTW
7304 0U, // GLDFF1SH_D_UXTW_SCALED
7305 0U, // GLDFF1SH_S_IMM
7306 0U, // GLDFF1SH_S_SXTW
7307 0U, // GLDFF1SH_S_SXTW_SCALED
7308 0U, // GLDFF1SH_S_UXTW
7309 0U, // GLDFF1SH_S_UXTW_SCALED
7310 0U, // GLDFF1SW_D
7311 0U, // GLDFF1SW_D_IMM
7312 0U, // GLDFF1SW_D_SCALED
7313 0U, // GLDFF1SW_D_SXTW
7314 0U, // GLDFF1SW_D_SXTW_SCALED
7315 0U, // GLDFF1SW_D_UXTW
7316 0U, // GLDFF1SW_D_UXTW_SCALED
7317 0U, // GLDFF1W_D
7318 0U, // GLDFF1W_D_IMM
7319 0U, // GLDFF1W_D_SCALED
7320 0U, // GLDFF1W_D_SXTW
7321 0U, // GLDFF1W_D_SXTW_SCALED
7322 0U, // GLDFF1W_D_UXTW
7323 0U, // GLDFF1W_D_UXTW_SCALED
7324 0U, // GLDFF1W_IMM
7325 0U, // GLDFF1W_SXTW
7326 0U, // GLDFF1W_SXTW_SCALED
7327 0U, // GLDFF1W_UXTW
7328 0U, // GLDFF1W_UXTW_SCALED
7329 0U, // G_ADD_LOW
7330 0U, // G_DUP
7331 0U, // G_DUPLANE16
7332 0U, // G_DUPLANE32
7333 0U, // G_DUPLANE64
7334 0U, // G_DUPLANE8
7335 0U, // G_EXT
7336 0U, // G_REV16
7337 0U, // G_REV32
7338 0U, // G_REV64
7339 0U, // G_SITOF
7340 0U, // G_TRN1
7341 0U, // G_TRN2
7342 0U, // G_UITOF
7343 0U, // G_UZP1
7344 0U, // G_UZP2
7345 0U, // G_VASHR
7346 0U, // G_VLSHR
7347 0U, // G_ZIP1
7348 0U, // G_ZIP2
7349 0U, // HWASAN_CHECK_MEMACCESS
7350 0U, // HWASAN_CHECK_MEMACCESS_SHORTGRANULES
7351 0U, // IRGstack
7352 0U, // JumpTableDest16
7353 0U, // JumpTableDest32
7354 0U, // JumpTableDest8
7355 0U, // LD1B_D_IMM
7356 0U, // LD1B_H_IMM
7357 0U, // LD1B_IMM
7358 0U, // LD1B_S_IMM
7359 0U, // LD1D_IMM
7360 0U, // LD1H_D_IMM
7361 0U, // LD1H_IMM
7362 0U, // LD1H_S_IMM
7363 0U, // LD1SB_D_IMM
7364 0U, // LD1SB_H_IMM
7365 0U, // LD1SB_S_IMM
7366 0U, // LD1SH_D_IMM
7367 0U, // LD1SH_S_IMM
7368 0U, // LD1SW_D_IMM
7369 0U, // LD1W_D_IMM
7370 0U, // LD1W_IMM
7371 0U, // LDFF1B
7372 0U, // LDFF1B_D
7373 0U, // LDFF1B_H
7374 0U, // LDFF1B_S
7375 0U, // LDFF1D
7376 0U, // LDFF1H
7377 0U, // LDFF1H_D
7378 0U, // LDFF1H_S
7379 0U, // LDFF1SB_D
7380 0U, // LDFF1SB_H
7381 0U, // LDFF1SB_S
7382 0U, // LDFF1SH_D
7383 0U, // LDFF1SH_S
7384 0U, // LDFF1SW_D
7385 0U, // LDFF1W
7386 0U, // LDFF1W_D
7387 0U, // LDNF1B_D_IMM
7388 0U, // LDNF1B_H_IMM
7389 0U, // LDNF1B_IMM
7390 0U, // LDNF1B_S_IMM
7391 0U, // LDNF1D_IMM
7392 0U, // LDNF1H_D_IMM
7393 0U, // LDNF1H_IMM
7394 0U, // LDNF1H_S_IMM
7395 0U, // LDNF1SB_D_IMM
7396 0U, // LDNF1SB_H_IMM
7397 0U, // LDNF1SB_S_IMM
7398 0U, // LDNF1SH_D_IMM
7399 0U, // LDNF1SH_S_IMM
7400 0U, // LDNF1SW_D_IMM
7401 0U, // LDNF1W_D_IMM
7402 0U, // LDNF1W_IMM
7403 0U, // LDR_ZZXI
7404 0U, // LDR_ZZZXI
7405 0U, // LDR_ZZZZXI
7406 0U, // LOADgot
7407 0U, // LSL_ZPZI_UNDEF_B
7408 0U, // LSL_ZPZI_UNDEF_D
7409 0U, // LSL_ZPZI_UNDEF_H
7410 0U, // LSL_ZPZI_UNDEF_S
7411 0U, // LSL_ZPZZ_UNDEF_B
7412 0U, // LSL_ZPZZ_UNDEF_D
7413 0U, // LSL_ZPZZ_UNDEF_H
7414 0U, // LSL_ZPZZ_UNDEF_S
7415 0U, // LSL_ZPZZ_ZERO_B
7416 0U, // LSL_ZPZZ_ZERO_D
7417 0U, // LSL_ZPZZ_ZERO_H
7418 0U, // LSL_ZPZZ_ZERO_S
7419 0U, // LSR_ZPZI_UNDEF_B
7420 0U, // LSR_ZPZI_UNDEF_D
7421 0U, // LSR_ZPZI_UNDEF_H
7422 0U, // LSR_ZPZI_UNDEF_S
7423 0U, // LSR_ZPZZ_UNDEF_B
7424 0U, // LSR_ZPZZ_UNDEF_D
7425 0U, // LSR_ZPZZ_UNDEF_H
7426 0U, // LSR_ZPZZ_UNDEF_S
7427 0U, // LSR_ZPZZ_ZERO_B
7428 0U, // LSR_ZPZZ_ZERO_D
7429 0U, // LSR_ZPZZ_ZERO_H
7430 0U, // LSR_ZPZZ_ZERO_S
7431 0U, // MOVMCSym
7432 0U, // MOVaddr
7433 0U, // MOVaddrBA
7434 0U, // MOVaddrCP
7435 0U, // MOVaddrEXT
7436 0U, // MOVaddrJT
7437 0U, // MOVaddrTLS
7438 0U, // MOVbaseTLS
7439 0U, // MOVi32imm
7440 0U, // MOVi64imm
7441 0U, // MUL_ZPZZ_UNDEF_B
7442 0U, // MUL_ZPZZ_UNDEF_D
7443 0U, // MUL_ZPZZ_UNDEF_H
7444 0U, // MUL_ZPZZ_UNDEF_S
7445 0U, // ORNWrr
7446 0U, // ORNXrr
7447 0U, // ORRWrr
7448 0U, // ORRXrr
7449 0U, // RDFFR_P
7450 0U, // RDFFR_PPz
7451 0U, // RET_ReallyLR
7452 0U, // SDIV_ZPZZ_UNDEF_D
7453 0U, // SDIV_ZPZZ_UNDEF_S
7454 0U, // SEH_AddFP
7455 0U, // SEH_EpilogEnd
7456 0U, // SEH_EpilogStart
7457 0U, // SEH_Nop
7458 0U, // SEH_PrologEnd
7459 0U, // SEH_SaveFPLR
7460 0U, // SEH_SaveFPLR_X
7461 0U, // SEH_SaveFReg
7462 0U, // SEH_SaveFRegP
7463 0U, // SEH_SaveFRegP_X
7464 0U, // SEH_SaveFReg_X
7465 0U, // SEH_SaveReg
7466 0U, // SEH_SaveRegP
7467 0U, // SEH_SaveRegP_X
7468 0U, // SEH_SaveReg_X
7469 0U, // SEH_SetFP
7470 0U, // SEH_StackAlloc
7471 0U, // SMAX_ZPZZ_UNDEF_B
7472 0U, // SMAX_ZPZZ_UNDEF_D
7473 0U, // SMAX_ZPZZ_UNDEF_H
7474 0U, // SMAX_ZPZZ_UNDEF_S
7475 0U, // SMIN_ZPZZ_UNDEF_B
7476 0U, // SMIN_ZPZZ_UNDEF_D
7477 0U, // SMIN_ZPZZ_UNDEF_H
7478 0U, // SMIN_ZPZZ_UNDEF_S
7479 0U, // SPACE
7480 0U, // SQSHLU_ZPZI_ZERO_B
7481 0U, // SQSHLU_ZPZI_ZERO_D
7482 0U, // SQSHLU_ZPZI_ZERO_H
7483 0U, // SQSHLU_ZPZI_ZERO_S
7484 0U, // SQSHL_ZPZI_ZERO_B
7485 0U, // SQSHL_ZPZI_ZERO_D
7486 0U, // SQSHL_ZPZI_ZERO_H
7487 0U, // SQSHL_ZPZI_ZERO_S
7488 0U, // SRSHR_ZPZI_ZERO_B
7489 0U, // SRSHR_ZPZI_ZERO_D
7490 0U, // SRSHR_ZPZI_ZERO_H
7491 0U, // SRSHR_ZPZI_ZERO_S
7492 0U, // STGloop
7493 0U, // STGloop_wback
7494 0U, // STR_ZZXI
7495 0U, // STR_ZZZXI
7496 0U, // STR_ZZZZXI
7497 0U, // STZGloop
7498 0U, // STZGloop_wback
7499 0U, // SUBR_ZPZZ_ZERO_B
7500 0U, // SUBR_ZPZZ_ZERO_D
7501 0U, // SUBR_ZPZZ_ZERO_H
7502 0U, // SUBR_ZPZZ_ZERO_S
7503 0U, // SUBSWrr
7504 0U, // SUBSXrr
7505 0U, // SUBWrr
7506 0U, // SUBXrr
7507 0U, // SUB_ZPZZ_UNDEF_B
7508 0U, // SUB_ZPZZ_UNDEF_D
7509 0U, // SUB_ZPZZ_UNDEF_H
7510 0U, // SUB_ZPZZ_UNDEF_S
7511 0U, // SUB_ZPZZ_ZERO_B
7512 0U, // SUB_ZPZZ_ZERO_D
7513 0U, // SUB_ZPZZ_ZERO_H
7514 0U, // SUB_ZPZZ_ZERO_S
7515 0U, // SpeculationBarrierISBDSBEndBB
7516 0U, // SpeculationBarrierSBEndBB
7517 0U, // SpeculationSafeValueW
7518 0U, // SpeculationSafeValueX
7519 0U, // TAGPstack
7520 0U, // TCRETURNdi
7521 0U, // TCRETURNri
7522 0U, // TCRETURNriALL
7523 0U, // TCRETURNriBTI
7524 0U, // TLSDESCCALL
7525 0U, // TLSDESC_CALLSEQ
7526 0U, // UDIV_ZPZZ_UNDEF_D
7527 0U, // UDIV_ZPZZ_UNDEF_S
7528 0U, // UMAX_ZPZZ_UNDEF_B
7529 0U, // UMAX_ZPZZ_UNDEF_D
7530 0U, // UMAX_ZPZZ_UNDEF_H
7531 0U, // UMAX_ZPZZ_UNDEF_S
7532 0U, // UMIN_ZPZZ_UNDEF_B
7533 0U, // UMIN_ZPZZ_UNDEF_D
7534 0U, // UMIN_ZPZZ_UNDEF_H
7535 0U, // UMIN_ZPZZ_UNDEF_S
7536 0U, // UQSHL_ZPZI_ZERO_B
7537 0U, // UQSHL_ZPZI_ZERO_D
7538 0U, // UQSHL_ZPZI_ZERO_H
7539 0U, // UQSHL_ZPZI_ZERO_S
7540 0U, // URSHR_ZPZI_ZERO_B
7541 0U, // URSHR_ZPZI_ZERO_D
7542 0U, // URSHR_ZPZI_ZERO_H
7543 0U, // URSHR_ZPZI_ZERO_S
7544 0U, // ABS_ZPmZ_B
7545 0U, // ABS_ZPmZ_D
7546 0U, // ABS_ZPmZ_H
7547 1U, // ABS_ZPmZ_S
7548 1U, // ABSv16i8
7549 2U, // ABSv1i64
7550 2U, // ABSv2i32
7551 3U, // ABSv2i64
7552 3U, // ABSv4i16
7553 4U, // ABSv4i32
7554 4U, // ABSv8i16
7555 5U, // ABSv8i8
7556 69U, // ADCLB_ZZZ_D
7557 133U, // ADCLB_ZZZ_S
7558 69U, // ADCLT_ZZZ_D
7559 133U, // ADCLT_ZZZ_S
7560 197U, // ADCSWr
7561 197U, // ADCSXr
7562 197U, // ADCWr
7563 197U, // ADCXr
7564 8453U, // ADDG
7565 325U, // ADDHNB_ZZZ_B
7566 6U, // ADDHNB_ZZZ_H
7567 389U, // ADDHNB_ZZZ_S
7568 453U, // ADDHNT_ZZZ_B
7569 1U, // ADDHNT_ZZZ_H
7570 69U, // ADDHNT_ZZZ_S
7571 16902U, // ADDHNv2i64_v2i32
7572 16966U, // ADDHNv2i64_v4i32
7573 25095U, // ADDHNv4i32_v4i16
7574 25159U, // ADDHNv4i32_v8i16
7575 33351U, // ADDHNv8i16_v16i8
7576 33287U, // ADDHNv8i16_v8i8
7577 197U, // ADDPL_XXI
7578 533128U, // ADDP_ZPmZ_B
7579 1057160U, // ADDP_ZPmZ_D
7580 1614536U, // ADDP_ZPmZ_H
7581 2106120U, // ADDP_ZPmZ_S
7582 49673U, // ADDPv16i8
7583 57865U, // ADDPv2i32
7584 16902U, // ADDPv2i64
7585 3U, // ADDPv2i64p
7586 66058U, // ADDPv4i16
7587 25095U, // ADDPv4i32
7588 33287U, // ADDPv8i16
7589 74250U, // ADDPv8i8
7590 837U, // ADDSWri
7591 901U, // ADDSWrs
7592 965U, // ADDSWrx
7593 837U, // ADDSXri
7594 901U, // ADDSXrs
7595 965U, // ADDSXrx
7596 82117U, // ADDSXrx64
7597 197U, // ADDVL_XXI
7598 1U, // ADDVv16i8v
7599 3U, // ADDVv4i16v
7600 4U, // ADDVv4i32v
7601 4U, // ADDVv8i16v
7602 5U, // ADDVv8i8v
7603 837U, // ADDWri
7604 901U, // ADDWrs
7605 965U, // ADDWrx
7606 837U, // ADDXri
7607 901U, // ADDXrs
7608 965U, // ADDXrx
7609 82117U, // ADDXrx64
7610 1029U, // ADD_ZI_B
7611 1093U, // ADD_ZI_D
7612 11U, // ADD_ZI_H
7613 1157U, // ADD_ZI_S
7614 533128U, // ADD_ZPmZ_B
7615 1057160U, // ADD_ZPmZ_D
7616 1614536U, // ADD_ZPmZ_H
7617 2106120U, // ADD_ZPmZ_S
7618 645U, // ADD_ZZZ_B
7619 389U, // ADD_ZZZ_D
7620 8U, // ADD_ZZZ_H
7621 773U, // ADD_ZZZ_S
7622 49673U, // ADDv16i8
7623 197U, // ADDv1i64
7624 57865U, // ADDv2i32
7625 16902U, // ADDv2i64
7626 66058U, // ADDv4i16
7627 25095U, // ADDv4i32
7628 33287U, // ADDv8i16
7629 74250U, // ADDv8i8
7630 2U, // ADR
7631 0U, // ADRP
7632 1221U, // ADR_LSL_ZZZ_D_0
7633 1285U, // ADR_LSL_ZZZ_D_1
7634 1349U, // ADR_LSL_ZZZ_D_2
7635 1413U, // ADR_LSL_ZZZ_D_3
7636 1477U, // ADR_LSL_ZZZ_S_0
7637 1541U, // ADR_LSL_ZZZ_S_1
7638 1605U, // ADR_LSL_ZZZ_S_2
7639 1669U, // ADR_LSL_ZZZ_S_3
7640 1733U, // ADR_SXTW_ZZZ_D_0
7641 1797U, // ADR_SXTW_ZZZ_D_1
7642 1861U, // ADR_SXTW_ZZZ_D_2
7643 1925U, // ADR_SXTW_ZZZ_D_3
7644 1989U, // ADR_UXTW_ZZZ_D_0
7645 2053U, // ADR_UXTW_ZZZ_D_1
7646 2117U, // ADR_UXTW_ZZZ_D_2
7647 2181U, // ADR_UXTW_ZZZ_D_3
7648 645U, // AESD_ZZZ_B
7649 1U, // AESDrr
7650 645U, // AESE_ZZZ_B
7651 1U, // AESErr
7652 2U, // AESIMC_ZZ_B
7653 1U, // AESIMCrr
7654 2U, // AESMC_ZZ_B
7655 1U, // AESMCrr
7656 2245U, // ANDSWri
7657 901U, // ANDSWrs
7658 2309U, // ANDSXri
7659 901U, // ANDSXrs
7660 533131U, // ANDS_PPzPP
7661 0U, // ANDV_VPZ_B
7662 0U, // ANDV_VPZ_D
7663 0U, // ANDV_VPZ_H
7664 0U, // ANDV_VPZ_S
7665 2245U, // ANDWri
7666 901U, // ANDWrs
7667 2309U, // ANDXri
7668 901U, // ANDXrs
7669 533131U, // AND_PPzPP
7670 2309U, // AND_ZI
7671 533128U, // AND_ZPmZ_B
7672 1057160U, // AND_ZPmZ_D
7673 1614536U, // AND_ZPmZ_H
7674 2106120U, // AND_ZPmZ_S
7675 389U, // AND_ZZZ
7676 49673U, // ANDv16i8
7677 74250U, // ANDv8i8
7678 8840U, // ASRD_ZPmI_B
7679 8584U, // ASRD_ZPmI_D
7680 90824U, // ASRD_ZPmI_H
7681 8968U, // ASRD_ZPmI_S
7682 533128U, // ASRR_ZPmZ_B
7683 1057160U, // ASRR_ZPmZ_D
7684 1614536U, // ASRR_ZPmZ_H
7685 2106120U, // ASRR_ZPmZ_S
7686 197U, // ASRVWr
7687 197U, // ASRVXr
7688 1057416U, // ASR_WIDE_ZPmZ_B
7689 99016U, // ASR_WIDE_ZPmZ_H
7690 1057544U, // ASR_WIDE_ZPmZ_S
7691 389U, // ASR_WIDE_ZZZ_B
7692 12U, // ASR_WIDE_ZZZ_H
7693 389U, // ASR_WIDE_ZZZ_S
7694 8840U, // ASR_ZPmI_B
7695 8584U, // ASR_ZPmI_D
7696 90824U, // ASR_ZPmI_H
7697 8968U, // ASR_ZPmI_S
7698 533128U, // ASR_ZPmZ_B
7699 1057160U, // ASR_ZPmZ_D
7700 1614536U, // ASR_ZPmZ_H
7701 2106120U, // ASR_ZPmZ_S
7702 197U, // ASR_ZZI_B
7703 197U, // ASR_ZZI_D
7704 12U, // ASR_ZZI_H
7705 197U, // ASR_ZZI_S
7706 2U, // AUTDA
7707 2U, // AUTDB
7708 0U, // AUTDZA
7709 0U, // AUTDZB
7710 2U, // AUTIA
7711 0U, // AUTIA1716
7712 0U, // AUTIASP
7713 0U, // AUTIAZ
7714 2U, // AUTIB
7715 0U, // AUTIB1716
7716 0U, // AUTIBSP
7717 0U, // AUTIBZ
7718 0U, // AUTIZA
7719 0U, // AUTIZB
7720 0U, // AXFLAG
7721 0U, // B
7722 36282889U, // BCAX
7723 1057157U, // BCAX_ZZZZ
7724 645U, // BDEP_ZZZ_B
7725 389U, // BDEP_ZZZ_D
7726 8U, // BDEP_ZZZ_H
7727 773U, // BDEP_ZZZ_S
7728 645U, // BEXT_ZZZ_B
7729 389U, // BEXT_ZZZ_D
7730 8U, // BEXT_ZZZ_H
7731 773U, // BEXT_ZZZ_S
7732 115274U, // BF16DOTlanev4bf16
7733 115271U, // BF16DOTlanev8bf16
7734 2U, // BFCVT
7735 4U, // BFCVTN
7736 4U, // BFCVTN2
7737 0U, // BFCVTNT_ZPmZ
7738 0U, // BFCVT_ZPmZ
7739 1696197U, // BFDOT_ZZI
7740 453U, // BFDOT_ZZZ
7741 66122U, // BFDOTv4bf16
7742 33351U, // BFDOTv8bf16
7743 33351U, // BFMLALB
7744 3277383U, // BFMLALBIdx
7745 33351U, // BFMLALT
7746 3277383U, // BFMLALTIdx
7747 33351U, // BFMMLA
7748 1696197U, // BFMMLA_B_ZZI
7749 453U, // BFMMLA_B_ZZZ
7750 1696197U, // BFMMLA_T_ZZI
7751 453U, // BFMMLA_T_ZZZ
7752 453U, // BFMMLA_ZZZ
7753 3680581U, // BFMWri
7754 3680581U, // BFMXri
7755 645U, // BGRP_ZZZ_B
7756 389U, // BGRP_ZZZ_D
7757 8U, // BGRP_ZZZ_H
7758 773U, // BGRP_ZZZ_S
7759 901U, // BICSWrs
7760 901U, // BICSXrs
7761 533131U, // BICS_PPzPP
7762 901U, // BICWrs
7763 901U, // BICXrs
7764 533131U, // BIC_PPzPP
7765 533128U, // BIC_ZPmZ_B
7766 1057160U, // BIC_ZPmZ_D
7767 1614536U, // BIC_ZPmZ_H
7768 2106120U, // BIC_ZPmZ_S
7769 389U, // BIC_ZZZ
7770 49673U, // BICv16i8
7771 0U, // BICv2i32
7772 0U, // BICv4i16
7773 0U, // BICv4i32
7774 0U, // BICv8i16
7775 74250U, // BICv8i8
7776 49737U, // BIFv16i8
7777 74314U, // BIFv8i8
7778 49737U, // BITv16i8
7779 74314U, // BITv8i8
7780 0U, // BL
7781 0U, // BLR
7782 2U, // BLRAA
7783 0U, // BLRAAZ
7784 2U, // BLRAB
7785 0U, // BLRABZ
7786 0U, // BR
7787 2U, // BRAA
7788 0U, // BRAAZ
7789 2U, // BRAB
7790 0U, // BRABZ
7791 0U, // BRB_IALL
7792 0U, // BRB_INJ
7793 0U, // BRK
7794 651U, // BRKAS_PPzP
7795 0U, // BRKA_PPmP
7796 651U, // BRKA_PPzP
7797 651U, // BRKBS_PPzP
7798 0U, // BRKB_PPmP
7799 651U, // BRKB_PPzP
7800 533131U, // BRKNS_PPzP
7801 533131U, // BRKN_PPzP
7802 533131U, // BRKPAS_PPzPP
7803 533131U, // BRKPA_PPzPP
7804 533131U, // BRKPBS_PPzPP
7805 533131U, // BRKPB_PPzPP
7806 1057157U, // BSL1N_ZZZZ
7807 1057157U, // BSL2N_ZZZZ
7808 1057157U, // BSL_ZZZZ
7809 49737U, // BSLv16i8
7810 74314U, // BSLv8i8
7811 0U, // Bcc
7812 4203141U, // CADD_ZZI_B
7813 4202885U, // CADD_ZZI_D
7814 139976U, // CADD_ZZI_H
7815 4203269U, // CADD_ZZI_S
7816 149837U, // CASAB
7817 149837U, // CASAH
7818 149837U, // CASALB
7819 149837U, // CASALH
7820 149837U, // CASALW
7821 149837U, // CASALX
7822 149837U, // CASAW
7823 149837U, // CASAX
7824 149837U, // CASB
7825 149837U, // CASH
7826 149837U, // CASLB
7827 149837U, // CASLH
7828 149837U, // CASLW
7829 149837U, // CASLX
7830 0U, // CASPALW
7831 0U, // CASPALX
7832 0U, // CASPAW
7833 0U, // CASPAX
7834 0U, // CASPLW
7835 0U, // CASPLX
7836 0U, // CASPW
7837 0U, // CASPX
7838 149837U, // CASW
7839 149837U, // CASX
7840 0U, // CBNZW
7841 0U, // CBNZX
7842 0U, // CBZW
7843 0U, // CBZX
7844 4726981U, // CCMNWi
7845 4726981U, // CCMNWr
7846 4726981U, // CCMNXi
7847 4726981U, // CCMNXr
7848 4726981U, // CCMPWi
7849 4726981U, // CCMPWr
7850 4726981U, // CCMPXi
7851 4726981U, // CCMPXr
7852 72475077U, // CDOT_ZZZI_D
7853 5777792U, // CDOT_ZZZI_S
7854 6300101U, // CDOT_ZZZ_D
7855 156352U, // CDOT_ZZZ_S
7856 0U, // CFINV
7857 532677U, // CLASTA_RPZ_B
7858 1056965U, // CLASTA_RPZ_D
7859 6824133U, // CLASTA_RPZ_H
7860 2105541U, // CLASTA_RPZ_S
7861 532677U, // CLASTA_VPZ_B
7862 1056965U, // CLASTA_VPZ_D
7863 6824133U, // CLASTA_VPZ_H
7864 2105541U, // CLASTA_VPZ_S
7865 533125U, // CLASTA_ZPZ_B
7866 1057157U, // CLASTA_ZPZ_D
7867 1614536U, // CLASTA_ZPZ_H
7868 2106117U, // CLASTA_ZPZ_S
7869 532677U, // CLASTB_RPZ_B
7870 1056965U, // CLASTB_RPZ_D
7871 6824133U, // CLASTB_RPZ_H
7872 2105541U, // CLASTB_RPZ_S
7873 532677U, // CLASTB_VPZ_B
7874 1056965U, // CLASTB_VPZ_D
7875 6824133U, // CLASTB_VPZ_H
7876 2105541U, // CLASTB_VPZ_S
7877 533125U, // CLASTB_ZPZ_B
7878 1057157U, // CLASTB_ZPZ_D
7879 1614536U, // CLASTB_ZPZ_H
7880 2106117U, // CLASTB_ZPZ_S
7881 0U, // CLREX
7882 2U, // CLSWr
7883 2U, // CLSXr
7884 0U, // CLS_ZPmZ_B
7885 0U, // CLS_ZPmZ_D
7886 0U, // CLS_ZPmZ_H
7887 1U, // CLS_ZPmZ_S
7888 1U, // CLSv16i8
7889 2U, // CLSv2i32
7890 3U, // CLSv4i16
7891 4U, // CLSv4i32
7892 4U, // CLSv8i16
7893 5U, // CLSv8i8
7894 2U, // CLZWr
7895 2U, // CLZXr
7896 0U, // CLZ_ZPmZ_B
7897 0U, // CLZ_ZPmZ_D
7898 0U, // CLZ_ZPmZ_H
7899 1U, // CLZ_ZPmZ_S
7900 1U, // CLZv16i8
7901 2U, // CLZv2i32
7902 3U, // CLZv4i16
7903 4U, // CLZv4i32
7904 4U, // CLZv8i16
7905 5U, // CLZv8i8
7906 49673U, // CMEQv16i8
7907 13U, // CMEQv16i8rz
7908 197U, // CMEQv1i64
7909 14U, // CMEQv1i64rz
7910 57865U, // CMEQv2i32
7911 14U, // CMEQv2i32rz
7912 16902U, // CMEQv2i64
7913 15U, // CMEQv2i64rz
7914 66058U, // CMEQv4i16
7915 15U, // CMEQv4i16rz
7916 25095U, // CMEQv4i32
7917 16U, // CMEQv4i32rz
7918 33287U, // CMEQv8i16
7919 16U, // CMEQv8i16rz
7920 74250U, // CMEQv8i8
7921 17U, // CMEQv8i8rz
7922 49673U, // CMGEv16i8
7923 13U, // CMGEv16i8rz
7924 197U, // CMGEv1i64
7925 14U, // CMGEv1i64rz
7926 57865U, // CMGEv2i32
7927 14U, // CMGEv2i32rz
7928 16902U, // CMGEv2i64
7929 15U, // CMGEv2i64rz
7930 66058U, // CMGEv4i16
7931 15U, // CMGEv4i16rz
7932 25095U, // CMGEv4i32
7933 16U, // CMGEv4i32rz
7934 33287U, // CMGEv8i16
7935 16U, // CMGEv8i16rz
7936 74250U, // CMGEv8i8
7937 17U, // CMGEv8i8rz
7938 49673U, // CMGTv16i8
7939 13U, // CMGTv16i8rz
7940 197U, // CMGTv1i64
7941 14U, // CMGTv1i64rz
7942 57865U, // CMGTv2i32
7943 14U, // CMGTv2i32rz
7944 16902U, // CMGTv2i64
7945 15U, // CMGTv2i64rz
7946 66058U, // CMGTv4i16
7947 15U, // CMGTv4i16rz
7948 25095U, // CMGTv4i32
7949 16U, // CMGTv4i32rz
7950 33287U, // CMGTv8i16
7951 16U, // CMGTv8i16rz
7952 74250U, // CMGTv8i8
7953 17U, // CMGTv8i8rz
7954 49673U, // CMHIv16i8
7955 197U, // CMHIv1i64
7956 57865U, // CMHIv2i32
7957 16902U, // CMHIv2i64
7958 66058U, // CMHIv4i16
7959 25095U, // CMHIv4i32
7960 33287U, // CMHIv8i16
7961 74250U, // CMHIv8i8
7962 49673U, // CMHSv16i8
7963 197U, // CMHSv1i64
7964 57865U, // CMHSv2i32
7965 16902U, // CMHSv2i64
7966 66058U, // CMHSv4i16
7967 25095U, // CMHSv4i32
7968 33287U, // CMHSv8i16
7969 74250U, // CMHSv8i8
7970 5777809U, // CMLA_ZZZI_H
7971 72474757U, // CMLA_ZZZI_S
7972 156352U, // CMLA_ZZZ_B
7973 6299717U, // CMLA_ZZZ_D
7974 156369U, // CMLA_ZZZ_H
7975 6299781U, // CMLA_ZZZ_S
7976 13U, // CMLEv16i8rz
7977 14U, // CMLEv1i64rz
7978 14U, // CMLEv2i32rz
7979 15U, // CMLEv2i64rz
7980 15U, // CMLEv4i16rz
7981 16U, // CMLEv4i32rz
7982 16U, // CMLEv8i16rz
7983 17U, // CMLEv8i8rz
7984 13U, // CMLTv16i8rz
7985 14U, // CMLTv1i64rz
7986 14U, // CMLTv2i32rz
7987 15U, // CMLTv2i64rz
7988 15U, // CMLTv4i16rz
7989 16U, // CMLTv4i32rz
7990 16U, // CMLTv8i16rz
7991 17U, // CMLTv8i8rz
7992 8843U, // CMPEQ_PPzZI_B
7993 8587U, // CMPEQ_PPzZI_D
7994 90824U, // CMPEQ_PPzZI_H
7995 8971U, // CMPEQ_PPzZI_S
7996 533131U, // CMPEQ_PPzZZ_B
7997 1057163U, // CMPEQ_PPzZZ_D
7998 1614536U, // CMPEQ_PPzZZ_H
7999 2106123U, // CMPEQ_PPzZZ_S
8000 1057419U, // CMPEQ_WIDE_PPzZZ_B
8001 99016U, // CMPEQ_WIDE_PPzZZ_H
8002 1057547U, // CMPEQ_WIDE_PPzZZ_S
8003 8843U, // CMPGE_PPzZI_B
8004 8587U, // CMPGE_PPzZI_D
8005 90824U, // CMPGE_PPzZI_H
8006 8971U, // CMPGE_PPzZI_S
8007 533131U, // CMPGE_PPzZZ_B
8008 1057163U, // CMPGE_PPzZZ_D
8009 1614536U, // CMPGE_PPzZZ_H
8010 2106123U, // CMPGE_PPzZZ_S
8011 1057419U, // CMPGE_WIDE_PPzZZ_B
8012 99016U, // CMPGE_WIDE_PPzZZ_H
8013 1057547U, // CMPGE_WIDE_PPzZZ_S
8014 8843U, // CMPGT_PPzZI_B
8015 8587U, // CMPGT_PPzZI_D
8016 90824U, // CMPGT_PPzZI_H
8017 8971U, // CMPGT_PPzZI_S
8018 533131U, // CMPGT_PPzZZ_B
8019 1057163U, // CMPGT_PPzZZ_D
8020 1614536U, // CMPGT_PPzZZ_H
8021 2106123U, // CMPGT_PPzZZ_S
8022 1057419U, // CMPGT_WIDE_PPzZZ_B
8023 99016U, // CMPGT_WIDE_PPzZZ_H
8024 1057547U, // CMPGT_WIDE_PPzZZ_S
8025 7348875U, // CMPHI_PPzZI_B
8026 7348619U, // CMPHI_PPzZI_D
8027 164552U, // CMPHI_PPzZI_H
8028 7349003U, // CMPHI_PPzZI_S
8029 533131U, // CMPHI_PPzZZ_B
8030 1057163U, // CMPHI_PPzZZ_D
8031 1614536U, // CMPHI_PPzZZ_H
8032 2106123U, // CMPHI_PPzZZ_S
8033 1057419U, // CMPHI_WIDE_PPzZZ_B
8034 99016U, // CMPHI_WIDE_PPzZZ_H
8035 1057547U, // CMPHI_WIDE_PPzZZ_S
8036 7348875U, // CMPHS_PPzZI_B
8037 7348619U, // CMPHS_PPzZI_D
8038 164552U, // CMPHS_PPzZI_H
8039 7349003U, // CMPHS_PPzZI_S
8040 533131U, // CMPHS_PPzZZ_B
8041 1057163U, // CMPHS_PPzZZ_D
8042 1614536U, // CMPHS_PPzZZ_H
8043 2106123U, // CMPHS_PPzZZ_S
8044 1057419U, // CMPHS_WIDE_PPzZZ_B
8045 99016U, // CMPHS_WIDE_PPzZZ_H
8046 1057547U, // CMPHS_WIDE_PPzZZ_S
8047 8843U, // CMPLE_PPzZI_B
8048 8587U, // CMPLE_PPzZI_D
8049 90824U, // CMPLE_PPzZI_H
8050 8971U, // CMPLE_PPzZI_S
8051 1057419U, // CMPLE_WIDE_PPzZZ_B
8052 99016U, // CMPLE_WIDE_PPzZZ_H
8053 1057547U, // CMPLE_WIDE_PPzZZ_S
8054 7348875U, // CMPLO_PPzZI_B
8055 7348619U, // CMPLO_PPzZI_D
8056 164552U, // CMPLO_PPzZI_H
8057 7349003U, // CMPLO_PPzZI_S
8058 1057419U, // CMPLO_WIDE_PPzZZ_B
8059 99016U, // CMPLO_WIDE_PPzZZ_H
8060 1057547U, // CMPLO_WIDE_PPzZZ_S
8061 7348875U, // CMPLS_PPzZI_B
8062 7348619U, // CMPLS_PPzZI_D
8063 164552U, // CMPLS_PPzZI_H
8064 7349003U, // CMPLS_PPzZI_S
8065 1057419U, // CMPLS_WIDE_PPzZZ_B
8066 99016U, // CMPLS_WIDE_PPzZZ_H
8067 1057547U, // CMPLS_WIDE_PPzZZ_S
8068 8843U, // CMPLT_PPzZI_B
8069 8587U, // CMPLT_PPzZI_D
8070 90824U, // CMPLT_PPzZI_H
8071 8971U, // CMPLT_PPzZI_S
8072 1057419U, // CMPLT_WIDE_PPzZZ_B
8073 99016U, // CMPLT_WIDE_PPzZZ_H
8074 1057547U, // CMPLT_WIDE_PPzZZ_S
8075 8843U, // CMPNE_PPzZI_B
8076 8587U, // CMPNE_PPzZI_D
8077 90824U, // CMPNE_PPzZI_H
8078 8971U, // CMPNE_PPzZI_S
8079 533131U, // CMPNE_PPzZZ_B
8080 1057163U, // CMPNE_PPzZZ_D
8081 1614536U, // CMPNE_PPzZZ_H
8082 2106123U, // CMPNE_PPzZZ_S
8083 1057419U, // CMPNE_WIDE_PPzZZ_B
8084 99016U, // CMPNE_WIDE_PPzZZ_H
8085 1057547U, // CMPNE_WIDE_PPzZZ_S
8086 49673U, // CMTSTv16i8
8087 197U, // CMTSTv1i64
8088 57865U, // CMTSTv2i32
8089 16902U, // CMTSTv2i64
8090 66058U, // CMTSTv4i16
8091 25095U, // CMTSTv4i32
8092 33287U, // CMTSTv8i16
8093 74250U, // CMTSTv8i8
8094 0U, // CNOT_ZPmZ_B
8095 0U, // CNOT_ZPmZ_D
8096 0U, // CNOT_ZPmZ_H
8097 1U, // CNOT_ZPmZ_S
8098 18U, // CNTB_XPiI
8099 18U, // CNTD_XPiI
8100 18U, // CNTH_XPiI
8101 645U, // CNTP_XPP_B
8102 389U, // CNTP_XPP_D
8103 325U, // CNTP_XPP_H
8104 773U, // CNTP_XPP_S
8105 18U, // CNTW_XPiI
8106 0U, // CNT_ZPmZ_B
8107 0U, // CNT_ZPmZ_D
8108 0U, // CNT_ZPmZ_H
8109 1U, // CNT_ZPmZ_S
8110 1U, // CNTv16i8
8111 5U, // CNTv8i8
8112 389U, // COMPACT_ZPZ_D
8113 773U, // COMPACT_ZPZ_S
8114 18U, // CPY_ZPmI_B
8115 19U, // CPY_ZPmI_D
8116 0U, // CPY_ZPmI_H
8117 19U, // CPY_ZPmI_S
8118 20U, // CPY_ZPmR_B
8119 20U, // CPY_ZPmR_D
8120 0U, // CPY_ZPmR_H
8121 20U, // CPY_ZPmR_S
8122 20U, // CPY_ZPmV_B
8123 20U, // CPY_ZPmV_D
8124 0U, // CPY_ZPmV_H
8125 20U, // CPY_ZPmV_S
8126 2507U, // CPY_ZPzI_B
8127 2571U, // CPY_ZPzI_D
8128 20U, // CPY_ZPzI_H
8129 2635U, // CPY_ZPzI_S
8130 2709U, // CPYi16
8131 2709U, // CPYi32
8132 2710U, // CPYi64
8133 2710U, // CPYi8
8134 197U, // CRC32Brr
8135 197U, // CRC32CBrr
8136 197U, // CRC32CHrr
8137 197U, // CRC32CWrr
8138 197U, // CRC32CXrr
8139 197U, // CRC32Hrr
8140 197U, // CRC32Wrr
8141 197U, // CRC32Xrr
8142 4726981U, // CSELWr
8143 4726981U, // CSELXr
8144 4726981U, // CSINCWr
8145 4726981U, // CSINCXr
8146 4726981U, // CSINVWr
8147 4726981U, // CSINVXr
8148 4726981U, // CSNEGWr
8149 4726981U, // CSNEGXr
8150 2U, // CTERMEQ_WW
8151 2U, // CTERMEQ_XX
8152 2U, // CTERMNE_WW
8153 2U, // CTERMNE_XX
8154 0U, // DCPS1
8155 0U, // DCPS2
8156 0U, // DCPS3
8157 0U, // DECB_XPiI
8158 0U, // DECD_XPiI
8159 0U, // DECD_ZPiI
8160 0U, // DECH_XPiI
8161 0U, // DECH_ZPiI
8162 2U, // DECP_XP_B
8163 2U, // DECP_XP_D
8164 2U, // DECP_XP_H
8165 2U, // DECP_XP_S
8166 2U, // DECP_ZP_D
8167 0U, // DECP_ZP_H
8168 2U, // DECP_ZP_S
8169 0U, // DECW_XPiI
8170 0U, // DECW_ZPiI
8171 0U, // DMB
8172 0U, // DRPS
8173 0U, // DSB
8174 0U, // DSBnXS
8175 0U, // DUPM_ZI
8176 0U, // DUP_ZI_B
8177 0U, // DUP_ZI_D
8178 0U, // DUP_ZI_H
8179 0U, // DUP_ZI_S
8180 2U, // DUP_ZR_B
8181 2U, // DUP_ZR_D
8182 0U, // DUP_ZR_H
8183 2U, // DUP_ZR_S
8184 23U, // DUP_ZZI_B
8185 23U, // DUP_ZZI_D
8186 0U, // DUP_ZZI_H
8187 0U, // DUP_ZZI_Q
8188 23U, // DUP_ZZI_S
8189 2U, // DUPv16i8gpr
8190 2710U, // DUPv16i8lane
8191 2U, // DUPv2i32gpr
8192 2709U, // DUPv2i32lane
8193 2U, // DUPv2i64gpr
8194 2710U, // DUPv2i64lane
8195 2U, // DUPv4i16gpr
8196 2709U, // DUPv4i16lane
8197 2U, // DUPv4i32gpr
8198 2709U, // DUPv4i32lane
8199 2U, // DUPv8i16gpr
8200 2709U, // DUPv8i16lane
8201 2U, // DUPv8i8gpr
8202 2710U, // DUPv8i8lane
8203 901U, // EONWrs
8204 901U, // EONXrs
8205 36282889U, // EOR3
8206 1057157U, // EOR3_ZZZZ
8207 0U, // EORBT_ZZZ_B
8208 69U, // EORBT_ZZZ_D
8209 17U, // EORBT_ZZZ_H
8210 133U, // EORBT_ZZZ_S
8211 533131U, // EORS_PPzPP
8212 0U, // EORTB_ZZZ_B
8213 69U, // EORTB_ZZZ_D
8214 17U, // EORTB_ZZZ_H
8215 133U, // EORTB_ZZZ_S
8216 0U, // EORV_VPZ_B
8217 0U, // EORV_VPZ_D
8218 0U, // EORV_VPZ_H
8219 0U, // EORV_VPZ_S
8220 2245U, // EORWri
8221 901U, // EORWrs
8222 2309U, // EORXri
8223 901U, // EORXrs
8224 533131U, // EOR_PPzPP
8225 2309U, // EOR_ZI
8226 533128U, // EOR_ZPmZ_B
8227 1057160U, // EOR_ZPmZ_D
8228 1614536U, // EOR_ZPmZ_H
8229 2106120U, // EOR_ZPmZ_S
8230 389U, // EOR_ZZZ
8231 49673U, // EORv16i8
8232 74250U, // EORv8i8
8233 0U, // ERET
8234 0U, // ERETAA
8235 0U, // ERETAB
8236 8389U, // EXTRWrri
8237 8389U, // EXTRXrri
8238 7348869U, // EXT_ZZI
8239 23U, // EXT_ZZI_B
8240 107017U, // EXTv16i8
8241 172554U, // EXTv8i8
8242 197U, // FABD16
8243 197U, // FABD32
8244 197U, // FABD64
8245 1057160U, // FABD_ZPmZ_D
8246 1614536U, // FABD_ZPmZ_H
8247 2106120U, // FABD_ZPmZ_S
8248 57865U, // FABDv2f32
8249 16902U, // FABDv2f64
8250 66058U, // FABDv4f16
8251 25095U, // FABDv4f32
8252 33287U, // FABDv8f16
8253 2U, // FABSDr
8254 2U, // FABSHr
8255 2U, // FABSSr
8256 0U, // FABS_ZPmZ_D
8257 0U, // FABS_ZPmZ_H
8258 1U, // FABS_ZPmZ_S
8259 2U, // FABSv2f32
8260 3U, // FABSv2f64
8261 3U, // FABSv4f16
8262 4U, // FABSv4f32
8263 4U, // FABSv8f16
8264 197U, // FACGE16
8265 197U, // FACGE32
8266 197U, // FACGE64
8267 1057163U, // FACGE_PPzZZ_D
8268 1614536U, // FACGE_PPzZZ_H
8269 2106123U, // FACGE_PPzZZ_S
8270 57865U, // FACGEv2f32
8271 16902U, // FACGEv2f64
8272 66058U, // FACGEv4f16
8273 25095U, // FACGEv4f32
8274 33287U, // FACGEv8f16
8275 197U, // FACGT16
8276 197U, // FACGT32
8277 197U, // FACGT64
8278 1057163U, // FACGT_PPzZZ_D
8279 1614536U, // FACGT_PPzZZ_H
8280 2106123U, // FACGT_PPzZZ_S
8281 57865U, // FACGTv2f32
8282 16902U, // FACGTv2f64
8283 66058U, // FACGTv4f16
8284 25095U, // FACGTv4f32
8285 33287U, // FACGTv8f16
8286 0U, // FADDA_VPZ_D
8287 0U, // FADDA_VPZ_H
8288 0U, // FADDA_VPZ_S
8289 197U, // FADDDrr
8290 197U, // FADDHrr
8291 1057160U, // FADDP_ZPmZZ_D
8292 1614536U, // FADDP_ZPmZZ_H
8293 2106120U, // FADDP_ZPmZZ_S
8294 57865U, // FADDPv2f32
8295 16902U, // FADDPv2f64
8296 24U, // FADDPv2i16p
8297 2U, // FADDPv2i32p
8298 3U, // FADDPv2i64p
8299 66058U, // FADDPv4f16
8300 25095U, // FADDPv4f32
8301 33287U, // FADDPv8f16
8302 197U, // FADDSrr
8303 0U, // FADDV_VPZ_D
8304 0U, // FADDV_VPZ_H
8305 0U, // FADDV_VPZ_S
8306 7872904U, // FADD_ZPmI_D
8307 180936U, // FADD_ZPmI_H
8308 7873288U, // FADD_ZPmI_S
8309 1057160U, // FADD_ZPmZ_D
8310 1614536U, // FADD_ZPmZ_H
8311 2106120U, // FADD_ZPmZ_S
8312 389U, // FADD_ZZZ_D
8313 8U, // FADD_ZZZ_H
8314 773U, // FADD_ZZZ_S
8315 57865U, // FADDv2f32
8316 16902U, // FADDv2f64
8317 66058U, // FADDv4f16
8318 25095U, // FADDv4f32
8319 33287U, // FADDv8f16
8320 101720456U, // FCADD_ZPmZ_D
8321 139502280U, // FCADD_ZPmZ_H
8322 102769416U, // FCADD_ZPmZ_S
8323 4383241U, // FCADDv2f32
8324 4391430U, // FCADDv2f64
8325 4399626U, // FCADDv4f16
8326 4407815U, // FCADDv4f32
8327 4416007U, // FCADDv8f16
8328 4726981U, // FCCMPDrr
8329 4726981U, // FCCMPEDrr
8330 4726981U, // FCCMPEHrr
8331 4726981U, // FCCMPESrr
8332 4726981U, // FCCMPHrr
8333 4726981U, // FCCMPSrr
8334 197U, // FCMEQ16
8335 197U, // FCMEQ32
8336 197U, // FCMEQ64
8337 229771U, // FCMEQ_PPzZ0_D
8338 2760U, // FCMEQ_PPzZ0_H
8339 230155U, // FCMEQ_PPzZ0_S
8340 1057163U, // FCMEQ_PPzZZ_D
8341 1614536U, // FCMEQ_PPzZZ_H
8342 2106123U, // FCMEQ_PPzZZ_S
8343 24U, // FCMEQv1i16rz
8344 24U, // FCMEQv1i32rz
8345 24U, // FCMEQv1i64rz
8346 57865U, // FCMEQv2f32
8347 16902U, // FCMEQv2f64
8348 25U, // FCMEQv2i32rz
8349 25U, // FCMEQv2i64rz
8350 66058U, // FCMEQv4f16
8351 25095U, // FCMEQv4f32
8352 26U, // FCMEQv4i16rz
8353 26U, // FCMEQv4i32rz
8354 33287U, // FCMEQv8f16
8355 27U, // FCMEQv8i16rz
8356 197U, // FCMGE16
8357 197U, // FCMGE32
8358 197U, // FCMGE64
8359 229771U, // FCMGE_PPzZ0_D
8360 2760U, // FCMGE_PPzZ0_H
8361 230155U, // FCMGE_PPzZ0_S
8362 1057163U, // FCMGE_PPzZZ_D
8363 1614536U, // FCMGE_PPzZZ_H
8364 2106123U, // FCMGE_PPzZZ_S
8365 24U, // FCMGEv1i16rz
8366 24U, // FCMGEv1i32rz
8367 24U, // FCMGEv1i64rz
8368 57865U, // FCMGEv2f32
8369 16902U, // FCMGEv2f64
8370 25U, // FCMGEv2i32rz
8371 25U, // FCMGEv2i64rz
8372 66058U, // FCMGEv4f16
8373 25095U, // FCMGEv4f32
8374 26U, // FCMGEv4i16rz
8375 26U, // FCMGEv4i32rz
8376 33287U, // FCMGEv8f16
8377 27U, // FCMGEv8i16rz
8378 197U, // FCMGT16
8379 197U, // FCMGT32
8380 197U, // FCMGT64
8381 229771U, // FCMGT_PPzZ0_D
8382 2760U, // FCMGT_PPzZ0_H
8383 230155U, // FCMGT_PPzZ0_S
8384 1057163U, // FCMGT_PPzZZ_D
8385 1614536U, // FCMGT_PPzZZ_H
8386 2106123U, // FCMGT_PPzZZ_S
8387 24U, // FCMGTv1i16rz
8388 24U, // FCMGTv1i32rz
8389 24U, // FCMGTv1i64rz
8390 57865U, // FCMGTv2f32
8391 16902U, // FCMGTv2f64
8392 25U, // FCMGTv2i32rz
8393 25U, // FCMGTv2i64rz
8394 66058U, // FCMGTv4f16
8395 25095U, // FCMGTv4f32
8396 26U, // FCMGTv4i16rz
8397 26U, // FCMGTv4i32rz
8398 33287U, // FCMGTv8f16
8399 27U, // FCMGTv8i16rz
8400 377495624U, // FCMLA_ZPmZZ_D
8401 72590033U, // FCMLA_ZPmZZ_H
8402 378019976U, // FCMLA_ZPmZZ_S
8403 5777809U, // FCMLA_ZZZI_H
8404 72474757U, // FCMLA_ZZZI_S
8405 6480457U, // FCMLAv2f32
8406 6488646U, // FCMLAv2f64
8407 6496842U, // FCMLAv4f16
8408 372376138U, // FCMLAv4f16_indexed
8409 6505031U, // FCMLAv4f32
8410 372490823U, // FCMLAv4f32_indexed
8411 6513223U, // FCMLAv8f16
8412 372376135U, // FCMLAv8f16_indexed
8413 229771U, // FCMLE_PPzZ0_D
8414 2760U, // FCMLE_PPzZ0_H
8415 230155U, // FCMLE_PPzZ0_S
8416 24U, // FCMLEv1i16rz
8417 24U, // FCMLEv1i32rz
8418 24U, // FCMLEv1i64rz
8419 25U, // FCMLEv2i32rz
8420 25U, // FCMLEv2i64rz
8421 26U, // FCMLEv4i16rz
8422 26U, // FCMLEv4i32rz
8423 27U, // FCMLEv8i16rz
8424 229771U, // FCMLT_PPzZ0_D
8425 2760U, // FCMLT_PPzZ0_H
8426 230155U, // FCMLT_PPzZ0_S
8427 24U, // FCMLTv1i16rz
8428 24U, // FCMLTv1i32rz
8429 24U, // FCMLTv1i64rz
8430 25U, // FCMLTv2i32rz
8431 25U, // FCMLTv2i64rz
8432 26U, // FCMLTv4i16rz
8433 26U, // FCMLTv4i32rz
8434 27U, // FCMLTv8i16rz
8435 229771U, // FCMNE_PPzZ0_D
8436 2760U, // FCMNE_PPzZ0_H
8437 230155U, // FCMNE_PPzZ0_S
8438 1057163U, // FCMNE_PPzZZ_D
8439 1614536U, // FCMNE_PPzZZ_H
8440 2106123U, // FCMNE_PPzZZ_S
8441 0U, // FCMPDri
8442 2U, // FCMPDrr
8443 0U, // FCMPEDri
8444 2U, // FCMPEDrr
8445 0U, // FCMPEHri
8446 2U, // FCMPEHrr
8447 0U, // FCMPESri
8448 2U, // FCMPESrr
8449 0U, // FCMPHri
8450 2U, // FCMPHrr
8451 0U, // FCMPSri
8452 2U, // FCMPSrr
8453 1057163U, // FCMUO_PPzZZ_D
8454 1614536U, // FCMUO_PPzZZ_H
8455 2106123U, // FCMUO_PPzZZ_S
8456 27U, // FCPY_ZPmI_D
8457 0U, // FCPY_ZPmI_H
8458 27U, // FCPY_ZPmI_S
8459 4726981U, // FCSELDrrr
8460 4726981U, // FCSELHrrr
8461 4726981U, // FCSELSrrr
8462 2U, // FCVTASUWDr
8463 2U, // FCVTASUWHr
8464 2U, // FCVTASUWSr
8465 2U, // FCVTASUXDr
8466 2U, // FCVTASUXHr
8467 2U, // FCVTASUXSr
8468 2U, // FCVTASv1f16
8469 2U, // FCVTASv1i32
8470 2U, // FCVTASv1i64
8471 2U, // FCVTASv2f32
8472 3U, // FCVTASv2f64
8473 3U, // FCVTASv4f16
8474 4U, // FCVTASv4f32
8475 4U, // FCVTASv8f16
8476 2U, // FCVTAUUWDr
8477 2U, // FCVTAUUWHr
8478 2U, // FCVTAUUWSr
8479 2U, // FCVTAUUXDr
8480 2U, // FCVTAUUXHr
8481 2U, // FCVTAUUXSr
8482 2U, // FCVTAUv1f16
8483 2U, // FCVTAUv1i32
8484 2U, // FCVTAUv1i64
8485 2U, // FCVTAUv2f32
8486 3U, // FCVTAUv2f64
8487 3U, // FCVTAUv4f16
8488 4U, // FCVTAUv4f32
8489 4U, // FCVTAUv8f16
8490 2U, // FCVTDHr
8491 2U, // FCVTDSr
8492 2U, // FCVTHDr
8493 2U, // FCVTHSr
8494 17U, // FCVTLT_ZPmZ_HtoS
8495 1U, // FCVTLT_ZPmZ_StoD
8496 2U, // FCVTLv2i32
8497 3U, // FCVTLv4i16
8498 4U, // FCVTLv4i32
8499 4U, // FCVTLv8i16
8500 2U, // FCVTMSUWDr
8501 2U, // FCVTMSUWHr
8502 2U, // FCVTMSUWSr
8503 2U, // FCVTMSUXDr
8504 2U, // FCVTMSUXHr
8505 2U, // FCVTMSUXSr
8506 2U, // FCVTMSv1f16
8507 2U, // FCVTMSv1i32
8508 2U, // FCVTMSv1i64
8509 2U, // FCVTMSv2f32
8510 3U, // FCVTMSv2f64
8511 3U, // FCVTMSv4f16
8512 4U, // FCVTMSv4f32
8513 4U, // FCVTMSv8f16
8514 2U, // FCVTMUUWDr
8515 2U, // FCVTMUUWHr
8516 2U, // FCVTMUUWSr
8517 2U, // FCVTMUUXDr
8518 2U, // FCVTMUUXHr
8519 2U, // FCVTMUUXSr
8520 2U, // FCVTMUv1f16
8521 2U, // FCVTMUv1i32
8522 2U, // FCVTMUv1i64
8523 2U, // FCVTMUv2f32
8524 3U, // FCVTMUv2f64
8525 3U, // FCVTMUv4f16
8526 4U, // FCVTMUv4f32
8527 4U, // FCVTMUv8f16
8528 2U, // FCVTNSUWDr
8529 2U, // FCVTNSUWHr
8530 2U, // FCVTNSUWSr
8531 2U, // FCVTNSUXDr
8532 2U, // FCVTNSUXHr
8533 2U, // FCVTNSUXSr
8534 2U, // FCVTNSv1f16
8535 2U, // FCVTNSv1i32
8536 2U, // FCVTNSv1i64
8537 2U, // FCVTNSv2f32
8538 3U, // FCVTNSv2f64
8539 3U, // FCVTNSv4f16
8540 4U, // FCVTNSv4f32
8541 4U, // FCVTNSv8f16
8542 0U, // FCVTNT_ZPmZ_DtoS
8543 0U, // FCVTNT_ZPmZ_StoH
8544 2U, // FCVTNUUWDr
8545 2U, // FCVTNUUWHr
8546 2U, // FCVTNUUWSr
8547 2U, // FCVTNUUXDr
8548 2U, // FCVTNUUXHr
8549 2U, // FCVTNUUXSr
8550 2U, // FCVTNUv1f16
8551 2U, // FCVTNUv1i32
8552 2U, // FCVTNUv1i64
8553 2U, // FCVTNUv2f32
8554 3U, // FCVTNUv2f64
8555 3U, // FCVTNUv4f16
8556 4U, // FCVTNUv4f32
8557 4U, // FCVTNUv8f16
8558 3U, // FCVTNv2i32
8559 4U, // FCVTNv4i16
8560 3U, // FCVTNv4i32
8561 4U, // FCVTNv8i16
8562 2U, // FCVTPSUWDr
8563 2U, // FCVTPSUWHr
8564 2U, // FCVTPSUWSr
8565 2U, // FCVTPSUXDr
8566 2U, // FCVTPSUXHr
8567 2U, // FCVTPSUXSr
8568 2U, // FCVTPSv1f16
8569 2U, // FCVTPSv1i32
8570 2U, // FCVTPSv1i64
8571 2U, // FCVTPSv2f32
8572 3U, // FCVTPSv2f64
8573 3U, // FCVTPSv4f16
8574 4U, // FCVTPSv4f32
8575 4U, // FCVTPSv8f16
8576 2U, // FCVTPUUWDr
8577 2U, // FCVTPUUWHr
8578 2U, // FCVTPUUWSr
8579 2U, // FCVTPUUXDr
8580 2U, // FCVTPUUXHr
8581 2U, // FCVTPUUXSr
8582 2U, // FCVTPUv1f16
8583 2U, // FCVTPUv1i32
8584 2U, // FCVTPUv1i64
8585 2U, // FCVTPUv2f32
8586 3U, // FCVTPUv2f64
8587 3U, // FCVTPUv4f16
8588 4U, // FCVTPUv4f32
8589 4U, // FCVTPUv8f16
8590 2U, // FCVTSDr
8591 2U, // FCVTSHr
8592 0U, // FCVTXNT_ZPmZ_DtoS
8593 2U, // FCVTXNv1i64
8594 3U, // FCVTXNv2f32
8595 3U, // FCVTXNv4f32
8596 0U, // FCVTX_ZPmZ_DtoS
8597 197U, // FCVTZSSWDri
8598 197U, // FCVTZSSWHri
8599 197U, // FCVTZSSWSri
8600 197U, // FCVTZSSXDri
8601 197U, // FCVTZSSXHri
8602 197U, // FCVTZSSXSri
8603 2U, // FCVTZSUWDr
8604 2U, // FCVTZSUWHr
8605 2U, // FCVTZSUWSr
8606 2U, // FCVTZSUXDr
8607 2U, // FCVTZSUXHr
8608 2U, // FCVTZSUXSr
8609 0U, // FCVTZS_ZPmZ_DtoD
8610 0U, // FCVTZS_ZPmZ_DtoS
8611 17U, // FCVTZS_ZPmZ_HtoD
8612 0U, // FCVTZS_ZPmZ_HtoH
8613 17U, // FCVTZS_ZPmZ_HtoS
8614 1U, // FCVTZS_ZPmZ_StoD
8615 1U, // FCVTZS_ZPmZ_StoS
8616 197U, // FCVTZSd
8617 197U, // FCVTZSh
8618 197U, // FCVTZSs
8619 2U, // FCVTZSv1f16
8620 2U, // FCVTZSv1i32
8621 2U, // FCVTZSv1i64
8622 2U, // FCVTZSv2f32
8623 3U, // FCVTZSv2f64
8624 201U, // FCVTZSv2i32_shift
8625 198U, // FCVTZSv2i64_shift
8626 3U, // FCVTZSv4f16
8627 4U, // FCVTZSv4f32
8628 202U, // FCVTZSv4i16_shift
8629 199U, // FCVTZSv4i32_shift
8630 4U, // FCVTZSv8f16
8631 199U, // FCVTZSv8i16_shift
8632 197U, // FCVTZUSWDri
8633 197U, // FCVTZUSWHri
8634 197U, // FCVTZUSWSri
8635 197U, // FCVTZUSXDri
8636 197U, // FCVTZUSXHri
8637 197U, // FCVTZUSXSri
8638 2U, // FCVTZUUWDr
8639 2U, // FCVTZUUWHr
8640 2U, // FCVTZUUWSr
8641 2U, // FCVTZUUXDr
8642 2U, // FCVTZUUXHr
8643 2U, // FCVTZUUXSr
8644 0U, // FCVTZU_ZPmZ_DtoD
8645 0U, // FCVTZU_ZPmZ_DtoS
8646 17U, // FCVTZU_ZPmZ_HtoD
8647 0U, // FCVTZU_ZPmZ_HtoH
8648 17U, // FCVTZU_ZPmZ_HtoS
8649 1U, // FCVTZU_ZPmZ_StoD
8650 1U, // FCVTZU_ZPmZ_StoS
8651 197U, // FCVTZUd
8652 197U, // FCVTZUh
8653 197U, // FCVTZUs
8654 2U, // FCVTZUv1f16
8655 2U, // FCVTZUv1i32
8656 2U, // FCVTZUv1i64
8657 2U, // FCVTZUv2f32
8658 3U, // FCVTZUv2f64
8659 201U, // FCVTZUv2i32_shift
8660 198U, // FCVTZUv2i64_shift
8661 3U, // FCVTZUv4f16
8662 4U, // FCVTZUv4f32
8663 202U, // FCVTZUv4i16_shift
8664 199U, // FCVTZUv4i32_shift
8665 4U, // FCVTZUv8f16
8666 199U, // FCVTZUv8i16_shift
8667 0U, // FCVT_ZPmZ_DtoH
8668 0U, // FCVT_ZPmZ_DtoS
8669 17U, // FCVT_ZPmZ_HtoD
8670 17U, // FCVT_ZPmZ_HtoS
8671 1U, // FCVT_ZPmZ_StoD
8672 0U, // FCVT_ZPmZ_StoH
8673 197U, // FDIVDrr
8674 197U, // FDIVHrr
8675 1057160U, // FDIVR_ZPmZ_D
8676 1614536U, // FDIVR_ZPmZ_H
8677 2106120U, // FDIVR_ZPmZ_S
8678 197U, // FDIVSrr
8679 1057160U, // FDIV_ZPmZ_D
8680 1614536U, // FDIV_ZPmZ_H
8681 2106120U, // FDIV_ZPmZ_S
8682 57865U, // FDIVv2f32
8683 16902U, // FDIVv2f64
8684 66058U, // FDIVv4f16
8685 25095U, // FDIVv4f32
8686 33287U, // FDIVv8f16
8687 0U, // FDUP_ZI_D
8688 0U, // FDUP_ZI_H
8689 0U, // FDUP_ZI_S
8690 2U, // FEXPA_ZZ_D
8691 0U, // FEXPA_ZZ_H
8692 2U, // FEXPA_ZZ_S
8693 2U, // FJCVTZS
8694 0U, // FLOGB_ZPmZ_D
8695 0U, // FLOGB_ZPmZ_H
8696 1U, // FLOGB_ZPmZ_S
8697 8389U, // FMADDDrrr
8698 8389U, // FMADDHrrr
8699 8389U, // FMADDSrrr
8700 8396872U, // FMAD_ZPmZZ_D
8701 1811153U, // FMAD_ZPmZZ_H
8702 8921224U, // FMAD_ZPmZZ_S
8703 197U, // FMAXDrr
8704 197U, // FMAXHrr
8705 197U, // FMAXNMDrr
8706 197U, // FMAXNMHrr
8707 1057160U, // FMAXNMP_ZPmZZ_D
8708 1614536U, // FMAXNMP_ZPmZZ_H
8709 2106120U, // FMAXNMP_ZPmZZ_S
8710 57865U, // FMAXNMPv2f32
8711 16902U, // FMAXNMPv2f64
8712 24U, // FMAXNMPv2i16p
8713 2U, // FMAXNMPv2i32p
8714 3U, // FMAXNMPv2i64p
8715 66058U, // FMAXNMPv4f16
8716 25095U, // FMAXNMPv4f32
8717 33287U, // FMAXNMPv8f16
8718 197U, // FMAXNMSrr
8719 0U, // FMAXNMV_VPZ_D
8720 0U, // FMAXNMV_VPZ_H
8721 0U, // FMAXNMV_VPZ_S
8722 3U, // FMAXNMVv4i16v
8723 4U, // FMAXNMVv4i32v
8724 4U, // FMAXNMVv8i16v
8725 9445768U, // FMAXNM_ZPmI_D
8726 254664U, // FMAXNM_ZPmI_H
8727 9446152U, // FMAXNM_ZPmI_S
8728 1057160U, // FMAXNM_ZPmZ_D
8729 1614536U, // FMAXNM_ZPmZ_H
8730 2106120U, // FMAXNM_ZPmZ_S
8731 57865U, // FMAXNMv2f32
8732 16902U, // FMAXNMv2f64
8733 66058U, // FMAXNMv4f16
8734 25095U, // FMAXNMv4f32
8735 33287U, // FMAXNMv8f16
8736 1057160U, // FMAXP_ZPmZZ_D
8737 1614536U, // FMAXP_ZPmZZ_H
8738 2106120U, // FMAXP_ZPmZZ_S
8739 57865U, // FMAXPv2f32
8740 16902U, // FMAXPv2f64
8741 24U, // FMAXPv2i16p
8742 2U, // FMAXPv2i32p
8743 3U, // FMAXPv2i64p
8744 66058U, // FMAXPv4f16
8745 25095U, // FMAXPv4f32
8746 33287U, // FMAXPv8f16
8747 197U, // FMAXSrr
8748 0U, // FMAXV_VPZ_D
8749 0U, // FMAXV_VPZ_H
8750 0U, // FMAXV_VPZ_S
8751 3U, // FMAXVv4i16v
8752 4U, // FMAXVv4i32v
8753 4U, // FMAXVv8i16v
8754 9445768U, // FMAX_ZPmI_D
8755 254664U, // FMAX_ZPmI_H
8756 9446152U, // FMAX_ZPmI_S
8757 1057160U, // FMAX_ZPmZ_D
8758 1614536U, // FMAX_ZPmZ_H
8759 2106120U, // FMAX_ZPmZ_S
8760 57865U, // FMAXv2f32
8761 16902U, // FMAXv2f64
8762 66058U, // FMAXv4f16
8763 25095U, // FMAXv4f32
8764 33287U, // FMAXv8f16
8765 197U, // FMINDrr
8766 197U, // FMINHrr
8767 197U, // FMINNMDrr
8768 197U, // FMINNMHrr
8769 1057160U, // FMINNMP_ZPmZZ_D
8770 1614536U, // FMINNMP_ZPmZZ_H
8771 2106120U, // FMINNMP_ZPmZZ_S
8772 57865U, // FMINNMPv2f32
8773 16902U, // FMINNMPv2f64
8774 24U, // FMINNMPv2i16p
8775 2U, // FMINNMPv2i32p
8776 3U, // FMINNMPv2i64p
8777 66058U, // FMINNMPv4f16
8778 25095U, // FMINNMPv4f32
8779 33287U, // FMINNMPv8f16
8780 197U, // FMINNMSrr
8781 0U, // FMINNMV_VPZ_D
8782 0U, // FMINNMV_VPZ_H
8783 0U, // FMINNMV_VPZ_S
8784 3U, // FMINNMVv4i16v
8785 4U, // FMINNMVv4i32v
8786 4U, // FMINNMVv8i16v
8787 9445768U, // FMINNM_ZPmI_D
8788 254664U, // FMINNM_ZPmI_H
8789 9446152U, // FMINNM_ZPmI_S
8790 1057160U, // FMINNM_ZPmZ_D
8791 1614536U, // FMINNM_ZPmZ_H
8792 2106120U, // FMINNM_ZPmZ_S
8793 57865U, // FMINNMv2f32
8794 16902U, // FMINNMv2f64
8795 66058U, // FMINNMv4f16
8796 25095U, // FMINNMv4f32
8797 33287U, // FMINNMv8f16
8798 1057160U, // FMINP_ZPmZZ_D
8799 1614536U, // FMINP_ZPmZZ_H
8800 2106120U, // FMINP_ZPmZZ_S
8801 57865U, // FMINPv2f32
8802 16902U, // FMINPv2f64
8803 24U, // FMINPv2i16p
8804 2U, // FMINPv2i32p
8805 3U, // FMINPv2i64p
8806 66058U, // FMINPv4f16
8807 25095U, // FMINPv4f32
8808 33287U, // FMINPv8f16
8809 197U, // FMINSrr
8810 0U, // FMINV_VPZ_D
8811 0U, // FMINV_VPZ_H
8812 0U, // FMINV_VPZ_S
8813 3U, // FMINVv4i16v
8814 4U, // FMINVv4i32v
8815 4U, // FMINVv8i16v
8816 9445768U, // FMIN_ZPmI_D
8817 254664U, // FMIN_ZPmI_H
8818 9446152U, // FMIN_ZPmI_S
8819 1057160U, // FMIN_ZPmZ_D
8820 1614536U, // FMIN_ZPmZ_H
8821 2106120U, // FMIN_ZPmZ_S
8822 57865U, // FMINv2f32
8823 16902U, // FMINv2f64
8824 66058U, // FMINv4f16
8825 25095U, // FMINv4f32
8826 33287U, // FMINv8f16
8827 2844U, // FMLAL2lanev4f16
8828 3277386U, // FMLAL2lanev8f16
8829 2908U, // FMLAL2v4f16
8830 66122U, // FMLAL2v8f16
8831 1696197U, // FMLALB_ZZZI_SHH
8832 453U, // FMLALB_ZZZ_SHH
8833 1696197U, // FMLALT_ZZZI_SHH
8834 453U, // FMLALT_ZZZ_SHH
8835 2844U, // FMLALlanev4f16
8836 3277386U, // FMLALlanev8f16
8837 2908U, // FMLALv4f16
8838 66122U, // FMLALv8f16
8839 8396872U, // FMLA_ZPmZZ_D
8840 1811153U, // FMLA_ZPmZZ_H
8841 8921224U, // FMLA_ZPmZZ_S
8842 1695813U, // FMLA_ZZZI_D
8843 2449U, // FMLA_ZZZI_H
8844 1695877U, // FMLA_ZZZI_S
8845 3277381U, // FMLAv1i16_indexed
8846 3392069U, // FMLAv1i32_indexed
8847 3408453U, // FMLAv1i64_indexed
8848 57929U, // FMLAv2f32
8849 16966U, // FMLAv2f64
8850 3392073U, // FMLAv2i32_indexed
8851 3408454U, // FMLAv2i64_indexed
8852 66122U, // FMLAv4f16
8853 25159U, // FMLAv4f32
8854 3277386U, // FMLAv4i16_indexed
8855 3392071U, // FMLAv4i32_indexed
8856 33351U, // FMLAv8f16
8857 3277383U, // FMLAv8i16_indexed
8858 2844U, // FMLSL2lanev4f16
8859 3277386U, // FMLSL2lanev8f16
8860 2908U, // FMLSL2v4f16
8861 66122U, // FMLSL2v8f16
8862 1696197U, // FMLSLB_ZZZI_SHH
8863 453U, // FMLSLB_ZZZ_SHH
8864 1696197U, // FMLSLT_ZZZI_SHH
8865 453U, // FMLSLT_ZZZ_SHH
8866 2844U, // FMLSLlanev4f16
8867 3277386U, // FMLSLlanev8f16
8868 2908U, // FMLSLv4f16
8869 66122U, // FMLSLv8f16
8870 8396872U, // FMLS_ZPmZZ_D
8871 1811153U, // FMLS_ZPmZZ_H
8872 8921224U, // FMLS_ZPmZZ_S
8873 1695813U, // FMLS_ZZZI_D
8874 2449U, // FMLS_ZZZI_H
8875 1695877U, // FMLS_ZZZI_S
8876 3277381U, // FMLSv1i16_indexed
8877 3392069U, // FMLSv1i32_indexed
8878 3408453U, // FMLSv1i64_indexed
8879 57929U, // FMLSv2f32
8880 16966U, // FMLSv2f64
8881 3392073U, // FMLSv2i32_indexed
8882 3408454U, // FMLSv2i64_indexed
8883 66122U, // FMLSv4f16
8884 25159U, // FMLSv4f32
8885 3277386U, // FMLSv4i16_indexed
8886 3392071U, // FMLSv4i32_indexed
8887 33351U, // FMLSv8f16
8888 3277383U, // FMLSv8i16_indexed
8889 69U, // FMMLA_ZZZ_D
8890 133U, // FMMLA_ZZZ_S
8891 2710U, // FMOVDXHighr
8892 2U, // FMOVDXr
8893 0U, // FMOVDi
8894 2U, // FMOVDr
8895 2U, // FMOVHWr
8896 2U, // FMOVHXr
8897 0U, // FMOVHi
8898 2U, // FMOVHr
8899 2U, // FMOVSWr
8900 0U, // FMOVSi
8901 2U, // FMOVSr
8902 2U, // FMOVWHr
8903 2U, // FMOVWSr
8904 2U, // FMOVXDHighr
8905 2U, // FMOVXDr
8906 2U, // FMOVXHr
8907 0U, // FMOVv2f32_ns
8908 0U, // FMOVv2f64_ns
8909 0U, // FMOVv4f16_ns
8910 0U, // FMOVv4f32_ns
8911 0U, // FMOVv8f16_ns
8912 8396872U, // FMSB_ZPmZZ_D
8913 1811153U, // FMSB_ZPmZZ_H
8914 8921224U, // FMSB_ZPmZZ_S
8915 8389U, // FMSUBDrrr
8916 8389U, // FMSUBHrrr
8917 8389U, // FMSUBSrrr
8918 197U, // FMULDrr
8919 197U, // FMULHrr
8920 197U, // FMULSrr
8921 197U, // FMULX16
8922 197U, // FMULX32
8923 197U, // FMULX64
8924 1057160U, // FMULX_ZPmZ_D
8925 1614536U, // FMULX_ZPmZ_H
8926 2106120U, // FMULX_ZPmZ_S
8927 10093061U, // FMULXv1i16_indexed
8928 10207749U, // FMULXv1i32_indexed
8929 10224133U, // FMULXv1i64_indexed
8930 57865U, // FMULXv2f32
8931 16902U, // FMULXv2f64
8932 10207753U, // FMULXv2i32_indexed
8933 10224134U, // FMULXv2i64_indexed
8934 66058U, // FMULXv4f16
8935 25095U, // FMULXv4f32
8936 10093066U, // FMULXv4i16_indexed
8937 10207751U, // FMULXv4i32_indexed
8938 33287U, // FMULXv8f16
8939 10093063U, // FMULXv8i16_indexed
8940 10494344U, // FMUL_ZPmI_D
8941 271048U, // FMUL_ZPmI_H
8942 10494728U, // FMUL_ZPmI_S
8943 1057160U, // FMUL_ZPmZ_D
8944 1614536U, // FMUL_ZPmZ_H
8945 2106120U, // FMUL_ZPmZ_S
8946 278917U, // FMUL_ZZZI_D
8947 2952U, // FMUL_ZZZI_H
8948 279301U, // FMUL_ZZZI_S
8949 389U, // FMUL_ZZZ_D
8950 8U, // FMUL_ZZZ_H
8951 773U, // FMUL_ZZZ_S
8952 10093061U, // FMULv1i16_indexed
8953 10207749U, // FMULv1i32_indexed
8954 10224133U, // FMULv1i64_indexed
8955 57865U, // FMULv2f32
8956 16902U, // FMULv2f64
8957 10207753U, // FMULv2i32_indexed
8958 10224134U, // FMULv2i64_indexed
8959 66058U, // FMULv4f16
8960 25095U, // FMULv4f32
8961 10093066U, // FMULv4i16_indexed
8962 10207751U, // FMULv4i32_indexed
8963 33287U, // FMULv8f16
8964 10093063U, // FMULv8i16_indexed
8965 2U, // FNEGDr
8966 2U, // FNEGHr
8967 2U, // FNEGSr
8968 0U, // FNEG_ZPmZ_D
8969 0U, // FNEG_ZPmZ_H
8970 1U, // FNEG_ZPmZ_S
8971 2U, // FNEGv2f32
8972 3U, // FNEGv2f64
8973 3U, // FNEGv4f16
8974 4U, // FNEGv4f32
8975 4U, // FNEGv8f16
8976 8389U, // FNMADDDrrr
8977 8389U, // FNMADDHrrr
8978 8389U, // FNMADDSrrr
8979 8396872U, // FNMAD_ZPmZZ_D
8980 1811153U, // FNMAD_ZPmZZ_H
8981 8921224U, // FNMAD_ZPmZZ_S
8982 8396872U, // FNMLA_ZPmZZ_D
8983 1811153U, // FNMLA_ZPmZZ_H
8984 8921224U, // FNMLA_ZPmZZ_S
8985 8396872U, // FNMLS_ZPmZZ_D
8986 1811153U, // FNMLS_ZPmZZ_H
8987 8921224U, // FNMLS_ZPmZZ_S
8988 8396872U, // FNMSB_ZPmZZ_D
8989 1811153U, // FNMSB_ZPmZZ_H
8990 8921224U, // FNMSB_ZPmZZ_S
8991 8389U, // FNMSUBDrrr
8992 8389U, // FNMSUBHrrr
8993 8389U, // FNMSUBSrrr
8994 197U, // FNMULDrr
8995 197U, // FNMULHrr
8996 197U, // FNMULSrr
8997 2U, // FRECPE_ZZ_D
8998 0U, // FRECPE_ZZ_H
8999 2U, // FRECPE_ZZ_S
9000 2U, // FRECPEv1f16
9001 2U, // FRECPEv1i32
9002 2U, // FRECPEv1i64
9003 2U, // FRECPEv2f32
9004 3U, // FRECPEv2f64
9005 3U, // FRECPEv4f16
9006 4U, // FRECPEv4f32
9007 4U, // FRECPEv8f16
9008 197U, // FRECPS16
9009 197U, // FRECPS32
9010 197U, // FRECPS64
9011 389U, // FRECPS_ZZZ_D
9012 8U, // FRECPS_ZZZ_H
9013 773U, // FRECPS_ZZZ_S
9014 57865U, // FRECPSv2f32
9015 16902U, // FRECPSv2f64
9016 66058U, // FRECPSv4f16
9017 25095U, // FRECPSv4f32
9018 33287U, // FRECPSv8f16
9019 0U, // FRECPX_ZPmZ_D
9020 0U, // FRECPX_ZPmZ_H
9021 1U, // FRECPX_ZPmZ_S
9022 2U, // FRECPXv1f16
9023 2U, // FRECPXv1i32
9024 2U, // FRECPXv1i64
9025 2U, // FRINT32XDr
9026 2U, // FRINT32XSr
9027 2U, // FRINT32Xv2f32
9028 3U, // FRINT32Xv2f64
9029 4U, // FRINT32Xv4f32
9030 2U, // FRINT32ZDr
9031 2U, // FRINT32ZSr
9032 2U, // FRINT32Zv2f32
9033 3U, // FRINT32Zv2f64
9034 4U, // FRINT32Zv4f32
9035 2U, // FRINT64XDr
9036 2U, // FRINT64XSr
9037 2U, // FRINT64Xv2f32
9038 3U, // FRINT64Xv2f64
9039 4U, // FRINT64Xv4f32
9040 2U, // FRINT64ZDr
9041 2U, // FRINT64ZSr
9042 2U, // FRINT64Zv2f32
9043 3U, // FRINT64Zv2f64
9044 4U, // FRINT64Zv4f32
9045 2U, // FRINTADr
9046 2U, // FRINTAHr
9047 2U, // FRINTASr
9048 0U, // FRINTA_ZPmZ_D
9049 0U, // FRINTA_ZPmZ_H
9050 1U, // FRINTA_ZPmZ_S
9051 2U, // FRINTAv2f32
9052 3U, // FRINTAv2f64
9053 3U, // FRINTAv4f16
9054 4U, // FRINTAv4f32
9055 4U, // FRINTAv8f16
9056 2U, // FRINTIDr
9057 2U, // FRINTIHr
9058 2U, // FRINTISr
9059 0U, // FRINTI_ZPmZ_D
9060 0U, // FRINTI_ZPmZ_H
9061 1U, // FRINTI_ZPmZ_S
9062 2U, // FRINTIv2f32
9063 3U, // FRINTIv2f64
9064 3U, // FRINTIv4f16
9065 4U, // FRINTIv4f32
9066 4U, // FRINTIv8f16
9067 2U, // FRINTMDr
9068 2U, // FRINTMHr
9069 2U, // FRINTMSr
9070 0U, // FRINTM_ZPmZ_D
9071 0U, // FRINTM_ZPmZ_H
9072 1U, // FRINTM_ZPmZ_S
9073 2U, // FRINTMv2f32
9074 3U, // FRINTMv2f64
9075 3U, // FRINTMv4f16
9076 4U, // FRINTMv4f32
9077 4U, // FRINTMv8f16
9078 2U, // FRINTNDr
9079 2U, // FRINTNHr
9080 2U, // FRINTNSr
9081 0U, // FRINTN_ZPmZ_D
9082 0U, // FRINTN_ZPmZ_H
9083 1U, // FRINTN_ZPmZ_S
9084 2U, // FRINTNv2f32
9085 3U, // FRINTNv2f64
9086 3U, // FRINTNv4f16
9087 4U, // FRINTNv4f32
9088 4U, // FRINTNv8f16
9089 2U, // FRINTPDr
9090 2U, // FRINTPHr
9091 2U, // FRINTPSr
9092 0U, // FRINTP_ZPmZ_D
9093 0U, // FRINTP_ZPmZ_H
9094 1U, // FRINTP_ZPmZ_S
9095 2U, // FRINTPv2f32
9096 3U, // FRINTPv2f64
9097 3U, // FRINTPv4f16
9098 4U, // FRINTPv4f32
9099 4U, // FRINTPv8f16
9100 2U, // FRINTXDr
9101 2U, // FRINTXHr
9102 2U, // FRINTXSr
9103 0U, // FRINTX_ZPmZ_D
9104 0U, // FRINTX_ZPmZ_H
9105 1U, // FRINTX_ZPmZ_S
9106 2U, // FRINTXv2f32
9107 3U, // FRINTXv2f64
9108 3U, // FRINTXv4f16
9109 4U, // FRINTXv4f32
9110 4U, // FRINTXv8f16
9111 2U, // FRINTZDr
9112 2U, // FRINTZHr
9113 2U, // FRINTZSr
9114 0U, // FRINTZ_ZPmZ_D
9115 0U, // FRINTZ_ZPmZ_H
9116 1U, // FRINTZ_ZPmZ_S
9117 2U, // FRINTZv2f32
9118 3U, // FRINTZv2f64
9119 3U, // FRINTZv4f16
9120 4U, // FRINTZv4f32
9121 4U, // FRINTZv8f16
9122 2U, // FRSQRTE_ZZ_D
9123 0U, // FRSQRTE_ZZ_H
9124 2U, // FRSQRTE_ZZ_S
9125 2U, // FRSQRTEv1f16
9126 2U, // FRSQRTEv1i32
9127 2U, // FRSQRTEv1i64
9128 2U, // FRSQRTEv2f32
9129 3U, // FRSQRTEv2f64
9130 3U, // FRSQRTEv4f16
9131 4U, // FRSQRTEv4f32
9132 4U, // FRSQRTEv8f16
9133 197U, // FRSQRTS16
9134 197U, // FRSQRTS32
9135 197U, // FRSQRTS64
9136 389U, // FRSQRTS_ZZZ_D
9137 8U, // FRSQRTS_ZZZ_H
9138 773U, // FRSQRTS_ZZZ_S
9139 57865U, // FRSQRTSv2f32
9140 16902U, // FRSQRTSv2f64
9141 66058U, // FRSQRTSv4f16
9142 25095U, // FRSQRTSv4f32
9143 33287U, // FRSQRTSv8f16
9144 1057160U, // FSCALE_ZPmZ_D
9145 1614536U, // FSCALE_ZPmZ_H
9146 2106120U, // FSCALE_ZPmZ_S
9147 2U, // FSQRTDr
9148 2U, // FSQRTHr
9149 2U, // FSQRTSr
9150 0U, // FSQRT_ZPmZ_D
9151 0U, // FSQRT_ZPmZ_H
9152 1U, // FSQRT_ZPmZ_S
9153 2U, // FSQRTv2f32
9154 3U, // FSQRTv2f64
9155 3U, // FSQRTv4f16
9156 4U, // FSQRTv4f32
9157 4U, // FSQRTv8f16
9158 197U, // FSUBDrr
9159 197U, // FSUBHrr
9160 7872904U, // FSUBR_ZPmI_D
9161 180936U, // FSUBR_ZPmI_H
9162 7873288U, // FSUBR_ZPmI_S
9163 1057160U, // FSUBR_ZPmZ_D
9164 1614536U, // FSUBR_ZPmZ_H
9165 2106120U, // FSUBR_ZPmZ_S
9166 197U, // FSUBSrr
9167 7872904U, // FSUB_ZPmI_D
9168 180936U, // FSUB_ZPmI_H
9169 7873288U, // FSUB_ZPmI_S
9170 1057160U, // FSUB_ZPmZ_D
9171 1614536U, // FSUB_ZPmZ_H
9172 2106120U, // FSUB_ZPmZ_S
9173 389U, // FSUB_ZZZ_D
9174 8U, // FSUB_ZZZ_H
9175 773U, // FSUB_ZZZ_S
9176 57865U, // FSUBv2f32
9177 16902U, // FSUBv2f64
9178 66058U, // FSUBv4f16
9179 25095U, // FSUBv4f32
9180 33287U, // FSUBv8f16
9181 8581U, // FTMAD_ZZI_D
9182 90824U, // FTMAD_ZZI_H
9183 8965U, // FTMAD_ZZI_S
9184 389U, // FTSMUL_ZZZ_D
9185 8U, // FTSMUL_ZZZ_H
9186 773U, // FTSMUL_ZZZ_S
9187 389U, // FTSSEL_ZZZ_D
9188 8U, // FTSSEL_ZZZ_H
9189 773U, // FTSSEL_ZZZ_S
9190 149829U, // GLD1B_D_IMM_REAL
9191 3013U, // GLD1B_D_REAL
9192 3077U, // GLD1B_D_SXTW_REAL
9193 3141U, // GLD1B_D_UXTW_REAL
9194 149829U, // GLD1B_S_IMM_REAL
9195 3205U, // GLD1B_S_SXTW_REAL
9196 3269U, // GLD1B_S_UXTW_REAL
9197 150789U, // GLD1D_IMM_REAL
9198 3013U, // GLD1D_REAL
9199 3397U, // GLD1D_SCALED_REAL
9200 3077U, // GLD1D_SXTW_REAL
9201 3461U, // GLD1D_SXTW_SCALED_REAL
9202 3141U, // GLD1D_UXTW_REAL
9203 3525U, // GLD1D_UXTW_SCALED_REAL
9204 151045U, // GLD1H_D_IMM_REAL
9205 3013U, // GLD1H_D_REAL
9206 3653U, // GLD1H_D_SCALED_REAL
9207 3077U, // GLD1H_D_SXTW_REAL
9208 3717U, // GLD1H_D_SXTW_SCALED_REAL
9209 3141U, // GLD1H_D_UXTW_REAL
9210 3781U, // GLD1H_D_UXTW_SCALED_REAL
9211 151045U, // GLD1H_S_IMM_REAL
9212 3205U, // GLD1H_S_SXTW_REAL
9213 3845U, // GLD1H_S_SXTW_SCALED_REAL
9214 3269U, // GLD1H_S_UXTW_REAL
9215 3909U, // GLD1H_S_UXTW_SCALED_REAL
9216 149829U, // GLD1SB_D_IMM_REAL
9217 3013U, // GLD1SB_D_REAL
9218 3077U, // GLD1SB_D_SXTW_REAL
9219 3141U, // GLD1SB_D_UXTW_REAL
9220 149829U, // GLD1SB_S_IMM_REAL
9221 3205U, // GLD1SB_S_SXTW_REAL
9222 3269U, // GLD1SB_S_UXTW_REAL
9223 151045U, // GLD1SH_D_IMM_REAL
9224 3013U, // GLD1SH_D_REAL
9225 3653U, // GLD1SH_D_SCALED_REAL
9226 3077U, // GLD1SH_D_SXTW_REAL
9227 3717U, // GLD1SH_D_SXTW_SCALED_REAL
9228 3141U, // GLD1SH_D_UXTW_REAL
9229 3781U, // GLD1SH_D_UXTW_SCALED_REAL
9230 151045U, // GLD1SH_S_IMM_REAL
9231 3205U, // GLD1SH_S_SXTW_REAL
9232 3845U, // GLD1SH_S_SXTW_SCALED_REAL
9233 3269U, // GLD1SH_S_UXTW_REAL
9234 3909U, // GLD1SH_S_UXTW_SCALED_REAL
9235 151429U, // GLD1SW_D_IMM_REAL
9236 3013U, // GLD1SW_D_REAL
9237 4037U, // GLD1SW_D_SCALED_REAL
9238 3077U, // GLD1SW_D_SXTW_REAL
9239 4101U, // GLD1SW_D_SXTW_SCALED_REAL
9240 3141U, // GLD1SW_D_UXTW_REAL
9241 4165U, // GLD1SW_D_UXTW_SCALED_REAL
9242 151429U, // GLD1W_D_IMM_REAL
9243 3013U, // GLD1W_D_REAL
9244 4037U, // GLD1W_D_SCALED_REAL
9245 3077U, // GLD1W_D_SXTW_REAL
9246 4101U, // GLD1W_D_SXTW_SCALED_REAL
9247 3141U, // GLD1W_D_UXTW_REAL
9248 4165U, // GLD1W_D_UXTW_SCALED_REAL
9249 151429U, // GLD1W_IMM_REAL
9250 3205U, // GLD1W_SXTW_REAL
9251 4229U, // GLD1W_SXTW_SCALED_REAL
9252 3269U, // GLD1W_UXTW_REAL
9253 4293U, // GLD1W_UXTW_SCALED_REAL
9254 149829U, // GLDFF1B_D_IMM_REAL
9255 3013U, // GLDFF1B_D_REAL
9256 3077U, // GLDFF1B_D_SXTW_REAL
9257 3141U, // GLDFF1B_D_UXTW_REAL
9258 149829U, // GLDFF1B_S_IMM_REAL
9259 3205U, // GLDFF1B_S_SXTW_REAL
9260 3269U, // GLDFF1B_S_UXTW_REAL
9261 150789U, // GLDFF1D_IMM_REAL
9262 3013U, // GLDFF1D_REAL
9263 3397U, // GLDFF1D_SCALED_REAL
9264 3077U, // GLDFF1D_SXTW_REAL
9265 3461U, // GLDFF1D_SXTW_SCALED_REAL
9266 3141U, // GLDFF1D_UXTW_REAL
9267 3525U, // GLDFF1D_UXTW_SCALED_REAL
9268 151045U, // GLDFF1H_D_IMM_REAL
9269 3013U, // GLDFF1H_D_REAL
9270 3653U, // GLDFF1H_D_SCALED_REAL
9271 3077U, // GLDFF1H_D_SXTW_REAL
9272 3717U, // GLDFF1H_D_SXTW_SCALED_REAL
9273 3141U, // GLDFF1H_D_UXTW_REAL
9274 3781U, // GLDFF1H_D_UXTW_SCALED_REAL
9275 151045U, // GLDFF1H_S_IMM_REAL
9276 3205U, // GLDFF1H_S_SXTW_REAL
9277 3845U, // GLDFF1H_S_SXTW_SCALED_REAL
9278 3269U, // GLDFF1H_S_UXTW_REAL
9279 3909U, // GLDFF1H_S_UXTW_SCALED_REAL
9280 149829U, // GLDFF1SB_D_IMM_REAL
9281 3013U, // GLDFF1SB_D_REAL
9282 3077U, // GLDFF1SB_D_SXTW_REAL
9283 3141U, // GLDFF1SB_D_UXTW_REAL
9284 149829U, // GLDFF1SB_S_IMM_REAL
9285 3205U, // GLDFF1SB_S_SXTW_REAL
9286 3269U, // GLDFF1SB_S_UXTW_REAL
9287 151045U, // GLDFF1SH_D_IMM_REAL
9288 3013U, // GLDFF1SH_D_REAL
9289 3653U, // GLDFF1SH_D_SCALED_REAL
9290 3077U, // GLDFF1SH_D_SXTW_REAL
9291 3717U, // GLDFF1SH_D_SXTW_SCALED_REAL
9292 3141U, // GLDFF1SH_D_UXTW_REAL
9293 3781U, // GLDFF1SH_D_UXTW_SCALED_REAL
9294 151045U, // GLDFF1SH_S_IMM_REAL
9295 3205U, // GLDFF1SH_S_SXTW_REAL
9296 3845U, // GLDFF1SH_S_SXTW_SCALED_REAL
9297 3269U, // GLDFF1SH_S_UXTW_REAL
9298 3909U, // GLDFF1SH_S_UXTW_SCALED_REAL
9299 151429U, // GLDFF1SW_D_IMM_REAL
9300 3013U, // GLDFF1SW_D_REAL
9301 4037U, // GLDFF1SW_D_SCALED_REAL
9302 3077U, // GLDFF1SW_D_SXTW_REAL
9303 4101U, // GLDFF1SW_D_SXTW_SCALED_REAL
9304 3141U, // GLDFF1SW_D_UXTW_REAL
9305 4165U, // GLDFF1SW_D_UXTW_SCALED_REAL
9306 151429U, // GLDFF1W_D_IMM_REAL
9307 3013U, // GLDFF1W_D_REAL
9308 4037U, // GLDFF1W_D_SCALED_REAL
9309 3077U, // GLDFF1W_D_SXTW_REAL
9310 4101U, // GLDFF1W_D_SXTW_SCALED_REAL
9311 3141U, // GLDFF1W_D_UXTW_REAL
9312 4165U, // GLDFF1W_D_UXTW_SCALED_REAL
9313 151429U, // GLDFF1W_IMM_REAL
9314 3205U, // GLDFF1W_SXTW_REAL
9315 4229U, // GLDFF1W_SXTW_SCALED_REAL
9316 3269U, // GLDFF1W_UXTW_REAL
9317 4293U, // GLDFF1W_UXTW_SCALED_REAL
9318 197U, // GMI
9319 0U, // HINT
9320 1057163U, // HISTCNT_ZPzZZ_D
9321 2106123U, // HISTCNT_ZPzZZ_S
9322 645U, // HISTSEG_ZZZ
9323 0U, // HLT
9324 0U, // HVC
9325 0U, // INCB_XPiI
9326 0U, // INCD_XPiI
9327 0U, // INCD_ZPiI
9328 0U, // INCH_XPiI
9329 0U, // INCH_ZPiI
9330 2U, // INCP_XP_B
9331 2U, // INCP_XP_D
9332 2U, // INCP_XP_H
9333 2U, // INCP_XP_S
9334 2U, // INCP_ZP_D
9335 0U, // INCP_ZP_H
9336 2U, // INCP_ZP_S
9337 0U, // INCW_XPiI
9338 0U, // INCW_ZPiI
9339 28U, // INDEX_II_B
9340 197U, // INDEX_II_D
9341 0U, // INDEX_II_H
9342 197U, // INDEX_II_S
9343 12U, // INDEX_IR_B
9344 197U, // INDEX_IR_D
9345 2U, // INDEX_IR_H
9346 197U, // INDEX_IR_S
9347 4357U, // INDEX_RI_B
9348 197U, // INDEX_RI_D
9349 29U, // INDEX_RI_H
9350 197U, // INDEX_RI_S
9351 197U, // INDEX_RR_B
9352 197U, // INDEX_RR_D
9353 12U, // INDEX_RR_H
9354 197U, // INDEX_RR_S
9355 2U, // INSR_ZR_B
9356 2U, // INSR_ZR_D
9357 0U, // INSR_ZR_H
9358 2U, // INSR_ZR_S
9359 2U, // INSR_ZV_B
9360 2U, // INSR_ZV_D
9361 0U, // INSR_ZV_H
9362 2U, // INSR_ZV_S
9363 0U, // INSvi16gpr
9364 2453U, // INSvi16lane
9365 0U, // INSvi32gpr
9366 2453U, // INSvi32lane
9367 0U, // INSvi64gpr
9368 2454U, // INSvi64lane
9369 0U, // INSvi8gpr
9370 2454U, // INSvi8lane
9371 197U, // IRG
9372 0U, // ISB
9373 645U, // LASTA_RPZ_B
9374 389U, // LASTA_RPZ_D
9375 325U, // LASTA_RPZ_H
9376 773U, // LASTA_RPZ_S
9377 645U, // LASTA_VPZ_B
9378 389U, // LASTA_VPZ_D
9379 325U, // LASTA_VPZ_H
9380 773U, // LASTA_VPZ_S
9381 645U, // LASTB_RPZ_B
9382 389U, // LASTB_RPZ_D
9383 325U, // LASTB_RPZ_H
9384 773U, // LASTB_RPZ_S
9385 645U, // LASTB_VPZ_B
9386 389U, // LASTB_VPZ_D
9387 325U, // LASTB_VPZ_H
9388 773U, // LASTB_VPZ_S
9389 4421U, // LD1B
9390 4421U, // LD1B_D
9391 289093U, // LD1B_D_IMM_REAL
9392 4421U, // LD1B_H
9393 289093U, // LD1B_H_IMM_REAL
9394 289093U, // LD1B_IMM_REAL
9395 4421U, // LD1B_S
9396 289093U, // LD1B_S_IMM_REAL
9397 4485U, // LD1D
9398 289093U, // LD1D_IMM_REAL
9399 0U, // LD1Fourv16b
9400 0U, // LD1Fourv16b_POST
9401 0U, // LD1Fourv1d
9402 0U, // LD1Fourv1d_POST
9403 0U, // LD1Fourv2d
9404 0U, // LD1Fourv2d_POST
9405 0U, // LD1Fourv2s
9406 0U, // LD1Fourv2s_POST
9407 0U, // LD1Fourv4h
9408 0U, // LD1Fourv4h_POST
9409 0U, // LD1Fourv4s
9410 0U, // LD1Fourv4s_POST
9411 0U, // LD1Fourv8b
9412 0U, // LD1Fourv8b_POST
9413 0U, // LD1Fourv8h
9414 0U, // LD1Fourv8h_POST
9415 4549U, // LD1H
9416 4549U, // LD1H_D
9417 289093U, // LD1H_D_IMM_REAL
9418 289093U, // LD1H_IMM_REAL
9419 4549U, // LD1H_S
9420 289093U, // LD1H_S_IMM_REAL
9421 0U, // LD1Onev16b
9422 0U, // LD1Onev16b_POST
9423 0U, // LD1Onev1d
9424 0U, // LD1Onev1d_POST
9425 0U, // LD1Onev2d
9426 0U, // LD1Onev2d_POST
9427 0U, // LD1Onev2s
9428 0U, // LD1Onev2s_POST
9429 0U, // LD1Onev4h
9430 0U, // LD1Onev4h_POST
9431 0U, // LD1Onev4s
9432 0U, // LD1Onev4s_POST
9433 0U, // LD1Onev8b
9434 0U, // LD1Onev8b_POST
9435 0U, // LD1Onev8h
9436 0U, // LD1Onev8h_POST
9437 149829U, // LD1RB_D_IMM
9438 149829U, // LD1RB_H_IMM
9439 149829U, // LD1RB_IMM
9440 149829U, // LD1RB_S_IMM
9441 150789U, // LD1RD_IMM
9442 151045U, // LD1RH_D_IMM
9443 151045U, // LD1RH_IMM
9444 151045U, // LD1RH_S_IMM
9445 4421U, // LD1RO_B
9446 4613U, // LD1RO_B_IMM
9447 4485U, // LD1RO_D
9448 4613U, // LD1RO_D_IMM
9449 4549U, // LD1RO_H
9450 4613U, // LD1RO_H_IMM
9451 4677U, // LD1RO_W
9452 4613U, // LD1RO_W_IMM
9453 4421U, // LD1RQ_B
9454 152197U, // LD1RQ_B_IMM
9455 4485U, // LD1RQ_D
9456 152197U, // LD1RQ_D_IMM
9457 4549U, // LD1RQ_H
9458 152197U, // LD1RQ_H_IMM
9459 4677U, // LD1RQ_W
9460 152197U, // LD1RQ_W_IMM
9461 149829U, // LD1RSB_D_IMM
9462 149829U, // LD1RSB_H_IMM
9463 149829U, // LD1RSB_S_IMM
9464 151045U, // LD1RSH_D_IMM
9465 151045U, // LD1RSH_S_IMM
9466 151429U, // LD1RSW_IMM
9467 151429U, // LD1RW_D_IMM
9468 151429U, // LD1RW_IMM
9469 0U, // LD1Rv16b
9470 0U, // LD1Rv16b_POST
9471 0U, // LD1Rv1d
9472 0U, // LD1Rv1d_POST
9473 0U, // LD1Rv2d
9474 0U, // LD1Rv2d_POST
9475 0U, // LD1Rv2s
9476 0U, // LD1Rv2s_POST
9477 0U, // LD1Rv4h
9478 0U, // LD1Rv4h_POST
9479 0U, // LD1Rv4s
9480 0U, // LD1Rv4s_POST
9481 0U, // LD1Rv8b
9482 0U, // LD1Rv8b_POST
9483 0U, // LD1Rv8h
9484 0U, // LD1Rv8h_POST
9485 4421U, // LD1SB_D
9486 289093U, // LD1SB_D_IMM_REAL
9487 4421U, // LD1SB_H
9488 289093U, // LD1SB_H_IMM_REAL
9489 4421U, // LD1SB_S
9490 289093U, // LD1SB_S_IMM_REAL
9491 4549U, // LD1SH_D
9492 289093U, // LD1SH_D_IMM_REAL
9493 4549U, // LD1SH_S
9494 289093U, // LD1SH_S_IMM_REAL
9495 4677U, // LD1SW_D
9496 289093U, // LD1SW_D_IMM_REAL
9497 0U, // LD1Threev16b
9498 0U, // LD1Threev16b_POST
9499 0U, // LD1Threev1d
9500 0U, // LD1Threev1d_POST
9501 0U, // LD1Threev2d
9502 0U, // LD1Threev2d_POST
9503 0U, // LD1Threev2s
9504 0U, // LD1Threev2s_POST
9505 0U, // LD1Threev4h
9506 0U, // LD1Threev4h_POST
9507 0U, // LD1Threev4s
9508 0U, // LD1Threev4s_POST
9509 0U, // LD1Threev8b
9510 0U, // LD1Threev8b_POST
9511 0U, // LD1Threev8h
9512 0U, // LD1Threev8h_POST
9513 0U, // LD1Twov16b
9514 0U, // LD1Twov16b_POST
9515 0U, // LD1Twov1d
9516 0U, // LD1Twov1d_POST
9517 0U, // LD1Twov2d
9518 0U, // LD1Twov2d_POST
9519 0U, // LD1Twov2s
9520 0U, // LD1Twov2s_POST
9521 0U, // LD1Twov4h
9522 0U, // LD1Twov4h_POST
9523 0U, // LD1Twov4s
9524 0U, // LD1Twov4s_POST
9525 0U, // LD1Twov8b
9526 0U, // LD1Twov8b_POST
9527 0U, // LD1Twov8h
9528 0U, // LD1Twov8h_POST
9529 4677U, // LD1W
9530 4677U, // LD1W_D
9531 289093U, // LD1W_D_IMM_REAL
9532 289093U, // LD1W_IMM_REAL
9533 0U, // LD1i16
9534 0U, // LD1i16_POST
9535 0U, // LD1i32
9536 0U, // LD1i32_POST
9537 0U, // LD1i64
9538 0U, // LD1i64_POST
9539 0U, // LD1i8
9540 0U, // LD1i8_POST
9541 4421U, // LD2B
9542 290309U, // LD2B_IMM
9543 4485U, // LD2D
9544 290309U, // LD2D_IMM
9545 4549U, // LD2H
9546 290309U, // LD2H_IMM
9547 0U, // LD2Rv16b
9548 0U, // LD2Rv16b_POST
9549 0U, // LD2Rv1d
9550 0U, // LD2Rv1d_POST
9551 0U, // LD2Rv2d
9552 0U, // LD2Rv2d_POST
9553 0U, // LD2Rv2s
9554 0U, // LD2Rv2s_POST
9555 0U, // LD2Rv4h
9556 0U, // LD2Rv4h_POST
9557 0U, // LD2Rv4s
9558 0U, // LD2Rv4s_POST
9559 0U, // LD2Rv8b
9560 0U, // LD2Rv8b_POST
9561 0U, // LD2Rv8h
9562 0U, // LD2Rv8h_POST
9563 0U, // LD2Twov16b
9564 0U, // LD2Twov16b_POST
9565 0U, // LD2Twov2d
9566 0U, // LD2Twov2d_POST
9567 0U, // LD2Twov2s
9568 0U, // LD2Twov2s_POST
9569 0U, // LD2Twov4h
9570 0U, // LD2Twov4h_POST
9571 0U, // LD2Twov4s
9572 0U, // LD2Twov4s_POST
9573 0U, // LD2Twov8b
9574 0U, // LD2Twov8b_POST
9575 0U, // LD2Twov8h
9576 0U, // LD2Twov8h_POST
9577 4677U, // LD2W
9578 290309U, // LD2W_IMM
9579 0U, // LD2i16
9580 0U, // LD2i16_POST
9581 0U, // LD2i32
9582 0U, // LD2i32_POST
9583 0U, // LD2i64
9584 0U, // LD2i64_POST
9585 0U, // LD2i8
9586 0U, // LD2i8_POST
9587 4421U, // LD3B
9588 4805U, // LD3B_IMM
9589 4485U, // LD3D
9590 4805U, // LD3D_IMM
9591 4549U, // LD3H
9592 4805U, // LD3H_IMM
9593 0U, // LD3Rv16b
9594 0U, // LD3Rv16b_POST
9595 0U, // LD3Rv1d
9596 0U, // LD3Rv1d_POST
9597 0U, // LD3Rv2d
9598 0U, // LD3Rv2d_POST
9599 0U, // LD3Rv2s
9600 0U, // LD3Rv2s_POST
9601 0U, // LD3Rv4h
9602 0U, // LD3Rv4h_POST
9603 0U, // LD3Rv4s
9604 0U, // LD3Rv4s_POST
9605 0U, // LD3Rv8b
9606 0U, // LD3Rv8b_POST
9607 0U, // LD3Rv8h
9608 0U, // LD3Rv8h_POST
9609 0U, // LD3Threev16b
9610 0U, // LD3Threev16b_POST
9611 0U, // LD3Threev2d
9612 0U, // LD3Threev2d_POST
9613 0U, // LD3Threev2s
9614 0U, // LD3Threev2s_POST
9615 0U, // LD3Threev4h
9616 0U, // LD3Threev4h_POST
9617 0U, // LD3Threev4s
9618 0U, // LD3Threev4s_POST
9619 0U, // LD3Threev8b
9620 0U, // LD3Threev8b_POST
9621 0U, // LD3Threev8h
9622 0U, // LD3Threev8h_POST
9623 4677U, // LD3W
9624 4805U, // LD3W_IMM
9625 0U, // LD3i16
9626 0U, // LD3i16_POST
9627 0U, // LD3i32
9628 0U, // LD3i32_POST
9629 0U, // LD3i64
9630 0U, // LD3i64_POST
9631 0U, // LD3i8
9632 0U, // LD3i8_POST
9633 4421U, // LD4B
9634 290693U, // LD4B_IMM
9635 4485U, // LD4D
9636 290693U, // LD4D_IMM
9637 0U, // LD4Fourv16b
9638 0U, // LD4Fourv16b_POST
9639 0U, // LD4Fourv2d
9640 0U, // LD4Fourv2d_POST
9641 0U, // LD4Fourv2s
9642 0U, // LD4Fourv2s_POST
9643 0U, // LD4Fourv4h
9644 0U, // LD4Fourv4h_POST
9645 0U, // LD4Fourv4s
9646 0U, // LD4Fourv4s_POST
9647 0U, // LD4Fourv8b
9648 0U, // LD4Fourv8b_POST
9649 0U, // LD4Fourv8h
9650 0U, // LD4Fourv8h_POST
9651 4549U, // LD4H
9652 290693U, // LD4H_IMM
9653 0U, // LD4Rv16b
9654 0U, // LD4Rv16b_POST
9655 0U, // LD4Rv1d
9656 0U, // LD4Rv1d_POST
9657 0U, // LD4Rv2d
9658 0U, // LD4Rv2d_POST
9659 0U, // LD4Rv2s
9660 0U, // LD4Rv2s_POST
9661 0U, // LD4Rv4h
9662 0U, // LD4Rv4h_POST
9663 0U, // LD4Rv4s
9664 0U, // LD4Rv4s_POST
9665 0U, // LD4Rv8b
9666 0U, // LD4Rv8b_POST
9667 0U, // LD4Rv8h
9668 0U, // LD4Rv8h_POST
9669 4677U, // LD4W
9670 290693U, // LD4W_IMM
9671 0U, // LD4i16
9672 0U, // LD4i16_POST
9673 0U, // LD4i32
9674 0U, // LD4i32_POST
9675 0U, // LD4i64
9676 0U, // LD4i64_POST
9677 0U, // LD4i8
9678 0U, // LD4i8_POST
9679 0U, // LD64B
9680 0U, // LDADDAB
9681 0U, // LDADDAH
9682 0U, // LDADDALB
9683 0U, // LDADDALH
9684 0U, // LDADDALW
9685 0U, // LDADDALX
9686 0U, // LDADDAW
9687 0U, // LDADDAX
9688 0U, // LDADDB
9689 0U, // LDADDH
9690 0U, // LDADDLB
9691 0U, // LDADDLH
9692 0U, // LDADDLW
9693 0U, // LDADDLX
9694 0U, // LDADDW
9695 0U, // LDADDX
9696 29U, // LDAPRB
9697 29U, // LDAPRH
9698 29U, // LDAPRW
9699 29U, // LDAPRX
9700 147653U, // LDAPURBi
9701 147653U, // LDAPURHi
9702 147653U, // LDAPURSBWi
9703 147653U, // LDAPURSBXi
9704 147653U, // LDAPURSHWi
9705 147653U, // LDAPURSHXi
9706 147653U, // LDAPURSWi
9707 147653U, // LDAPURXi
9708 147653U, // LDAPURi
9709 29U, // LDARB
9710 29U, // LDARH
9711 29U, // LDARW
9712 29U, // LDARX
9713 147661U, // LDAXPW
9714 147661U, // LDAXPX
9715 29U, // LDAXRB
9716 29U, // LDAXRH
9717 29U, // LDAXRW
9718 29U, // LDAXRX
9719 0U, // LDCLRAB
9720 0U, // LDCLRAH
9721 0U, // LDCLRALB
9722 0U, // LDCLRALH
9723 0U, // LDCLRALW
9724 0U, // LDCLRALX
9725 0U, // LDCLRAW
9726 0U, // LDCLRAX
9727 0U, // LDCLRB
9728 0U, // LDCLRH
9729 0U, // LDCLRLB
9730 0U, // LDCLRLH
9731 0U, // LDCLRLW
9732 0U, // LDCLRLX
9733 0U, // LDCLRW
9734 0U, // LDCLRX
9735 0U, // LDEORAB
9736 0U, // LDEORAH
9737 0U, // LDEORALB
9738 0U, // LDEORALH
9739 0U, // LDEORALW
9740 0U, // LDEORALX
9741 0U, // LDEORAW
9742 0U, // LDEORAX
9743 0U, // LDEORB
9744 0U, // LDEORH
9745 0U, // LDEORLB
9746 0U, // LDEORLH
9747 0U, // LDEORLW
9748 0U, // LDEORLX
9749 0U, // LDEORW
9750 0U, // LDEORX
9751 4421U, // LDFF1B_D_REAL
9752 4421U, // LDFF1B_H_REAL
9753 4421U, // LDFF1B_REAL
9754 4421U, // LDFF1B_S_REAL
9755 4485U, // LDFF1D_REAL
9756 4549U, // LDFF1H_D_REAL
9757 4549U, // LDFF1H_REAL
9758 4549U, // LDFF1H_S_REAL
9759 4421U, // LDFF1SB_D_REAL
9760 4421U, // LDFF1SB_H_REAL
9761 4421U, // LDFF1SB_S_REAL
9762 4549U, // LDFF1SH_D_REAL
9763 4549U, // LDFF1SH_S_REAL
9764 4677U, // LDFF1SW_D_REAL
9765 4677U, // LDFF1W_D_REAL
9766 4677U, // LDFF1W_REAL
9767 152197U, // LDG
9768 29U, // LDGM
9769 29U, // LDLARB
9770 29U, // LDLARH
9771 29U, // LDLARW
9772 29U, // LDLARX
9773 289093U, // LDNF1B_D_IMM_REAL
9774 289093U, // LDNF1B_H_IMM_REAL
9775 289093U, // LDNF1B_IMM_REAL
9776 289093U, // LDNF1B_S_IMM_REAL
9777 289093U, // LDNF1D_IMM_REAL
9778 289093U, // LDNF1H_D_IMM_REAL
9779 289093U, // LDNF1H_IMM_REAL
9780 289093U, // LDNF1H_S_IMM_REAL
9781 289093U, // LDNF1SB_D_IMM_REAL
9782 289093U, // LDNF1SB_H_IMM_REAL
9783 289093U, // LDNF1SB_S_IMM_REAL
9784 289093U, // LDNF1SH_D_IMM_REAL
9785 289093U, // LDNF1SH_S_IMM_REAL
9786 289093U, // LDNF1SW_D_IMM_REAL
9787 289093U, // LDNF1W_D_IMM_REAL
9788 289093U, // LDNF1W_IMM_REAL
9789 11018445U, // LDNPDi
9790 11542733U, // LDNPQi
9791 12067021U, // LDNPSi
9792 12067021U, // LDNPWi
9793 11018445U, // LDNPXi
9794 289093U, // LDNT1B_ZRI
9795 4421U, // LDNT1B_ZRR
9796 149829U, // LDNT1B_ZZR_D_REAL
9797 149829U, // LDNT1B_ZZR_S_REAL
9798 289093U, // LDNT1D_ZRI
9799 4485U, // LDNT1D_ZRR
9800 149829U, // LDNT1D_ZZR_D_REAL
9801 289093U, // LDNT1H_ZRI
9802 4549U, // LDNT1H_ZRR
9803 149829U, // LDNT1H_ZZR_D_REAL
9804 149829U, // LDNT1H_ZZR_S_REAL
9805 149829U, // LDNT1SB_ZZR_D_REAL
9806 149829U, // LDNT1SB_ZZR_S_REAL
9807 149829U, // LDNT1SH_ZZR_D_REAL
9808 149829U, // LDNT1SH_ZZR_S_REAL
9809 149829U, // LDNT1SW_ZZR_D_REAL
9810 289093U, // LDNT1W_ZRI
9811 4677U, // LDNT1W_ZRR
9812 149829U, // LDNT1W_ZZR_D_REAL
9813 149829U, // LDNT1W_ZZR_S_REAL
9814 11018445U, // LDPDi
9815 12880205U, // LDPDpost
9816 180365645U, // LDPDpre
9817 11542733U, // LDPQi
9818 13404493U, // LDPQpost
9819 180889933U, // LDPQpre
9820 12067021U, // LDPSWi
9821 13928781U, // LDPSWpost
9822 181414221U, // LDPSWpre
9823 12067021U, // LDPSi
9824 13928781U, // LDPSpost
9825 181414221U, // LDPSpre
9826 12067021U, // LDPWi
9827 13928781U, // LDPWpost
9828 181414221U, // LDPWpre
9829 11018445U, // LDPXi
9830 12880205U, // LDPXpost
9831 180365645U, // LDPXpre
9832 4869U, // LDRAAindexed
9833 306437U, // LDRAAwriteback
9834 4869U, // LDRABindexed
9835 306437U, // LDRABwriteback
9836 2398U, // LDRBBpost
9837 305477U, // LDRBBpre
9838 14164165U, // LDRBBroW
9839 14688453U, // LDRBBroX
9840 4933U, // LDRBBui
9841 2398U, // LDRBpost
9842 305477U, // LDRBpre
9843 14164165U, // LDRBroW
9844 14688453U, // LDRBroX
9845 4933U, // LDRBui
9846 0U, // LDRDl
9847 2398U, // LDRDpost
9848 305477U, // LDRDpre
9849 15212741U, // LDRDroW
9850 15737029U, // LDRDroX
9851 4997U, // LDRDui
9852 2398U, // LDRHHpost
9853 305477U, // LDRHHpre
9854 16261317U, // LDRHHroW
9855 16785605U, // LDRHHroX
9856 5061U, // LDRHHui
9857 2398U, // LDRHpost
9858 305477U, // LDRHpre
9859 16261317U, // LDRHroW
9860 16785605U, // LDRHroX
9861 5061U, // LDRHui
9862 0U, // LDRQl
9863 2398U, // LDRQpost
9864 305477U, // LDRQpre
9865 17309893U, // LDRQroW
9866 17834181U, // LDRQroX
9867 5125U, // LDRQui
9868 2398U, // LDRSBWpost
9869 305477U, // LDRSBWpre
9870 14164165U, // LDRSBWroW
9871 14688453U, // LDRSBWroX
9872 4933U, // LDRSBWui
9873 2398U, // LDRSBXpost
9874 305477U, // LDRSBXpre
9875 14164165U, // LDRSBXroW
9876 14688453U, // LDRSBXroX
9877 4933U, // LDRSBXui
9878 2398U, // LDRSHWpost
9879 305477U, // LDRSHWpre
9880 16261317U, // LDRSHWroW
9881 16785605U, // LDRSHWroX
9882 5061U, // LDRSHWui
9883 2398U, // LDRSHXpost
9884 305477U, // LDRSHXpre
9885 16261317U, // LDRSHXroW
9886 16785605U, // LDRSHXroX
9887 5061U, // LDRSHXui
9888 0U, // LDRSWl
9889 2398U, // LDRSWpost
9890 305477U, // LDRSWpre
9891 18358469U, // LDRSWroW
9892 18882757U, // LDRSWroX
9893 5189U, // LDRSWui
9894 0U, // LDRSl
9895 2398U, // LDRSpost
9896 305477U, // LDRSpre
9897 18358469U, // LDRSroW
9898 18882757U, // LDRSroX
9899 5189U, // LDRSui
9900 0U, // LDRWl
9901 2398U, // LDRWpost
9902 305477U, // LDRWpre
9903 18358469U, // LDRWroW
9904 18882757U, // LDRWroX
9905 5189U, // LDRWui
9906 0U, // LDRXl
9907 2398U, // LDRXpost
9908 305477U, // LDRXpre
9909 15212741U, // LDRXroW
9910 15737029U, // LDRXroX
9911 4997U, // LDRXui
9912 286917U, // LDR_PXI
9913 286917U, // LDR_ZXI
9914 0U, // LDSETAB
9915 0U, // LDSETAH
9916 0U, // LDSETALB
9917 0U, // LDSETALH
9918 0U, // LDSETALW
9919 0U, // LDSETALX
9920 0U, // LDSETAW
9921 0U, // LDSETAX
9922 0U, // LDSETB
9923 0U, // LDSETH
9924 0U, // LDSETLB
9925 0U, // LDSETLH
9926 0U, // LDSETLW
9927 0U, // LDSETLX
9928 0U, // LDSETW
9929 0U, // LDSETX
9930 0U, // LDSMAXAB
9931 0U, // LDSMAXAH
9932 0U, // LDSMAXALB
9933 0U, // LDSMAXALH
9934 0U, // LDSMAXALW
9935 0U, // LDSMAXALX
9936 0U, // LDSMAXAW
9937 0U, // LDSMAXAX
9938 0U, // LDSMAXB
9939 0U, // LDSMAXH
9940 0U, // LDSMAXLB
9941 0U, // LDSMAXLH
9942 0U, // LDSMAXLW
9943 0U, // LDSMAXLX
9944 0U, // LDSMAXW
9945 0U, // LDSMAXX
9946 0U, // LDSMINAB
9947 0U, // LDSMINAH
9948 0U, // LDSMINALB
9949 0U, // LDSMINALH
9950 0U, // LDSMINALW
9951 0U, // LDSMINALX
9952 0U, // LDSMINAW
9953 0U, // LDSMINAX
9954 0U, // LDSMINB
9955 0U, // LDSMINH
9956 0U, // LDSMINLB
9957 0U, // LDSMINLH
9958 0U, // LDSMINLW
9959 0U, // LDSMINLX
9960 0U, // LDSMINW
9961 0U, // LDSMINX
9962 147653U, // LDTRBi
9963 147653U, // LDTRHi
9964 147653U, // LDTRSBWi
9965 147653U, // LDTRSBXi
9966 147653U, // LDTRSHWi
9967 147653U, // LDTRSHXi
9968 147653U, // LDTRSWi
9969 147653U, // LDTRWi
9970 147653U, // LDTRXi
9971 0U, // LDUMAXAB
9972 0U, // LDUMAXAH
9973 0U, // LDUMAXALB
9974 0U, // LDUMAXALH
9975 0U, // LDUMAXALW
9976 0U, // LDUMAXALX
9977 0U, // LDUMAXAW
9978 0U, // LDUMAXAX
9979 0U, // LDUMAXB
9980 0U, // LDUMAXH
9981 0U, // LDUMAXLB
9982 0U, // LDUMAXLH
9983 0U, // LDUMAXLW
9984 0U, // LDUMAXLX
9985 0U, // LDUMAXW
9986 0U, // LDUMAXX
9987 0U, // LDUMINAB
9988 0U, // LDUMINAH
9989 0U, // LDUMINALB
9990 0U, // LDUMINALH
9991 0U, // LDUMINALW
9992 0U, // LDUMINALX
9993 0U, // LDUMINAW
9994 0U, // LDUMINAX
9995 0U, // LDUMINB
9996 0U, // LDUMINH
9997 0U, // LDUMINLB
9998 0U, // LDUMINLH
9999 0U, // LDUMINLW
10000 0U, // LDUMINLX
10001 0U, // LDUMINW
10002 0U, // LDUMINX
10003 147653U, // LDURBBi
10004 147653U, // LDURBi
10005 147653U, // LDURDi
10006 147653U, // LDURHHi
10007 147653U, // LDURHi
10008 147653U, // LDURQi
10009 147653U, // LDURSBWi
10010 147653U, // LDURSBXi
10011 147653U, // LDURSHWi
10012 147653U, // LDURSHXi
10013 147653U, // LDURSWi
10014 147653U, // LDURSi
10015 147653U, // LDURWi
10016 147653U, // LDURXi
10017 147661U, // LDXPW
10018 147661U, // LDXPX
10019 29U, // LDXRB
10020 29U, // LDXRH
10021 29U, // LDXRW
10022 29U, // LDXRX
10023 533128U, // LSLR_ZPmZ_B
10024 1057160U, // LSLR_ZPmZ_D
10025 1614536U, // LSLR_ZPmZ_H
10026 2106120U, // LSLR_ZPmZ_S
10027 197U, // LSLVWr
10028 197U, // LSLVXr
10029 1057416U, // LSL_WIDE_ZPmZ_B
10030 99016U, // LSL_WIDE_ZPmZ_H
10031 1057544U, // LSL_WIDE_ZPmZ_S
10032 389U, // LSL_WIDE_ZZZ_B
10033 12U, // LSL_WIDE_ZZZ_H
10034 389U, // LSL_WIDE_ZZZ_S
10035 8840U, // LSL_ZPmI_B
10036 8584U, // LSL_ZPmI_D
10037 90824U, // LSL_ZPmI_H
10038 8968U, // LSL_ZPmI_S
10039 533128U, // LSL_ZPmZ_B
10040 1057160U, // LSL_ZPmZ_D
10041 1614536U, // LSL_ZPmZ_H
10042 2106120U, // LSL_ZPmZ_S
10043 197U, // LSL_ZZI_B
10044 197U, // LSL_ZZI_D
10045 12U, // LSL_ZZI_H
10046 197U, // LSL_ZZI_S
10047 533128U, // LSRR_ZPmZ_B
10048 1057160U, // LSRR_ZPmZ_D
10049 1614536U, // LSRR_ZPmZ_H
10050 2106120U, // LSRR_ZPmZ_S
10051 197U, // LSRVWr
10052 197U, // LSRVXr
10053 1057416U, // LSR_WIDE_ZPmZ_B
10054 99016U, // LSR_WIDE_ZPmZ_H
10055 1057544U, // LSR_WIDE_ZPmZ_S
10056 389U, // LSR_WIDE_ZZZ_B
10057 12U, // LSR_WIDE_ZZZ_H
10058 389U, // LSR_WIDE_ZZZ_S
10059 8840U, // LSR_ZPmI_B
10060 8584U, // LSR_ZPmI_D
10061 90824U, // LSR_ZPmI_H
10062 8968U, // LSR_ZPmI_S
10063 533128U, // LSR_ZPmZ_B
10064 1057160U, // LSR_ZPmZ_D
10065 1614536U, // LSR_ZPmZ_H
10066 2106120U, // LSR_ZPmZ_S
10067 197U, // LSR_ZZI_B
10068 197U, // LSR_ZZI_D
10069 12U, // LSR_ZZI_H
10070 197U, // LSR_ZZI_S
10071 8389U, // MADDWrrr
10072 8389U, // MADDXrrr
10073 5256U, // MAD_ZPmZZ_B
10074 8396872U, // MAD_ZPmZZ_D
10075 1811153U, // MAD_ZPmZZ_H
10076 8921224U, // MAD_ZPmZZ_S
10077 533131U, // MATCH_PPzZZ_B
10078 1614536U, // MATCH_PPzZZ_H
10079 5256U, // MLA_ZPmZZ_B
10080 8396872U, // MLA_ZPmZZ_D
10081 1811153U, // MLA_ZPmZZ_H
10082 8921224U, // MLA_ZPmZZ_S
10083 1695813U, // MLA_ZZZI_D
10084 2449U, // MLA_ZZZI_H
10085 1695877U, // MLA_ZZZI_S
10086 49737U, // MLAv16i8
10087 57929U, // MLAv2i32
10088 3392073U, // MLAv2i32_indexed
10089 66122U, // MLAv4i16
10090 3277386U, // MLAv4i16_indexed
10091 25159U, // MLAv4i32
10092 3392071U, // MLAv4i32_indexed
10093 33351U, // MLAv8i16
10094 3277383U, // MLAv8i16_indexed
10095 74314U, // MLAv8i8
10096 5256U, // MLS_ZPmZZ_B
10097 8396872U, // MLS_ZPmZZ_D
10098 1811153U, // MLS_ZPmZZ_H
10099 8921224U, // MLS_ZPmZZ_S
10100 1695813U, // MLS_ZZZI_D
10101 2449U, // MLS_ZZZI_H
10102 1695877U, // MLS_ZZZI_S
10103 49737U, // MLSv16i8
10104 57929U, // MLSv2i32
10105 3392073U, // MLSv2i32_indexed
10106 66122U, // MLSv4i16
10107 3277386U, // MLSv4i16_indexed
10108 25159U, // MLSv4i32
10109 3392071U, // MLSv4i32_indexed
10110 33351U, // MLSv8i16
10111 3277383U, // MLSv8i16_indexed
10112 74314U, // MLSv8i8
10113 0U, // MOVID
10114 2U, // MOVIv16b_ns
10115 0U, // MOVIv2d_ns
10116 30U, // MOVIv2i32
10117 30U, // MOVIv2s_msl
10118 30U, // MOVIv4i16
10119 30U, // MOVIv4i32
10120 30U, // MOVIv4s_msl
10121 2U, // MOVIv8b_ns
10122 30U, // MOVIv8i16
10123 0U, // MOVKWi
10124 0U, // MOVKXi
10125 30U, // MOVNWi
10126 30U, // MOVNXi
10127 0U, // MOVPRFX_ZPmZ_B
10128 0U, // MOVPRFX_ZPmZ_D
10129 0U, // MOVPRFX_ZPmZ_H
10130 1U, // MOVPRFX_ZPmZ_S
10131 651U, // MOVPRFX_ZPzZ_B
10132 395U, // MOVPRFX_ZPzZ_D
10133 8U, // MOVPRFX_ZPzZ_H
10134 779U, // MOVPRFX_ZPzZ_S
10135 2U, // MOVPRFX_ZZ
10136 30U, // MOVZWi
10137 30U, // MOVZXi
10138 0U, // MRS
10139 5256U, // MSB_ZPmZZ_B
10140 8396872U, // MSB_ZPmZZ_D
10141 1811153U, // MSB_ZPmZZ_H
10142 8921224U, // MSB_ZPmZZ_S
10143 0U, // MSR
10144 0U, // MSRpstateImm1
10145 0U, // MSRpstateImm4
10146 8389U, // MSUBWrrr
10147 8389U, // MSUBXrrr
10148 197U, // MUL_ZI_B
10149 197U, // MUL_ZI_D
10150 12U, // MUL_ZI_H
10151 197U, // MUL_ZI_S
10152 533128U, // MUL_ZPmZ_B
10153 1057160U, // MUL_ZPmZ_D
10154 1614536U, // MUL_ZPmZ_H
10155 2106120U, // MUL_ZPmZ_S
10156 278917U, // MUL_ZZZI_D
10157 2952U, // MUL_ZZZI_H
10158 279301U, // MUL_ZZZI_S
10159 645U, // MUL_ZZZ_B
10160 389U, // MUL_ZZZ_D
10161 8U, // MUL_ZZZ_H
10162 773U, // MUL_ZZZ_S
10163 49673U, // MULv16i8
10164 57865U, // MULv2i32
10165 10207753U, // MULv2i32_indexed
10166 66058U, // MULv4i16
10167 10093066U, // MULv4i16_indexed
10168 25095U, // MULv4i32
10169 10207751U, // MULv4i32_indexed
10170 33287U, // MULv8i16
10171 10093063U, // MULv8i16_indexed
10172 74250U, // MULv8i8
10173 30U, // MVNIv2i32
10174 30U, // MVNIv2s_msl
10175 30U, // MVNIv4i16
10176 30U, // MVNIv4i32
10177 30U, // MVNIv4s_msl
10178 30U, // MVNIv8i16
10179 533131U, // NANDS_PPzPP
10180 533131U, // NAND_PPzPP
10181 1057157U, // NBSL_ZZZZ
10182 0U, // NEG_ZPmZ_B
10183 0U, // NEG_ZPmZ_D
10184 0U, // NEG_ZPmZ_H
10185 1U, // NEG_ZPmZ_S
10186 1U, // NEGv16i8
10187 2U, // NEGv1i64
10188 2U, // NEGv2i32
10189 3U, // NEGv2i64
10190 3U, // NEGv4i16
10191 4U, // NEGv4i32
10192 4U, // NEGv8i16
10193 5U, // NEGv8i8
10194 533131U, // NMATCH_PPzZZ_B
10195 1614536U, // NMATCH_PPzZZ_H
10196 533131U, // NORS_PPzPP
10197 533131U, // NOR_PPzPP
10198 0U, // NOT_ZPmZ_B
10199 0U, // NOT_ZPmZ_D
10200 0U, // NOT_ZPmZ_H
10201 1U, // NOT_ZPmZ_S
10202 1U, // NOTv16i8
10203 5U, // NOTv8i8
10204 533131U, // ORNS_PPzPP
10205 901U, // ORNWrs
10206 901U, // ORNXrs
10207 533131U, // ORN_PPzPP
10208 49673U, // ORNv16i8
10209 74250U, // ORNv8i8
10210 533131U, // ORRS_PPzPP
10211 2245U, // ORRWri
10212 901U, // ORRWrs
10213 2309U, // ORRXri
10214 901U, // ORRXrs
10215 533131U, // ORR_PPzPP
10216 2309U, // ORR_ZI
10217 533128U, // ORR_ZPmZ_B
10218 1057160U, // ORR_ZPmZ_D
10219 1614536U, // ORR_ZPmZ_H
10220 2106120U, // ORR_ZPmZ_S
10221 389U, // ORR_ZZZ
10222 49673U, // ORRv16i8
10223 0U, // ORRv2i32
10224 0U, // ORRv4i16
10225 0U, // ORRv4i32
10226 0U, // ORRv8i16
10227 74250U, // ORRv8i8
10228 0U, // ORV_VPZ_B
10229 0U, // ORV_VPZ_D
10230 0U, // ORV_VPZ_H
10231 0U, // ORV_VPZ_S
10232 2U, // PACDA
10233 2U, // PACDB
10234 0U, // PACDZA
10235 0U, // PACDZB
10236 197U, // PACGA
10237 2U, // PACIA
10238 0U, // PACIA1716
10239 0U, // PACIASP
10240 0U, // PACIAZ
10241 2U, // PACIB
10242 0U, // PACIB1716
10243 0U, // PACIBSP
10244 0U, // PACIBZ
10245 0U, // PACIZA
10246 0U, // PACIZB
10247 0U, // PFALSE
10248 645U, // PFIRST_B
10249 773U, // PMULLB_ZZZ_D
10250 31U, // PMULLB_ZZZ_H
10251 0U, // PMULLB_ZZZ_Q
10252 773U, // PMULLT_ZZZ_D
10253 31U, // PMULLT_ZZZ_H
10254 0U, // PMULLT_ZZZ_Q
10255 49673U, // PMULLv16i8
10256 0U, // PMULLv1i64
10257 0U, // PMULLv2i64
10258 74250U, // PMULLv8i8
10259 645U, // PMUL_ZZZ_B
10260 49673U, // PMULv16i8
10261 74250U, // PMULv8i8
10262 645U, // PNEXT_B
10263 389U, // PNEXT_D
10264 8U, // PNEXT_H
10265 773U, // PNEXT_S
10266 5332U, // PRFB_D_PZI
10267 31U, // PRFB_D_SCALED
10268 32U, // PRFB_D_SXTW_SCALED
10269 32U, // PRFB_D_UXTW_SCALED
10270 5396U, // PRFB_PRI
10271 33U, // PRFB_PRR
10272 5332U, // PRFB_S_PZI
10273 33U, // PRFB_S_SXTW_SCALED
10274 34U, // PRFB_S_UXTW_SCALED
10275 34U, // PRFD_D_PZI
10276 35U, // PRFD_D_SCALED
10277 35U, // PRFD_D_SXTW_SCALED
10278 36U, // PRFD_D_UXTW_SCALED
10279 5396U, // PRFD_PRI
10280 36U, // PRFD_PRR
10281 34U, // PRFD_S_PZI
10282 37U, // PRFD_S_SXTW_SCALED
10283 37U, // PRFD_S_UXTW_SCALED
10284 38U, // PRFH_D_PZI
10285 38U, // PRFH_D_SCALED
10286 39U, // PRFH_D_SXTW_SCALED
10287 39U, // PRFH_D_UXTW_SCALED
10288 5396U, // PRFH_PRI
10289 40U, // PRFH_PRR
10290 38U, // PRFH_S_PZI
10291 40U, // PRFH_S_SXTW_SCALED
10292 41U, // PRFH_S_UXTW_SCALED
10293 0U, // PRFMl
10294 15212741U, // PRFMroW
10295 15737029U, // PRFMroX
10296 4997U, // PRFMui
10297 41U, // PRFS_PRR
10298 147653U, // PRFUMi
10299 42U, // PRFW_D_PZI
10300 42U, // PRFW_D_SCALED
10301 43U, // PRFW_D_SXTW_SCALED
10302 43U, // PRFW_D_UXTW_SCALED
10303 5396U, // PRFW_PRI
10304 42U, // PRFW_S_PZI
10305 44U, // PRFW_S_SXTW_SCALED
10306 44U, // PRFW_S_UXTW_SCALED
10307 2U, // PTEST_PP
10308 2U, // PTRUES_B
10309 2U, // PTRUES_D
10310 0U, // PTRUES_H
10311 2U, // PTRUES_S
10312 2U, // PTRUE_B
10313 2U, // PTRUE_D
10314 0U, // PTRUE_H
10315 2U, // PTRUE_S
10316 0U, // PUNPKHI_PP
10317 0U, // PUNPKLO_PP
10318 325U, // RADDHNB_ZZZ_B
10319 6U, // RADDHNB_ZZZ_H
10320 389U, // RADDHNB_ZZZ_S
10321 453U, // RADDHNT_ZZZ_B
10322 1U, // RADDHNT_ZZZ_H
10323 69U, // RADDHNT_ZZZ_S
10324 16902U, // RADDHNv2i64_v2i32
10325 16966U, // RADDHNv2i64_v4i32
10326 25095U, // RADDHNv4i32_v4i16
10327 25159U, // RADDHNv4i32_v8i16
10328 33351U, // RADDHNv8i16_v16i8
10329 33287U, // RADDHNv8i16_v8i8
10330 16902U, // RAX1
10331 389U, // RAX1_ZZZ_D
10332 2U, // RBITWr
10333 2U, // RBITXr
10334 0U, // RBIT_ZPmZ_B
10335 0U, // RBIT_ZPmZ_D
10336 0U, // RBIT_ZPmZ_H
10337 1U, // RBIT_ZPmZ_S
10338 1U, // RBITv16i8
10339 5U, // RBITv8i8
10340 45U, // RDFFRS_PPz
10341 45U, // RDFFR_PPz_REAL
10342 0U, // RDFFR_P_REAL
10343 2U, // RDVLI_XI
10344 0U, // RET
10345 0U, // RETAA
10346 0U, // RETAB
10347 2U, // REV16Wr
10348 2U, // REV16Xr
10349 1U, // REV16v16i8
10350 5U, // REV16v8i8
10351 2U, // REV32Xr
10352 1U, // REV32v16i8
10353 3U, // REV32v4i16
10354 4U, // REV32v8i16
10355 5U, // REV32v8i8
10356 1U, // REV64v16i8
10357 2U, // REV64v2i32
10358 3U, // REV64v4i16
10359 4U, // REV64v4i32
10360 4U, // REV64v8i16
10361 5U, // REV64v8i8
10362 0U, // REVB_ZPmZ_D
10363 0U, // REVB_ZPmZ_H
10364 1U, // REVB_ZPmZ_S
10365 0U, // REVH_ZPmZ_D
10366 1U, // REVH_ZPmZ_S
10367 0U, // REVW_ZPmZ_D
10368 2U, // REVWr
10369 2U, // REVXr
10370 2U, // REV_PP_B
10371 2U, // REV_PP_D
10372 0U, // REV_PP_H
10373 2U, // REV_PP_S
10374 2U, // REV_ZZ_B
10375 2U, // REV_ZZ_D
10376 0U, // REV_ZZ_H
10377 2U, // REV_ZZ_S
10378 197U, // RMIF
10379 197U, // RORVWr
10380 197U, // RORVXr
10381 197U, // RSHRNB_ZZI_B
10382 12U, // RSHRNB_ZZI_H
10383 197U, // RSHRNB_ZZI_S
10384 2373U, // RSHRNT_ZZI_B
10385 20U, // RSHRNT_ZZI_H
10386 2373U, // RSHRNT_ZZI_S
10387 2375U, // RSHRNv16i8_shift
10388 198U, // RSHRNv2i32_shift
10389 199U, // RSHRNv4i16_shift
10390 2374U, // RSHRNv4i32_shift
10391 2375U, // RSHRNv8i16_shift
10392 199U, // RSHRNv8i8_shift
10393 325U, // RSUBHNB_ZZZ_B
10394 6U, // RSUBHNB_ZZZ_H
10395 389U, // RSUBHNB_ZZZ_S
10396 453U, // RSUBHNT_ZZZ_B
10397 1U, // RSUBHNT_ZZZ_H
10398 69U, // RSUBHNT_ZZZ_S
10399 16902U, // RSUBHNv2i64_v2i32
10400 16966U, // RSUBHNv2i64_v4i32
10401 25095U, // RSUBHNv4i32_v4i16
10402 25159U, // RSUBHNv4i32_v8i16
10403 33351U, // RSUBHNv8i16_v16i8
10404 33287U, // RSUBHNv8i16_v8i8
10405 133U, // SABALB_ZZZ_D
10406 0U, // SABALB_ZZZ_H
10407 453U, // SABALB_ZZZ_S
10408 133U, // SABALT_ZZZ_D
10409 0U, // SABALT_ZZZ_H
10410 453U, // SABALT_ZZZ_S
10411 49737U, // SABALv16i8_v8i16
10412 57929U, // SABALv2i32_v2i64
10413 66122U, // SABALv4i16_v4i32
10414 25159U, // SABALv4i32_v2i64
10415 33351U, // SABALv8i16_v4i32
10416 74314U, // SABALv8i8_v8i16
10417 0U, // SABA_ZZZ_B
10418 69U, // SABA_ZZZ_D
10419 17U, // SABA_ZZZ_H
10420 133U, // SABA_ZZZ_S
10421 49737U, // SABAv16i8
10422 57929U, // SABAv2i32
10423 66122U, // SABAv4i16
10424 25159U, // SABAv4i32
10425 33351U, // SABAv8i16
10426 74314U, // SABAv8i8
10427 773U, // SABDLB_ZZZ_D
10428 31U, // SABDLB_ZZZ_H
10429 325U, // SABDLB_ZZZ_S
10430 773U, // SABDLT_ZZZ_D
10431 31U, // SABDLT_ZZZ_H
10432 325U, // SABDLT_ZZZ_S
10433 49673U, // SABDLv16i8_v8i16
10434 57865U, // SABDLv2i32_v2i64
10435 66058U, // SABDLv4i16_v4i32
10436 25095U, // SABDLv4i32_v2i64
10437 33287U, // SABDLv8i16_v4i32
10438 74250U, // SABDLv8i8_v8i16
10439 533128U, // SABD_ZPmZ_B
10440 1057160U, // SABD_ZPmZ_D
10441 1614536U, // SABD_ZPmZ_H
10442 2106120U, // SABD_ZPmZ_S
10443 49673U, // SABDv16i8
10444 57865U, // SABDv2i32
10445 66058U, // SABDv4i16
10446 25095U, // SABDv4i32
10447 33287U, // SABDv8i16
10448 74250U, // SABDv8i8
10449 136U, // SADALP_ZPmZ_D
10450 0U, // SADALP_ZPmZ_H
10451 456U, // SADALP_ZPmZ_S
10452 1U, // SADALPv16i8_v8i16
10453 2U, // SADALPv2i32_v1i64
10454 3U, // SADALPv4i16_v2i32
10455 4U, // SADALPv4i32_v2i64
10456 4U, // SADALPv8i16_v4i32
10457 5U, // SADALPv8i8_v4i16
10458 773U, // SADDLBT_ZZZ_D
10459 31U, // SADDLBT_ZZZ_H
10460 325U, // SADDLBT_ZZZ_S
10461 773U, // SADDLB_ZZZ_D
10462 31U, // SADDLB_ZZZ_H
10463 325U, // SADDLB_ZZZ_S
10464 1U, // SADDLPv16i8_v8i16
10465 2U, // SADDLPv2i32_v1i64
10466 3U, // SADDLPv4i16_v2i32
10467 4U, // SADDLPv4i32_v2i64
10468 4U, // SADDLPv8i16_v4i32
10469 5U, // SADDLPv8i8_v4i16
10470 773U, // SADDLT_ZZZ_D
10471 31U, // SADDLT_ZZZ_H
10472 325U, // SADDLT_ZZZ_S
10473 1U, // SADDLVv16i8v
10474 3U, // SADDLVv4i16v
10475 4U, // SADDLVv4i32v
10476 4U, // SADDLVv8i16v
10477 5U, // SADDLVv8i8v
10478 49673U, // SADDLv16i8_v8i16
10479 57865U, // SADDLv2i32_v2i64
10480 66058U, // SADDLv4i16_v4i32
10481 25095U, // SADDLv4i32_v2i64
10482 33287U, // SADDLv8i16_v4i32
10483 74250U, // SADDLv8i8_v8i16
10484 0U, // SADDV_VPZ_B
10485 0U, // SADDV_VPZ_H
10486 0U, // SADDV_VPZ_S
10487 773U, // SADDWB_ZZZ_D
10488 31U, // SADDWB_ZZZ_H
10489 325U, // SADDWB_ZZZ_S
10490 773U, // SADDWT_ZZZ_D
10491 31U, // SADDWT_ZZZ_H
10492 325U, // SADDWT_ZZZ_S
10493 49671U, // SADDWv16i8_v8i16
10494 57862U, // SADDWv2i32_v2i64
10495 66055U, // SADDWv4i16_v4i32
10496 25094U, // SADDWv4i32_v2i64
10497 33287U, // SADDWv8i16_v4i32
10498 74247U, // SADDWv8i8_v8i16
10499 0U, // SB
10500 69U, // SBCLB_ZZZ_D
10501 133U, // SBCLB_ZZZ_S
10502 69U, // SBCLT_ZZZ_D
10503 133U, // SBCLT_ZZZ_S
10504 197U, // SBCSWr
10505 197U, // SBCSXr
10506 197U, // SBCWr
10507 197U, // SBCXr
10508 8389U, // SBFMWri
10509 8389U, // SBFMXri
10510 197U, // SCVTFSWDri
10511 197U, // SCVTFSWHri
10512 197U, // SCVTFSWSri
10513 197U, // SCVTFSXDri
10514 197U, // SCVTFSXHri
10515 197U, // SCVTFSXSri
10516 2U, // SCVTFUWDri
10517 2U, // SCVTFUWHri
10518 2U, // SCVTFUWSri
10519 2U, // SCVTFUXDri
10520 2U, // SCVTFUXHri
10521 2U, // SCVTFUXSri
10522 0U, // SCVTF_ZPmZ_DtoD
10523 0U, // SCVTF_ZPmZ_DtoH
10524 0U, // SCVTF_ZPmZ_DtoS
10525 0U, // SCVTF_ZPmZ_HtoH
10526 1U, // SCVTF_ZPmZ_StoD
10527 0U, // SCVTF_ZPmZ_StoH
10528 1U, // SCVTF_ZPmZ_StoS
10529 197U, // SCVTFd
10530 197U, // SCVTFh
10531 197U, // SCVTFs
10532 2U, // SCVTFv1i16
10533 2U, // SCVTFv1i32
10534 2U, // SCVTFv1i64
10535 2U, // SCVTFv2f32
10536 3U, // SCVTFv2f64
10537 201U, // SCVTFv2i32_shift
10538 198U, // SCVTFv2i64_shift
10539 3U, // SCVTFv4f16
10540 4U, // SCVTFv4f32
10541 202U, // SCVTFv4i16_shift
10542 199U, // SCVTFv4i32_shift
10543 4U, // SCVTFv8f16
10544 199U, // SCVTFv8i16_shift
10545 1057160U, // SDIVR_ZPmZ_D
10546 2106120U, // SDIVR_ZPmZ_S
10547 197U, // SDIVWr
10548 197U, // SDIVXr
10549 1057160U, // SDIV_ZPmZ_D
10550 2106120U, // SDIV_ZPmZ_S
10551 1696197U, // SDOT_ZZZI_D
10552 2432U, // SDOT_ZZZI_S
10553 453U, // SDOT_ZZZ_D
10554 0U, // SDOT_ZZZ_S
10555 311881U, // SDOTlanev16i8
10556 311882U, // SDOTlanev8i8
10557 49737U, // SDOTv16i8
10558 74314U, // SDOTv8i8
10559 533125U, // SEL_PPPP
10560 533125U, // SEL_ZPZZ_B
10561 1057157U, // SEL_ZPZZ_D
10562 1614536U, // SEL_ZPZZ_H
10563 2106117U, // SEL_ZPZZ_S
10564 0U, // SETF16
10565 0U, // SETF8
10566 0U, // SETFFR
10567 25157U, // SHA1Crrr
10568 2U, // SHA1Hrr
10569 25157U, // SHA1Mrrr
10570 25157U, // SHA1Prrr
10571 25159U, // SHA1SU0rrr
10572 4U, // SHA1SU1rr
10573 25157U, // SHA256H2rrr
10574 25157U, // SHA256Hrrr
10575 4U, // SHA256SU0rr
10576 25159U, // SHA256SU1rrr
10577 16965U, // SHA512H
10578 16965U, // SHA512H2
10579 3U, // SHA512SU0
10580 16966U, // SHA512SU1
10581 533128U, // SHADD_ZPmZ_B
10582 1057160U, // SHADD_ZPmZ_D
10583 1614536U, // SHADD_ZPmZ_H
10584 2106120U, // SHADD_ZPmZ_S
10585 49673U, // SHADDv16i8
10586 57865U, // SHADDv2i32
10587 66058U, // SHADDv4i16
10588 25095U, // SHADDv4i32
10589 33287U, // SHADDv8i16
10590 74250U, // SHADDv8i8
10591 45U, // SHLLv16i8
10592 46U, // SHLLv2i32
10593 46U, // SHLLv4i16
10594 47U, // SHLLv4i32
10595 47U, // SHLLv8i16
10596 48U, // SHLLv8i8
10597 197U, // SHLd
10598 201U, // SHLv16i8_shift
10599 201U, // SHLv2i32_shift
10600 198U, // SHLv2i64_shift
10601 202U, // SHLv4i16_shift
10602 199U, // SHLv4i32_shift
10603 199U, // SHLv8i16_shift
10604 202U, // SHLv8i8_shift
10605 197U, // SHRNB_ZZI_B
10606 12U, // SHRNB_ZZI_H
10607 197U, // SHRNB_ZZI_S
10608 2373U, // SHRNT_ZZI_B
10609 20U, // SHRNT_ZZI_H
10610 2373U, // SHRNT_ZZI_S
10611 2375U, // SHRNv16i8_shift
10612 198U, // SHRNv2i32_shift
10613 199U, // SHRNv4i16_shift
10614 2374U, // SHRNv4i32_shift
10615 2375U, // SHRNv8i16_shift
10616 199U, // SHRNv8i8_shift
10617 533128U, // SHSUBR_ZPmZ_B
10618 1057160U, // SHSUBR_ZPmZ_D
10619 1614536U, // SHSUBR_ZPmZ_H
10620 2106120U, // SHSUBR_ZPmZ_S
10621 533128U, // SHSUB_ZPmZ_B
10622 1057160U, // SHSUB_ZPmZ_D
10623 1614536U, // SHSUB_ZPmZ_H
10624 2106120U, // SHSUB_ZPmZ_S
10625 49673U, // SHSUBv16i8
10626 57865U, // SHSUBv2i32
10627 66058U, // SHSUBv4i16
10628 25095U, // SHSUBv4i32
10629 33287U, // SHSUBv8i16
10630 74250U, // SHSUBv8i8
10631 20U, // SLI_ZZI_B
10632 2373U, // SLI_ZZI_D
10633 20U, // SLI_ZZI_H
10634 2373U, // SLI_ZZI_S
10635 2373U, // SLId
10636 2377U, // SLIv16i8_shift
10637 2377U, // SLIv2i32_shift
10638 2374U, // SLIv2i64_shift
10639 2378U, // SLIv4i16_shift
10640 2375U, // SLIv4i32_shift
10641 2375U, // SLIv8i16_shift
10642 2378U, // SLIv8i8_shift
10643 25159U, // SM3PARTW1
10644 25159U, // SM3PARTW2
10645 204161543U, // SM3SS1
10646 3392071U, // SM3TT1A
10647 3392071U, // SM3TT1B
10648 3392071U, // SM3TT2A
10649 3392071U, // SM3TT2B
10650 4U, // SM4E
10651 773U, // SM4EKEY_ZZZ_S
10652 25095U, // SM4ENCKEY
10653 773U, // SM4E_ZZZ_S
10654 8389U, // SMADDLrrr
10655 533128U, // SMAXP_ZPmZ_B
10656 1057160U, // SMAXP_ZPmZ_D
10657 1614536U, // SMAXP_ZPmZ_H
10658 2106120U, // SMAXP_ZPmZ_S
10659 49673U, // SMAXPv16i8
10660 57865U, // SMAXPv2i32
10661 66058U, // SMAXPv4i16
10662 25095U, // SMAXPv4i32
10663 33287U, // SMAXPv8i16
10664 74250U, // SMAXPv8i8
10665 0U, // SMAXV_VPZ_B
10666 0U, // SMAXV_VPZ_D
10667 0U, // SMAXV_VPZ_H
10668 0U, // SMAXV_VPZ_S
10669 1U, // SMAXVv16i8v
10670 3U, // SMAXVv4i16v
10671 4U, // SMAXVv4i32v
10672 4U, // SMAXVv8i16v
10673 5U, // SMAXVv8i8v
10674 197U, // SMAX_ZI_B
10675 197U, // SMAX_ZI_D
10676 12U, // SMAX_ZI_H
10677 197U, // SMAX_ZI_S
10678 533128U, // SMAX_ZPmZ_B
10679 1057160U, // SMAX_ZPmZ_D
10680 1614536U, // SMAX_ZPmZ_H
10681 2106120U, // SMAX_ZPmZ_S
10682 49673U, // SMAXv16i8
10683 57865U, // SMAXv2i32
10684 66058U, // SMAXv4i16
10685 25095U, // SMAXv4i32
10686 33287U, // SMAXv8i16
10687 74250U, // SMAXv8i8
10688 0U, // SMC
10689 533128U, // SMINP_ZPmZ_B
10690 1057160U, // SMINP_ZPmZ_D
10691 1614536U, // SMINP_ZPmZ_H
10692 2106120U, // SMINP_ZPmZ_S
10693 49673U, // SMINPv16i8
10694 57865U, // SMINPv2i32
10695 66058U, // SMINPv4i16
10696 25095U, // SMINPv4i32
10697 33287U, // SMINPv8i16
10698 74250U, // SMINPv8i8
10699 0U, // SMINV_VPZ_B
10700 0U, // SMINV_VPZ_D
10701 0U, // SMINV_VPZ_H
10702 0U, // SMINV_VPZ_S
10703 1U, // SMINVv16i8v
10704 3U, // SMINVv4i16v
10705 4U, // SMINVv4i32v
10706 4U, // SMINVv8i16v
10707 5U, // SMINVv8i8v
10708 197U, // SMIN_ZI_B
10709 197U, // SMIN_ZI_D
10710 12U, // SMIN_ZI_H
10711 197U, // SMIN_ZI_S
10712 533128U, // SMIN_ZPmZ_B
10713 1057160U, // SMIN_ZPmZ_D
10714 1614536U, // SMIN_ZPmZ_H
10715 2106120U, // SMIN_ZPmZ_S
10716 49673U, // SMINv16i8
10717 57865U, // SMINv2i32
10718 66058U, // SMINv4i16
10719 25095U, // SMINv4i32
10720 33287U, // SMINv8i16
10721 74250U, // SMINv8i8
10722 1695877U, // SMLALB_ZZZI_D
10723 1696197U, // SMLALB_ZZZI_S
10724 133U, // SMLALB_ZZZ_D
10725 0U, // SMLALB_ZZZ_H
10726 453U, // SMLALB_ZZZ_S
10727 1695877U, // SMLALT_ZZZI_D
10728 1696197U, // SMLALT_ZZZI_S
10729 133U, // SMLALT_ZZZ_D
10730 0U, // SMLALT_ZZZ_H
10731 453U, // SMLALT_ZZZ_S
10732 49737U, // SMLALv16i8_v8i16
10733 3392073U, // SMLALv2i32_indexed
10734 57929U, // SMLALv2i32_v2i64
10735 3277386U, // SMLALv4i16_indexed
10736 66122U, // SMLALv4i16_v4i32
10737 3392071U, // SMLALv4i32_indexed
10738 25159U, // SMLALv4i32_v2i64
10739 3277383U, // SMLALv8i16_indexed
10740 33351U, // SMLALv8i16_v4i32
10741 74314U, // SMLALv8i8_v8i16
10742 1695877U, // SMLSLB_ZZZI_D
10743 1696197U, // SMLSLB_ZZZI_S
10744 133U, // SMLSLB_ZZZ_D
10745 0U, // SMLSLB_ZZZ_H
10746 453U, // SMLSLB_ZZZ_S
10747 1695877U, // SMLSLT_ZZZI_D
10748 1696197U, // SMLSLT_ZZZI_S
10749 133U, // SMLSLT_ZZZ_D
10750 0U, // SMLSLT_ZZZ_H
10751 453U, // SMLSLT_ZZZ_S
10752 49737U, // SMLSLv16i8_v8i16
10753 3392073U, // SMLSLv2i32_indexed
10754 57929U, // SMLSLv2i32_v2i64
10755 3277386U, // SMLSLv4i16_indexed
10756 66122U, // SMLSLv4i16_v4i32
10757 3392071U, // SMLSLv4i32_indexed
10758 25159U, // SMLSLv4i32_v2i64
10759 3277383U, // SMLSLv8i16_indexed
10760 33351U, // SMLSLv8i16_v4i32
10761 74314U, // SMLSLv8i8_v8i16
10762 49737U, // SMMLA
10763 0U, // SMMLA_ZZZ
10764 2709U, // SMOVvi16to32
10765 2709U, // SMOVvi16to64
10766 2709U, // SMOVvi32to64
10767 2710U, // SMOVvi8to32
10768 2710U, // SMOVvi8to64
10769 8389U, // SMSUBLrrr
10770 533128U, // SMULH_ZPmZ_B
10771 1057160U, // SMULH_ZPmZ_D
10772 1614536U, // SMULH_ZPmZ_H
10773 2106120U, // SMULH_ZPmZ_S
10774 645U, // SMULH_ZZZ_B
10775 389U, // SMULH_ZZZ_D
10776 8U, // SMULH_ZZZ_H
10777 773U, // SMULH_ZZZ_S
10778 197U, // SMULHrr
10779 279301U, // SMULLB_ZZZI_D
10780 278853U, // SMULLB_ZZZI_S
10781 773U, // SMULLB_ZZZ_D
10782 31U, // SMULLB_ZZZ_H
10783 325U, // SMULLB_ZZZ_S
10784 279301U, // SMULLT_ZZZI_D
10785 278853U, // SMULLT_ZZZI_S
10786 773U, // SMULLT_ZZZ_D
10787 31U, // SMULLT_ZZZ_H
10788 325U, // SMULLT_ZZZ_S
10789 49673U, // SMULLv16i8_v8i16
10790 10207753U, // SMULLv2i32_indexed
10791 57865U, // SMULLv2i32_v2i64
10792 10093066U, // SMULLv4i16_indexed
10793 66058U, // SMULLv4i16_v4i32
10794 10207751U, // SMULLv4i32_indexed
10795 25095U, // SMULLv4i32_v2i64
10796 10093063U, // SMULLv8i16_indexed
10797 33287U, // SMULLv8i16_v4i32
10798 74250U, // SMULLv8i8_v8i16
10799 5445U, // SPLICE_ZPZZ_B
10800 5509U, // SPLICE_ZPZZ_D
10801 48U, // SPLICE_ZPZZ_H
10802 5573U, // SPLICE_ZPZZ_S
10803 533125U, // SPLICE_ZPZ_B
10804 1057157U, // SPLICE_ZPZ_D
10805 1614536U, // SPLICE_ZPZ_H
10806 2106117U, // SPLICE_ZPZ_S
10807 0U, // SQABS_ZPmZ_B
10808 0U, // SQABS_ZPmZ_D
10809 0U, // SQABS_ZPmZ_H
10810 1U, // SQABS_ZPmZ_S
10811 1U, // SQABSv16i8
10812 2U, // SQABSv1i16
10813 2U, // SQABSv1i32
10814 2U, // SQABSv1i64
10815 2U, // SQABSv1i8
10816 2U, // SQABSv2i32
10817 3U, // SQABSv2i64
10818 3U, // SQABSv4i16
10819 4U, // SQABSv4i32
10820 4U, // SQABSv8i16
10821 5U, // SQABSv8i8
10822 1029U, // SQADD_ZI_B
10823 1093U, // SQADD_ZI_D
10824 11U, // SQADD_ZI_H
10825 1157U, // SQADD_ZI_S
10826 533128U, // SQADD_ZPmZ_B
10827 1057160U, // SQADD_ZPmZ_D
10828 1614536U, // SQADD_ZPmZ_H
10829 2106120U, // SQADD_ZPmZ_S
10830 645U, // SQADD_ZZZ_B
10831 389U, // SQADD_ZZZ_D
10832 8U, // SQADD_ZZZ_H
10833 773U, // SQADD_ZZZ_S
10834 49673U, // SQADDv16i8
10835 197U, // SQADDv1i16
10836 197U, // SQADDv1i32
10837 197U, // SQADDv1i64
10838 197U, // SQADDv1i8
10839 57865U, // SQADDv2i32
10840 16902U, // SQADDv2i64
10841 66058U, // SQADDv4i16
10842 25095U, // SQADDv4i32
10843 33287U, // SQADDv8i16
10844 74250U, // SQADDv8i8
10845 4203141U, // SQCADD_ZZI_B
10846 4202885U, // SQCADD_ZZI_D
10847 139976U, // SQCADD_ZZI_H
10848 4203269U, // SQCADD_ZZI_S
10849 0U, // SQDECB_XPiI
10850 0U, // SQDECB_XPiWdI
10851 0U, // SQDECD_XPiI
10852 0U, // SQDECD_XPiWdI
10853 0U, // SQDECD_ZPiI
10854 0U, // SQDECH_XPiI
10855 0U, // SQDECH_XPiWdI
10856 0U, // SQDECH_ZPiI
10857 5637U, // SQDECP_XPWd_B
10858 5637U, // SQDECP_XPWd_D
10859 5637U, // SQDECP_XPWd_H
10860 5637U, // SQDECP_XPWd_S
10861 2U, // SQDECP_XP_B
10862 2U, // SQDECP_XP_D
10863 2U, // SQDECP_XP_H
10864 2U, // SQDECP_XP_S
10865 2U, // SQDECP_ZP_D
10866 0U, // SQDECP_ZP_H
10867 2U, // SQDECP_ZP_S
10868 0U, // SQDECW_XPiI
10869 0U, // SQDECW_XPiWdI
10870 0U, // SQDECW_ZPiI
10871 133U, // SQDMLALBT_ZZZ_D
10872 0U, // SQDMLALBT_ZZZ_H
10873 453U, // SQDMLALBT_ZZZ_S
10874 1695877U, // SQDMLALB_ZZZI_D
10875 1696197U, // SQDMLALB_ZZZI_S
10876 133U, // SQDMLALB_ZZZ_D
10877 0U, // SQDMLALB_ZZZ_H
10878 453U, // SQDMLALB_ZZZ_S
10879 1695877U, // SQDMLALT_ZZZI_D
10880 1696197U, // SQDMLALT_ZZZI_S
10881 133U, // SQDMLALT_ZZZ_D
10882 0U, // SQDMLALT_ZZZ_H
10883 453U, // SQDMLALT_ZZZ_S
10884 2373U, // SQDMLALi16
10885 2373U, // SQDMLALi32
10886 3277381U, // SQDMLALv1i32_indexed
10887 3392069U, // SQDMLALv1i64_indexed
10888 3392073U, // SQDMLALv2i32_indexed
10889 57929U, // SQDMLALv2i32_v2i64
10890 3277386U, // SQDMLALv4i16_indexed
10891 66122U, // SQDMLALv4i16_v4i32
10892 3392071U, // SQDMLALv4i32_indexed
10893 25159U, // SQDMLALv4i32_v2i64
10894 3277383U, // SQDMLALv8i16_indexed
10895 33351U, // SQDMLALv8i16_v4i32
10896 133U, // SQDMLSLBT_ZZZ_D
10897 0U, // SQDMLSLBT_ZZZ_H
10898 453U, // SQDMLSLBT_ZZZ_S
10899 1695877U, // SQDMLSLB_ZZZI_D
10900 1696197U, // SQDMLSLB_ZZZI_S
10901 133U, // SQDMLSLB_ZZZ_D
10902 0U, // SQDMLSLB_ZZZ_H
10903 453U, // SQDMLSLB_ZZZ_S
10904 1695877U, // SQDMLSLT_ZZZI_D
10905 1696197U, // SQDMLSLT_ZZZI_S
10906 133U, // SQDMLSLT_ZZZ_D
10907 0U, // SQDMLSLT_ZZZ_H
10908 453U, // SQDMLSLT_ZZZ_S
10909 2373U, // SQDMLSLi16
10910 2373U, // SQDMLSLi32
10911 3277381U, // SQDMLSLv1i32_indexed
10912 3392069U, // SQDMLSLv1i64_indexed
10913 3392073U, // SQDMLSLv2i32_indexed
10914 57929U, // SQDMLSLv2i32_v2i64
10915 3277386U, // SQDMLSLv4i16_indexed
10916 66122U, // SQDMLSLv4i16_v4i32
10917 3392071U, // SQDMLSLv4i32_indexed
10918 25159U, // SQDMLSLv4i32_v2i64
10919 3277383U, // SQDMLSLv8i16_indexed
10920 33351U, // SQDMLSLv8i16_v4i32
10921 278917U, // SQDMULH_ZZZI_D
10922 2952U, // SQDMULH_ZZZI_H
10923 279301U, // SQDMULH_ZZZI_S
10924 645U, // SQDMULH_ZZZ_B
10925 389U, // SQDMULH_ZZZ_D
10926 8U, // SQDMULH_ZZZ_H
10927 773U, // SQDMULH_ZZZ_S
10928 197U, // SQDMULHv1i16
10929 10093061U, // SQDMULHv1i16_indexed
10930 197U, // SQDMULHv1i32
10931 10207749U, // SQDMULHv1i32_indexed
10932 57865U, // SQDMULHv2i32
10933 10207753U, // SQDMULHv2i32_indexed
10934 66058U, // SQDMULHv4i16
10935 10093066U, // SQDMULHv4i16_indexed
10936 25095U, // SQDMULHv4i32
10937 10207751U, // SQDMULHv4i32_indexed
10938 33287U, // SQDMULHv8i16
10939 10093063U, // SQDMULHv8i16_indexed
10940 279301U, // SQDMULLB_ZZZI_D
10941 278853U, // SQDMULLB_ZZZI_S
10942 773U, // SQDMULLB_ZZZ_D
10943 31U, // SQDMULLB_ZZZ_H
10944 325U, // SQDMULLB_ZZZ_S
10945 279301U, // SQDMULLT_ZZZI_D
10946 278853U, // SQDMULLT_ZZZI_S
10947 773U, // SQDMULLT_ZZZ_D
10948 31U, // SQDMULLT_ZZZ_H
10949 325U, // SQDMULLT_ZZZ_S
10950 197U, // SQDMULLi16
10951 197U, // SQDMULLi32
10952 10093061U, // SQDMULLv1i32_indexed
10953 10207749U, // SQDMULLv1i64_indexed
10954 10207753U, // SQDMULLv2i32_indexed
10955 57865U, // SQDMULLv2i32_v2i64
10956 10093066U, // SQDMULLv4i16_indexed
10957 66058U, // SQDMULLv4i16_v4i32
10958 10207751U, // SQDMULLv4i32_indexed
10959 25095U, // SQDMULLv4i32_v2i64
10960 10093063U, // SQDMULLv8i16_indexed
10961 33287U, // SQDMULLv8i16_v4i32
10962 0U, // SQINCB_XPiI
10963 0U, // SQINCB_XPiWdI
10964 0U, // SQINCD_XPiI
10965 0U, // SQINCD_XPiWdI
10966 0U, // SQINCD_ZPiI
10967 0U, // SQINCH_XPiI
10968 0U, // SQINCH_XPiWdI
10969 0U, // SQINCH_ZPiI
10970 5637U, // SQINCP_XPWd_B
10971 5637U, // SQINCP_XPWd_D
10972 5637U, // SQINCP_XPWd_H
10973 5637U, // SQINCP_XPWd_S
10974 2U, // SQINCP_XP_B
10975 2U, // SQINCP_XP_D
10976 2U, // SQINCP_XP_H
10977 2U, // SQINCP_XP_S
10978 2U, // SQINCP_ZP_D
10979 0U, // SQINCP_ZP_H
10980 2U, // SQINCP_ZP_S
10981 0U, // SQINCW_XPiI
10982 0U, // SQINCW_XPiWdI
10983 0U, // SQINCW_ZPiI
10984 0U, // SQNEG_ZPmZ_B
10985 0U, // SQNEG_ZPmZ_D
10986 0U, // SQNEG_ZPmZ_H
10987 1U, // SQNEG_ZPmZ_S
10988 1U, // SQNEGv16i8
10989 2U, // SQNEGv1i16
10990 2U, // SQNEGv1i32
10991 2U, // SQNEGv1i64
10992 2U, // SQNEGv1i8
10993 2U, // SQNEGv2i32
10994 3U, // SQNEGv2i64
10995 3U, // SQNEGv4i16
10996 4U, // SQNEGv4i32
10997 4U, // SQNEGv8i16
10998 5U, // SQNEGv8i8
10999 5777809U, // SQRDCMLAH_ZZZI_H
11000 72474757U, // SQRDCMLAH_ZZZI_S
11001 156352U, // SQRDCMLAH_ZZZ_B
11002 6299717U, // SQRDCMLAH_ZZZ_D
11003 156369U, // SQRDCMLAH_ZZZ_H
11004 6299781U, // SQRDCMLAH_ZZZ_S
11005 1695813U, // SQRDMLAH_ZZZI_D
11006 2449U, // SQRDMLAH_ZZZI_H
11007 1695877U, // SQRDMLAH_ZZZI_S
11008 0U, // SQRDMLAH_ZZZ_B
11009 69U, // SQRDMLAH_ZZZ_D
11010 17U, // SQRDMLAH_ZZZ_H
11011 133U, // SQRDMLAH_ZZZ_S
11012 3277381U, // SQRDMLAHi16_indexed
11013 3392069U, // SQRDMLAHi32_indexed
11014 2373U, // SQRDMLAHv1i16
11015 2373U, // SQRDMLAHv1i32
11016 57929U, // SQRDMLAHv2i32
11017 3392073U, // SQRDMLAHv2i32_indexed
11018 66122U, // SQRDMLAHv4i16
11019 3277386U, // SQRDMLAHv4i16_indexed
11020 25159U, // SQRDMLAHv4i32
11021 3392071U, // SQRDMLAHv4i32_indexed
11022 33351U, // SQRDMLAHv8i16
11023 3277383U, // SQRDMLAHv8i16_indexed
11024 1695813U, // SQRDMLSH_ZZZI_D
11025 2449U, // SQRDMLSH_ZZZI_H
11026 1695877U, // SQRDMLSH_ZZZI_S
11027 0U, // SQRDMLSH_ZZZ_B
11028 69U, // SQRDMLSH_ZZZ_D
11029 17U, // SQRDMLSH_ZZZ_H
11030 133U, // SQRDMLSH_ZZZ_S
11031 3277381U, // SQRDMLSHi16_indexed
11032 3392069U, // SQRDMLSHi32_indexed
11033 2373U, // SQRDMLSHv1i16
11034 2373U, // SQRDMLSHv1i32
11035 57929U, // SQRDMLSHv2i32
11036 3392073U, // SQRDMLSHv2i32_indexed
11037 66122U, // SQRDMLSHv4i16
11038 3277386U, // SQRDMLSHv4i16_indexed
11039 25159U, // SQRDMLSHv4i32
11040 3392071U, // SQRDMLSHv4i32_indexed
11041 33351U, // SQRDMLSHv8i16
11042 3277383U, // SQRDMLSHv8i16_indexed
11043 278917U, // SQRDMULH_ZZZI_D
11044 2952U, // SQRDMULH_ZZZI_H
11045 279301U, // SQRDMULH_ZZZI_S
11046 645U, // SQRDMULH_ZZZ_B
11047 389U, // SQRDMULH_ZZZ_D
11048 8U, // SQRDMULH_ZZZ_H
11049 773U, // SQRDMULH_ZZZ_S
11050 197U, // SQRDMULHv1i16
11051 10093061U, // SQRDMULHv1i16_indexed
11052 197U, // SQRDMULHv1i32
11053 10207749U, // SQRDMULHv1i32_indexed
11054 57865U, // SQRDMULHv2i32
11055 10207753U, // SQRDMULHv2i32_indexed
11056 66058U, // SQRDMULHv4i16
11057 10093066U, // SQRDMULHv4i16_indexed
11058 25095U, // SQRDMULHv4i32
11059 10207751U, // SQRDMULHv4i32_indexed
11060 33287U, // SQRDMULHv8i16
11061 10093063U, // SQRDMULHv8i16_indexed
11062 533128U, // SQRSHLR_ZPmZ_B
11063 1057160U, // SQRSHLR_ZPmZ_D
11064 1614536U, // SQRSHLR_ZPmZ_H
11065 2106120U, // SQRSHLR_ZPmZ_S
11066 533128U, // SQRSHL_ZPmZ_B
11067 1057160U, // SQRSHL_ZPmZ_D
11068 1614536U, // SQRSHL_ZPmZ_H
11069 2106120U, // SQRSHL_ZPmZ_S
11070 49673U, // SQRSHLv16i8
11071 197U, // SQRSHLv1i16
11072 197U, // SQRSHLv1i32
11073 197U, // SQRSHLv1i64
11074 197U, // SQRSHLv1i8
11075 57865U, // SQRSHLv2i32
11076 16902U, // SQRSHLv2i64
11077 66058U, // SQRSHLv4i16
11078 25095U, // SQRSHLv4i32
11079 33287U, // SQRSHLv8i16
11080 74250U, // SQRSHLv8i8
11081 197U, // SQRSHRNB_ZZI_B
11082 12U, // SQRSHRNB_ZZI_H
11083 197U, // SQRSHRNB_ZZI_S
11084 2373U, // SQRSHRNT_ZZI_B
11085 20U, // SQRSHRNT_ZZI_H
11086 2373U, // SQRSHRNT_ZZI_S
11087 197U, // SQRSHRNb
11088 197U, // SQRSHRNh
11089 197U, // SQRSHRNs
11090 2375U, // SQRSHRNv16i8_shift
11091 198U, // SQRSHRNv2i32_shift
11092 199U, // SQRSHRNv4i16_shift
11093 2374U, // SQRSHRNv4i32_shift
11094 2375U, // SQRSHRNv8i16_shift
11095 199U, // SQRSHRNv8i8_shift
11096 197U, // SQRSHRUNB_ZZI_B
11097 12U, // SQRSHRUNB_ZZI_H
11098 197U, // SQRSHRUNB_ZZI_S
11099 2373U, // SQRSHRUNT_ZZI_B
11100 20U, // SQRSHRUNT_ZZI_H
11101 2373U, // SQRSHRUNT_ZZI_S
11102 197U, // SQRSHRUNb
11103 197U, // SQRSHRUNh
11104 197U, // SQRSHRUNs
11105 2375U, // SQRSHRUNv16i8_shift
11106 198U, // SQRSHRUNv2i32_shift
11107 199U, // SQRSHRUNv4i16_shift
11108 2374U, // SQRSHRUNv4i32_shift
11109 2375U, // SQRSHRUNv8i16_shift
11110 199U, // SQRSHRUNv8i8_shift
11111 533128U, // SQSHLR_ZPmZ_B
11112 1057160U, // SQSHLR_ZPmZ_D
11113 1614536U, // SQSHLR_ZPmZ_H
11114 2106120U, // SQSHLR_ZPmZ_S
11115 8840U, // SQSHLU_ZPmI_B
11116 8584U, // SQSHLU_ZPmI_D
11117 90824U, // SQSHLU_ZPmI_H
11118 8968U, // SQSHLU_ZPmI_S
11119 197U, // SQSHLUb
11120 197U, // SQSHLUd
11121 197U, // SQSHLUh
11122 197U, // SQSHLUs
11123 201U, // SQSHLUv16i8_shift
11124 201U, // SQSHLUv2i32_shift
11125 198U, // SQSHLUv2i64_shift
11126 202U, // SQSHLUv4i16_shift
11127 199U, // SQSHLUv4i32_shift
11128 199U, // SQSHLUv8i16_shift
11129 202U, // SQSHLUv8i8_shift
11130 8840U, // SQSHL_ZPmI_B
11131 8584U, // SQSHL_ZPmI_D
11132 90824U, // SQSHL_ZPmI_H
11133 8968U, // SQSHL_ZPmI_S
11134 533128U, // SQSHL_ZPmZ_B
11135 1057160U, // SQSHL_ZPmZ_D
11136 1614536U, // SQSHL_ZPmZ_H
11137 2106120U, // SQSHL_ZPmZ_S
11138 197U, // SQSHLb
11139 197U, // SQSHLd
11140 197U, // SQSHLh
11141 197U, // SQSHLs
11142 49673U, // SQSHLv16i8
11143 201U, // SQSHLv16i8_shift
11144 197U, // SQSHLv1i16
11145 197U, // SQSHLv1i32
11146 197U, // SQSHLv1i64
11147 197U, // SQSHLv1i8
11148 57865U, // SQSHLv2i32
11149 201U, // SQSHLv2i32_shift
11150 16902U, // SQSHLv2i64
11151 198U, // SQSHLv2i64_shift
11152 66058U, // SQSHLv4i16
11153 202U, // SQSHLv4i16_shift
11154 25095U, // SQSHLv4i32
11155 199U, // SQSHLv4i32_shift
11156 33287U, // SQSHLv8i16
11157 199U, // SQSHLv8i16_shift
11158 74250U, // SQSHLv8i8
11159 202U, // SQSHLv8i8_shift
11160 197U, // SQSHRNB_ZZI_B
11161 12U, // SQSHRNB_ZZI_H
11162 197U, // SQSHRNB_ZZI_S
11163 2373U, // SQSHRNT_ZZI_B
11164 20U, // SQSHRNT_ZZI_H
11165 2373U, // SQSHRNT_ZZI_S
11166 197U, // SQSHRNb
11167 197U, // SQSHRNh
11168 197U, // SQSHRNs
11169 2375U, // SQSHRNv16i8_shift
11170 198U, // SQSHRNv2i32_shift
11171 199U, // SQSHRNv4i16_shift
11172 2374U, // SQSHRNv4i32_shift
11173 2375U, // SQSHRNv8i16_shift
11174 199U, // SQSHRNv8i8_shift
11175 197U, // SQSHRUNB_ZZI_B
11176 12U, // SQSHRUNB_ZZI_H
11177 197U, // SQSHRUNB_ZZI_S
11178 2373U, // SQSHRUNT_ZZI_B
11179 20U, // SQSHRUNT_ZZI_H
11180 2373U, // SQSHRUNT_ZZI_S
11181 197U, // SQSHRUNb
11182 197U, // SQSHRUNh
11183 197U, // SQSHRUNs
11184 2375U, // SQSHRUNv16i8_shift
11185 198U, // SQSHRUNv2i32_shift
11186 199U, // SQSHRUNv4i16_shift
11187 2374U, // SQSHRUNv4i32_shift
11188 2375U, // SQSHRUNv8i16_shift
11189 199U, // SQSHRUNv8i8_shift
11190 533128U, // SQSUBR_ZPmZ_B
11191 1057160U, // SQSUBR_ZPmZ_D
11192 1614536U, // SQSUBR_ZPmZ_H
11193 2106120U, // SQSUBR_ZPmZ_S
11194 1029U, // SQSUB_ZI_B
11195 1093U, // SQSUB_ZI_D
11196 11U, // SQSUB_ZI_H
11197 1157U, // SQSUB_ZI_S
11198 533128U, // SQSUB_ZPmZ_B
11199 1057160U, // SQSUB_ZPmZ_D
11200 1614536U, // SQSUB_ZPmZ_H
11201 2106120U, // SQSUB_ZPmZ_S
11202 645U, // SQSUB_ZZZ_B
11203 389U, // SQSUB_ZZZ_D
11204 8U, // SQSUB_ZZZ_H
11205 773U, // SQSUB_ZZZ_S
11206 49673U, // SQSUBv16i8
11207 197U, // SQSUBv1i16
11208 197U, // SQSUBv1i32
11209 197U, // SQSUBv1i64
11210 197U, // SQSUBv1i8
11211 57865U, // SQSUBv2i32
11212 16902U, // SQSUBv2i64
11213 66058U, // SQSUBv4i16
11214 25095U, // SQSUBv4i32
11215 33287U, // SQSUBv8i16
11216 74250U, // SQSUBv8i8
11217 2U, // SQXTNB_ZZ_B
11218 0U, // SQXTNB_ZZ_H
11219 2U, // SQXTNB_ZZ_S
11220 2U, // SQXTNT_ZZ_B
11221 0U, // SQXTNT_ZZ_H
11222 2U, // SQXTNT_ZZ_S
11223 4U, // SQXTNv16i8
11224 2U, // SQXTNv1i16
11225 2U, // SQXTNv1i32
11226 2U, // SQXTNv1i8
11227 3U, // SQXTNv2i32
11228 4U, // SQXTNv4i16
11229 3U, // SQXTNv4i32
11230 4U, // SQXTNv8i16
11231 4U, // SQXTNv8i8
11232 2U, // SQXTUNB_ZZ_B
11233 0U, // SQXTUNB_ZZ_H
11234 2U, // SQXTUNB_ZZ_S
11235 2U, // SQXTUNT_ZZ_B
11236 0U, // SQXTUNT_ZZ_H
11237 2U, // SQXTUNT_ZZ_S
11238 4U, // SQXTUNv16i8
11239 2U, // SQXTUNv1i16
11240 2U, // SQXTUNv1i32
11241 2U, // SQXTUNv1i8
11242 3U, // SQXTUNv2i32
11243 4U, // SQXTUNv4i16
11244 3U, // SQXTUNv4i32
11245 4U, // SQXTUNv8i16
11246 4U, // SQXTUNv8i8
11247 533128U, // SRHADD_ZPmZ_B
11248 1057160U, // SRHADD_ZPmZ_D
11249 1614536U, // SRHADD_ZPmZ_H
11250 2106120U, // SRHADD_ZPmZ_S
11251 49673U, // SRHADDv16i8
11252 57865U, // SRHADDv2i32
11253 66058U, // SRHADDv4i16
11254 25095U, // SRHADDv4i32
11255 33287U, // SRHADDv8i16
11256 74250U, // SRHADDv8i8
11257 20U, // SRI_ZZI_B
11258 2373U, // SRI_ZZI_D
11259 20U, // SRI_ZZI_H
11260 2373U, // SRI_ZZI_S
11261 2373U, // SRId
11262 2377U, // SRIv16i8_shift
11263 2377U, // SRIv2i32_shift
11264 2374U, // SRIv2i64_shift
11265 2378U, // SRIv4i16_shift
11266 2375U, // SRIv4i32_shift
11267 2375U, // SRIv8i16_shift
11268 2378U, // SRIv8i8_shift
11269 533128U, // SRSHLR_ZPmZ_B
11270 1057160U, // SRSHLR_ZPmZ_D
11271 1614536U, // SRSHLR_ZPmZ_H
11272 2106120U, // SRSHLR_ZPmZ_S
11273 533128U, // SRSHL_ZPmZ_B
11274 1057160U, // SRSHL_ZPmZ_D
11275 1614536U, // SRSHL_ZPmZ_H
11276 2106120U, // SRSHL_ZPmZ_S
11277 49673U, // SRSHLv16i8
11278 197U, // SRSHLv1i64
11279 57865U, // SRSHLv2i32
11280 16902U, // SRSHLv2i64
11281 66058U, // SRSHLv4i16
11282 25095U, // SRSHLv4i32
11283 33287U, // SRSHLv8i16
11284 74250U, // SRSHLv8i8
11285 8840U, // SRSHR_ZPmI_B
11286 8584U, // SRSHR_ZPmI_D
11287 90824U, // SRSHR_ZPmI_H
11288 8968U, // SRSHR_ZPmI_S
11289 197U, // SRSHRd
11290 201U, // SRSHRv16i8_shift
11291 201U, // SRSHRv2i32_shift
11292 198U, // SRSHRv2i64_shift
11293 202U, // SRSHRv4i16_shift
11294 199U, // SRSHRv4i32_shift
11295 199U, // SRSHRv8i16_shift
11296 202U, // SRSHRv8i8_shift
11297 20U, // SRSRA_ZZI_B
11298 2373U, // SRSRA_ZZI_D
11299 20U, // SRSRA_ZZI_H
11300 2373U, // SRSRA_ZZI_S
11301 2373U, // SRSRAd
11302 2377U, // SRSRAv16i8_shift
11303 2377U, // SRSRAv2i32_shift
11304 2374U, // SRSRAv2i64_shift
11305 2378U, // SRSRAv4i16_shift
11306 2375U, // SRSRAv4i32_shift
11307 2375U, // SRSRAv8i16_shift
11308 2378U, // SRSRAv8i8_shift
11309 197U, // SSHLLB_ZZI_D
11310 12U, // SSHLLB_ZZI_H
11311 197U, // SSHLLB_ZZI_S
11312 197U, // SSHLLT_ZZI_D
11313 12U, // SSHLLT_ZZI_H
11314 197U, // SSHLLT_ZZI_S
11315 201U, // SSHLLv16i8_shift
11316 201U, // SSHLLv2i32_shift
11317 202U, // SSHLLv4i16_shift
11318 199U, // SSHLLv4i32_shift
11319 199U, // SSHLLv8i16_shift
11320 202U, // SSHLLv8i8_shift
11321 49673U, // SSHLv16i8
11322 197U, // SSHLv1i64
11323 57865U, // SSHLv2i32
11324 16902U, // SSHLv2i64
11325 66058U, // SSHLv4i16
11326 25095U, // SSHLv4i32
11327 33287U, // SSHLv8i16
11328 74250U, // SSHLv8i8
11329 197U, // SSHRd
11330 201U, // SSHRv16i8_shift
11331 201U, // SSHRv2i32_shift
11332 198U, // SSHRv2i64_shift
11333 202U, // SSHRv4i16_shift
11334 199U, // SSHRv4i32_shift
11335 199U, // SSHRv8i16_shift
11336 202U, // SSHRv8i8_shift
11337 20U, // SSRA_ZZI_B
11338 2373U, // SSRA_ZZI_D
11339 20U, // SSRA_ZZI_H
11340 2373U, // SSRA_ZZI_S
11341 2373U, // SSRAd
11342 2377U, // SSRAv16i8_shift
11343 2377U, // SSRAv2i32_shift
11344 2374U, // SSRAv2i64_shift
11345 2378U, // SSRAv4i16_shift
11346 2375U, // SSRAv4i32_shift
11347 2375U, // SSRAv8i16_shift
11348 2378U, // SSRAv8i8_shift
11349 149829U, // SST1B_D_IMM
11350 3013U, // SST1B_D_REAL
11351 3077U, // SST1B_D_SXTW
11352 3141U, // SST1B_D_UXTW
11353 149829U, // SST1B_S_IMM
11354 3205U, // SST1B_S_SXTW
11355 3269U, // SST1B_S_UXTW
11356 150789U, // SST1D_IMM
11357 3013U, // SST1D_REAL
11358 3397U, // SST1D_SCALED_SCALED_REAL
11359 3077U, // SST1D_SXTW
11360 3461U, // SST1D_SXTW_SCALED
11361 3141U, // SST1D_UXTW
11362 3525U, // SST1D_UXTW_SCALED
11363 151045U, // SST1H_D_IMM
11364 3013U, // SST1H_D_REAL
11365 3653U, // SST1H_D_SCALED_SCALED_REAL
11366 3077U, // SST1H_D_SXTW
11367 3717U, // SST1H_D_SXTW_SCALED
11368 3141U, // SST1H_D_UXTW
11369 3781U, // SST1H_D_UXTW_SCALED
11370 151045U, // SST1H_S_IMM
11371 3205U, // SST1H_S_SXTW
11372 3845U, // SST1H_S_SXTW_SCALED
11373 3269U, // SST1H_S_UXTW
11374 3909U, // SST1H_S_UXTW_SCALED
11375 151429U, // SST1W_D_IMM
11376 3013U, // SST1W_D_REAL
11377 4037U, // SST1W_D_SCALED_SCALED_REAL
11378 3077U, // SST1W_D_SXTW
11379 4101U, // SST1W_D_SXTW_SCALED
11380 3141U, // SST1W_D_UXTW
11381 4165U, // SST1W_D_UXTW_SCALED
11382 151429U, // SST1W_IMM
11383 3205U, // SST1W_SXTW
11384 4229U, // SST1W_SXTW_SCALED
11385 3269U, // SST1W_UXTW
11386 4293U, // SST1W_UXTW_SCALED
11387 773U, // SSUBLBT_ZZZ_D
11388 31U, // SSUBLBT_ZZZ_H
11389 325U, // SSUBLBT_ZZZ_S
11390 773U, // SSUBLB_ZZZ_D
11391 31U, // SSUBLB_ZZZ_H
11392 325U, // SSUBLB_ZZZ_S
11393 773U, // SSUBLTB_ZZZ_D
11394 31U, // SSUBLTB_ZZZ_H
11395 325U, // SSUBLTB_ZZZ_S
11396 773U, // SSUBLT_ZZZ_D
11397 31U, // SSUBLT_ZZZ_H
11398 325U, // SSUBLT_ZZZ_S
11399 49673U, // SSUBLv16i8_v8i16
11400 57865U, // SSUBLv2i32_v2i64
11401 66058U, // SSUBLv4i16_v4i32
11402 25095U, // SSUBLv4i32_v2i64
11403 33287U, // SSUBLv8i16_v4i32
11404 74250U, // SSUBLv8i8_v8i16
11405 773U, // SSUBWB_ZZZ_D
11406 31U, // SSUBWB_ZZZ_H
11407 325U, // SSUBWB_ZZZ_S
11408 773U, // SSUBWT_ZZZ_D
11409 31U, // SSUBWT_ZZZ_H
11410 325U, // SSUBWT_ZZZ_S
11411 49671U, // SSUBWv16i8_v8i16
11412 57862U, // SSUBWv2i32_v2i64
11413 66055U, // SSUBWv4i16_v4i32
11414 25094U, // SSUBWv4i32_v2i64
11415 33287U, // SSUBWv8i16_v4i32
11416 74247U, // SSUBWv8i8_v8i16
11417 4421U, // ST1B
11418 4421U, // ST1B_D
11419 289093U, // ST1B_D_IMM
11420 4421U, // ST1B_H
11421 289093U, // ST1B_H_IMM
11422 289093U, // ST1B_IMM
11423 4421U, // ST1B_S
11424 289093U, // ST1B_S_IMM
11425 4485U, // ST1D
11426 289093U, // ST1D_IMM
11427 0U, // ST1Fourv16b
11428 0U, // ST1Fourv16b_POST
11429 0U, // ST1Fourv1d
11430 0U, // ST1Fourv1d_POST
11431 0U, // ST1Fourv2d
11432 0U, // ST1Fourv2d_POST
11433 0U, // ST1Fourv2s
11434 0U, // ST1Fourv2s_POST
11435 0U, // ST1Fourv4h
11436 0U, // ST1Fourv4h_POST
11437 0U, // ST1Fourv4s
11438 0U, // ST1Fourv4s_POST
11439 0U, // ST1Fourv8b
11440 0U, // ST1Fourv8b_POST
11441 0U, // ST1Fourv8h
11442 0U, // ST1Fourv8h_POST
11443 4549U, // ST1H
11444 4549U, // ST1H_D
11445 289093U, // ST1H_D_IMM
11446 289093U, // ST1H_IMM
11447 4549U, // ST1H_S
11448 289093U, // ST1H_S_IMM
11449 0U, // ST1Onev16b
11450 0U, // ST1Onev16b_POST
11451 0U, // ST1Onev1d
11452 0U, // ST1Onev1d_POST
11453 0U, // ST1Onev2d
11454 0U, // ST1Onev2d_POST
11455 0U, // ST1Onev2s
11456 0U, // ST1Onev2s_POST
11457 0U, // ST1Onev4h
11458 0U, // ST1Onev4h_POST
11459 0U, // ST1Onev4s
11460 0U, // ST1Onev4s_POST
11461 0U, // ST1Onev8b
11462 0U, // ST1Onev8b_POST
11463 0U, // ST1Onev8h
11464 0U, // ST1Onev8h_POST
11465 0U, // ST1Threev16b
11466 0U, // ST1Threev16b_POST
11467 0U, // ST1Threev1d
11468 0U, // ST1Threev1d_POST
11469 0U, // ST1Threev2d
11470 0U, // ST1Threev2d_POST
11471 0U, // ST1Threev2s
11472 0U, // ST1Threev2s_POST
11473 0U, // ST1Threev4h
11474 0U, // ST1Threev4h_POST
11475 0U, // ST1Threev4s
11476 0U, // ST1Threev4s_POST
11477 0U, // ST1Threev8b
11478 0U, // ST1Threev8b_POST
11479 0U, // ST1Threev8h
11480 0U, // ST1Threev8h_POST
11481 0U, // ST1Twov16b
11482 0U, // ST1Twov16b_POST
11483 0U, // ST1Twov1d
11484 0U, // ST1Twov1d_POST
11485 0U, // ST1Twov2d
11486 0U, // ST1Twov2d_POST
11487 0U, // ST1Twov2s
11488 0U, // ST1Twov2s_POST
11489 0U, // ST1Twov4h
11490 0U, // ST1Twov4h_POST
11491 0U, // ST1Twov4s
11492 0U, // ST1Twov4s_POST
11493 0U, // ST1Twov8b
11494 0U, // ST1Twov8b_POST
11495 0U, // ST1Twov8h
11496 0U, // ST1Twov8h_POST
11497 4677U, // ST1W
11498 4677U, // ST1W_D
11499 289093U, // ST1W_D_IMM
11500 289093U, // ST1W_IMM
11501 0U, // ST1i16
11502 0U, // ST1i16_POST
11503 0U, // ST1i32
11504 0U, // ST1i32_POST
11505 0U, // ST1i64
11506 0U, // ST1i64_POST
11507 0U, // ST1i8
11508 0U, // ST1i8_POST
11509 4421U, // ST2B
11510 290309U, // ST2B_IMM
11511 4485U, // ST2D
11512 290309U, // ST2D_IMM
11513 147717U, // ST2GOffset
11514 4766U, // ST2GPostIndex
11515 307845U, // ST2GPreIndex
11516 4549U, // ST2H
11517 290309U, // ST2H_IMM
11518 0U, // ST2Twov16b
11519 0U, // ST2Twov16b_POST
11520 0U, // ST2Twov2d
11521 0U, // ST2Twov2d_POST
11522 0U, // ST2Twov2s
11523 0U, // ST2Twov2s_POST
11524 0U, // ST2Twov4h
11525 0U, // ST2Twov4h_POST
11526 0U, // ST2Twov4s
11527 0U, // ST2Twov4s_POST
11528 0U, // ST2Twov8b
11529 0U, // ST2Twov8b_POST
11530 0U, // ST2Twov8h
11531 0U, // ST2Twov8h_POST
11532 4677U, // ST2W
11533 290309U, // ST2W_IMM
11534 0U, // ST2i16
11535 0U, // ST2i16_POST
11536 0U, // ST2i32
11537 0U, // ST2i32_POST
11538 0U, // ST2i64
11539 0U, // ST2i64_POST
11540 0U, // ST2i8
11541 0U, // ST2i8_POST
11542 4421U, // ST3B
11543 4805U, // ST3B_IMM
11544 4485U, // ST3D
11545 4805U, // ST3D_IMM
11546 4549U, // ST3H
11547 4805U, // ST3H_IMM
11548 0U, // ST3Threev16b
11549 0U, // ST3Threev16b_POST
11550 0U, // ST3Threev2d
11551 0U, // ST3Threev2d_POST
11552 0U, // ST3Threev2s
11553 0U, // ST3Threev2s_POST
11554 0U, // ST3Threev4h
11555 0U, // ST3Threev4h_POST
11556 0U, // ST3Threev4s
11557 0U, // ST3Threev4s_POST
11558 0U, // ST3Threev8b
11559 0U, // ST3Threev8b_POST
11560 0U, // ST3Threev8h
11561 0U, // ST3Threev8h_POST
11562 4677U, // ST3W
11563 4805U, // ST3W_IMM
11564 0U, // ST3i16
11565 0U, // ST3i16_POST
11566 0U, // ST3i32
11567 0U, // ST3i32_POST
11568 0U, // ST3i64
11569 0U, // ST3i64_POST
11570 0U, // ST3i8
11571 0U, // ST3i8_POST
11572 4421U, // ST4B
11573 290693U, // ST4B_IMM
11574 4485U, // ST4D
11575 290693U, // ST4D_IMM
11576 0U, // ST4Fourv16b
11577 0U, // ST4Fourv16b_POST
11578 0U, // ST4Fourv2d
11579 0U, // ST4Fourv2d_POST
11580 0U, // ST4Fourv2s
11581 0U, // ST4Fourv2s_POST
11582 0U, // ST4Fourv4h
11583 0U, // ST4Fourv4h_POST
11584 0U, // ST4Fourv4s
11585 0U, // ST4Fourv4s_POST
11586 0U, // ST4Fourv8b
11587 0U, // ST4Fourv8b_POST
11588 0U, // ST4Fourv8h
11589 0U, // ST4Fourv8h_POST
11590 4549U, // ST4H
11591 290693U, // ST4H_IMM
11592 4677U, // ST4W
11593 290693U, // ST4W_IMM
11594 0U, // ST4i16
11595 0U, // ST4i16_POST
11596 0U, // ST4i32
11597 0U, // ST4i32_POST
11598 0U, // ST4i64
11599 0U, // ST4i64_POST
11600 0U, // ST4i8
11601 0U, // ST4i8_POST
11602 0U, // ST64B
11603 0U, // ST64BV
11604 0U, // ST64BV0
11605 29U, // STGM
11606 147717U, // STGOffset
11607 11542733U, // STGPi
11608 4766U, // STGPostIndex
11609 13404493U, // STGPpost
11610 180889933U, // STGPpre
11611 307845U, // STGPreIndex
11612 29U, // STLLRB
11613 29U, // STLLRH
11614 29U, // STLLRW
11615 29U, // STLLRX
11616 29U, // STLRB
11617 29U, // STLRH
11618 29U, // STLRW
11619 29U, // STLRX
11620 147653U, // STLURBi
11621 147653U, // STLURHi
11622 147653U, // STLURWi
11623 147653U, // STLURXi
11624 319685U, // STLXPW
11625 319685U, // STLXPX
11626 147661U, // STLXRB
11627 147661U, // STLXRH
11628 147661U, // STLXRW
11629 147661U, // STLXRX
11630 11018445U, // STNPDi
11631 11542733U, // STNPQi
11632 12067021U, // STNPSi
11633 12067021U, // STNPWi
11634 11018445U, // STNPXi
11635 289093U, // STNT1B_ZRI
11636 4421U, // STNT1B_ZRR
11637 149829U, // STNT1B_ZZR_D_REAL
11638 149829U, // STNT1B_ZZR_S_REAL
11639 289093U, // STNT1D_ZRI
11640 4485U, // STNT1D_ZRR
11641 149829U, // STNT1D_ZZR_D_REAL
11642 289093U, // STNT1H_ZRI
11643 4549U, // STNT1H_ZRR
11644 149829U, // STNT1H_ZZR_D_REAL
11645 149829U, // STNT1H_ZZR_S_REAL
11646 289093U, // STNT1W_ZRI
11647 4677U, // STNT1W_ZRR
11648 149829U, // STNT1W_ZZR_D_REAL
11649 149829U, // STNT1W_ZZR_S_REAL
11650 11018445U, // STPDi
11651 12880205U, // STPDpost
11652 180365645U, // STPDpre
11653 11542733U, // STPQi
11654 13404493U, // STPQpost
11655 180889933U, // STPQpre
11656 12067021U, // STPSi
11657 13928781U, // STPSpost
11658 181414221U, // STPSpre
11659 12067021U, // STPWi
11660 13928781U, // STPWpost
11661 181414221U, // STPWpre
11662 11018445U, // STPXi
11663 12880205U, // STPXpost
11664 180365645U, // STPXpre
11665 2398U, // STRBBpost
11666 305477U, // STRBBpre
11667 14164165U, // STRBBroW
11668 14688453U, // STRBBroX
11669 4933U, // STRBBui
11670 2398U, // STRBpost
11671 305477U, // STRBpre
11672 14164165U, // STRBroW
11673 14688453U, // STRBroX
11674 4933U, // STRBui
11675 2398U, // STRDpost
11676 305477U, // STRDpre
11677 15212741U, // STRDroW
11678 15737029U, // STRDroX
11679 4997U, // STRDui
11680 2398U, // STRHHpost
11681 305477U, // STRHHpre
11682 16261317U, // STRHHroW
11683 16785605U, // STRHHroX
11684 5061U, // STRHHui
11685 2398U, // STRHpost
11686 305477U, // STRHpre
11687 16261317U, // STRHroW
11688 16785605U, // STRHroX
11689 5061U, // STRHui
11690 2398U, // STRQpost
11691 305477U, // STRQpre
11692 17309893U, // STRQroW
11693 17834181U, // STRQroX
11694 5125U, // STRQui
11695 2398U, // STRSpost
11696 305477U, // STRSpre
11697 18358469U, // STRSroW
11698 18882757U, // STRSroX
11699 5189U, // STRSui
11700 2398U, // STRWpost
11701 305477U, // STRWpre
11702 18358469U, // STRWroW
11703 18882757U, // STRWroX
11704 5189U, // STRWui
11705 2398U, // STRXpost
11706 305477U, // STRXpre
11707 15212741U, // STRXroW
11708 15737029U, // STRXroX
11709 4997U, // STRXui
11710 286917U, // STR_PXI
11711 286917U, // STR_ZXI
11712 147653U, // STTRBi
11713 147653U, // STTRHi
11714 147653U, // STTRWi
11715 147653U, // STTRXi
11716 147653U, // STURBBi
11717 147653U, // STURBi
11718 147653U, // STURDi
11719 147653U, // STURHHi
11720 147653U, // STURHi
11721 147653U, // STURQi
11722 147653U, // STURSi
11723 147653U, // STURWi
11724 147653U, // STURXi
11725 319685U, // STXPW
11726 319685U, // STXPX
11727 147661U, // STXRB
11728 147661U, // STXRH
11729 147661U, // STXRW
11730 147661U, // STXRX
11731 147717U, // STZ2GOffset
11732 4766U, // STZ2GPostIndex
11733 307845U, // STZ2GPreIndex
11734 29U, // STZGM
11735 147717U, // STZGOffset
11736 4766U, // STZGPostIndex
11737 307845U, // STZGPreIndex
11738 8453U, // SUBG
11739 325U, // SUBHNB_ZZZ_B
11740 6U, // SUBHNB_ZZZ_H
11741 389U, // SUBHNB_ZZZ_S
11742 453U, // SUBHNT_ZZZ_B
11743 1U, // SUBHNT_ZZZ_H
11744 69U, // SUBHNT_ZZZ_S
11745 16902U, // SUBHNv2i64_v2i32
11746 16966U, // SUBHNv2i64_v4i32
11747 25095U, // SUBHNv4i32_v4i16
11748 25159U, // SUBHNv4i32_v8i16
11749 33351U, // SUBHNv8i16_v16i8
11750 33287U, // SUBHNv8i16_v8i8
11751 197U, // SUBP
11752 197U, // SUBPS
11753 1029U, // SUBR_ZI_B
11754 1093U, // SUBR_ZI_D
11755 11U, // SUBR_ZI_H
11756 1157U, // SUBR_ZI_S
11757 533128U, // SUBR_ZPmZ_B
11758 1057160U, // SUBR_ZPmZ_D
11759 1614536U, // SUBR_ZPmZ_H
11760 2106120U, // SUBR_ZPmZ_S
11761 837U, // SUBSWri
11762 901U, // SUBSWrs
11763 965U, // SUBSWrx
11764 837U, // SUBSXri
11765 901U, // SUBSXrs
11766 965U, // SUBSXrx
11767 82117U, // SUBSXrx64
11768 837U, // SUBWri
11769 901U, // SUBWrs
11770 965U, // SUBWrx
11771 837U, // SUBXri
11772 901U, // SUBXrs
11773 965U, // SUBXrx
11774 82117U, // SUBXrx64
11775 1029U, // SUB_ZI_B
11776 1093U, // SUB_ZI_D
11777 11U, // SUB_ZI_H
11778 1157U, // SUB_ZI_S
11779 533128U, // SUB_ZPmZ_B
11780 1057160U, // SUB_ZPmZ_D
11781 1614536U, // SUB_ZPmZ_H
11782 2106120U, // SUB_ZPmZ_S
11783 645U, // SUB_ZZZ_B
11784 389U, // SUB_ZZZ_D
11785 8U, // SUB_ZZZ_H
11786 773U, // SUB_ZZZ_S
11787 49673U, // SUBv16i8
11788 197U, // SUBv1i64
11789 57865U, // SUBv2i32
11790 16902U, // SUBv2i64
11791 66058U, // SUBv4i16
11792 25095U, // SUBv4i32
11793 33287U, // SUBv8i16
11794 74250U, // SUBv8i8
11795 2432U, // SUDOT_ZZZI
11796 311881U, // SUDOTlanev16i8
11797 311882U, // SUDOTlanev8i8
11798 2U, // SUNPKHI_ZZ_D
11799 0U, // SUNPKHI_ZZ_H
11800 2U, // SUNPKHI_ZZ_S
11801 2U, // SUNPKLO_ZZ_D
11802 0U, // SUNPKLO_ZZ_H
11803 2U, // SUNPKLO_ZZ_S
11804 533128U, // SUQADD_ZPmZ_B
11805 1057160U, // SUQADD_ZPmZ_D
11806 1614536U, // SUQADD_ZPmZ_H
11807 2106120U, // SUQADD_ZPmZ_S
11808 1U, // SUQADDv16i8
11809 2U, // SUQADDv1i16
11810 2U, // SUQADDv1i32
11811 2U, // SUQADDv1i64
11812 2U, // SUQADDv1i8
11813 2U, // SUQADDv2i32
11814 3U, // SUQADDv2i64
11815 3U, // SUQADDv4i16
11816 4U, // SUQADDv4i32
11817 4U, // SUQADDv8i16
11818 5U, // SUQADDv8i8
11819 0U, // SVC
11820 0U, // SWPAB
11821 0U, // SWPAH
11822 0U, // SWPALB
11823 0U, // SWPALH
11824 0U, // SWPALW
11825 0U, // SWPALX
11826 0U, // SWPAW
11827 0U, // SWPAX
11828 0U, // SWPB
11829 0U, // SWPH
11830 0U, // SWPLB
11831 0U, // SWPLH
11832 0U, // SWPLW
11833 0U, // SWPLX
11834 0U, // SWPW
11835 0U, // SWPX
11836 0U, // SXTB_ZPmZ_D
11837 0U, // SXTB_ZPmZ_H
11838 1U, // SXTB_ZPmZ_S
11839 0U, // SXTH_ZPmZ_D
11840 1U, // SXTH_ZPmZ_S
11841 0U, // SXTW_ZPmZ_D
11842 5701U, // SYSLxt
11843 0U, // SYSxt
11844 31U, // TBL_ZZZZ_B
11845 0U, // TBL_ZZZZ_D
11846 0U, // TBL_ZZZZ_H
11847 0U, // TBL_ZZZZ_S
11848 31U, // TBL_ZZZ_B
11849 0U, // TBL_ZZZ_D
11850 0U, // TBL_ZZZ_H
11851 0U, // TBL_ZZZ_S
11852 1U, // TBLv16i8Four
11853 1U, // TBLv16i8One
11854 1U, // TBLv16i8Three
11855 1U, // TBLv16i8Two
11856 5U, // TBLv8i8Four
11857 5U, // TBLv8i8One
11858 5U, // TBLv8i8Three
11859 5U, // TBLv8i8Two
11860 5765U, // TBNZW
11861 5765U, // TBNZX
11862 0U, // TBX_ZZZ_B
11863 69U, // TBX_ZZZ_D
11864 17U, // TBX_ZZZ_H
11865 133U, // TBX_ZZZ_S
11866 1U, // TBXv16i8Four
11867 1U, // TBXv16i8One
11868 1U, // TBXv16i8Three
11869 1U, // TBXv16i8Two
11870 5U, // TBXv8i8Four
11871 5U, // TBXv8i8One
11872 5U, // TBXv8i8Three
11873 5U, // TBXv8i8Two
11874 5765U, // TBZW
11875 5765U, // TBZX
11876 0U, // TCANCEL
11877 0U, // TCOMMIT
11878 645U, // TRN1_PPP_B
11879 389U, // TRN1_PPP_D
11880 8U, // TRN1_PPP_H
11881 773U, // TRN1_PPP_S
11882 645U, // TRN1_ZZZ_B
11883 389U, // TRN1_ZZZ_D
11884 8U, // TRN1_ZZZ_H
11885 49U, // TRN1_ZZZ_Q
11886 773U, // TRN1_ZZZ_S
11887 49673U, // TRN1v16i8
11888 57865U, // TRN1v2i32
11889 16902U, // TRN1v2i64
11890 66058U, // TRN1v4i16
11891 25095U, // TRN1v4i32
11892 33287U, // TRN1v8i16
11893 74250U, // TRN1v8i8
11894 645U, // TRN2_PPP_B
11895 389U, // TRN2_PPP_D
11896 8U, // TRN2_PPP_H
11897 773U, // TRN2_PPP_S
11898 645U, // TRN2_ZZZ_B
11899 389U, // TRN2_ZZZ_D
11900 8U, // TRN2_ZZZ_H
11901 49U, // TRN2_ZZZ_Q
11902 773U, // TRN2_ZZZ_S
11903 49673U, // TRN2v16i8
11904 57865U, // TRN2v2i32
11905 16902U, // TRN2v2i64
11906 66058U, // TRN2v4i16
11907 25095U, // TRN2v4i32
11908 33287U, // TRN2v8i16
11909 74250U, // TRN2v8i8
11910 0U, // TSB
11911 0U, // TSTART
11912 0U, // TTEST
11913 133U, // UABALB_ZZZ_D
11914 0U, // UABALB_ZZZ_H
11915 453U, // UABALB_ZZZ_S
11916 133U, // UABALT_ZZZ_D
11917 0U, // UABALT_ZZZ_H
11918 453U, // UABALT_ZZZ_S
11919 49737U, // UABALv16i8_v8i16
11920 57929U, // UABALv2i32_v2i64
11921 66122U, // UABALv4i16_v4i32
11922 25159U, // UABALv4i32_v2i64
11923 33351U, // UABALv8i16_v4i32
11924 74314U, // UABALv8i8_v8i16
11925 0U, // UABA_ZZZ_B
11926 69U, // UABA_ZZZ_D
11927 17U, // UABA_ZZZ_H
11928 133U, // UABA_ZZZ_S
11929 49737U, // UABAv16i8
11930 57929U, // UABAv2i32
11931 66122U, // UABAv4i16
11932 25159U, // UABAv4i32
11933 33351U, // UABAv8i16
11934 74314U, // UABAv8i8
11935 773U, // UABDLB_ZZZ_D
11936 31U, // UABDLB_ZZZ_H
11937 325U, // UABDLB_ZZZ_S
11938 773U, // UABDLT_ZZZ_D
11939 31U, // UABDLT_ZZZ_H
11940 325U, // UABDLT_ZZZ_S
11941 49673U, // UABDLv16i8_v8i16
11942 57865U, // UABDLv2i32_v2i64
11943 66058U, // UABDLv4i16_v4i32
11944 25095U, // UABDLv4i32_v2i64
11945 33287U, // UABDLv8i16_v4i32
11946 74250U, // UABDLv8i8_v8i16
11947 533128U, // UABD_ZPmZ_B
11948 1057160U, // UABD_ZPmZ_D
11949 1614536U, // UABD_ZPmZ_H
11950 2106120U, // UABD_ZPmZ_S
11951 49673U, // UABDv16i8
11952 57865U, // UABDv2i32
11953 66058U, // UABDv4i16
11954 25095U, // UABDv4i32
11955 33287U, // UABDv8i16
11956 74250U, // UABDv8i8
11957 136U, // UADALP_ZPmZ_D
11958 0U, // UADALP_ZPmZ_H
11959 456U, // UADALP_ZPmZ_S
11960 1U, // UADALPv16i8_v8i16
11961 2U, // UADALPv2i32_v1i64
11962 3U, // UADALPv4i16_v2i32
11963 4U, // UADALPv4i32_v2i64
11964 4U, // UADALPv8i16_v4i32
11965 5U, // UADALPv8i8_v4i16
11966 773U, // UADDLB_ZZZ_D
11967 31U, // UADDLB_ZZZ_H
11968 325U, // UADDLB_ZZZ_S
11969 1U, // UADDLPv16i8_v8i16
11970 2U, // UADDLPv2i32_v1i64
11971 3U, // UADDLPv4i16_v2i32
11972 4U, // UADDLPv4i32_v2i64
11973 4U, // UADDLPv8i16_v4i32
11974 5U, // UADDLPv8i8_v4i16
11975 773U, // UADDLT_ZZZ_D
11976 31U, // UADDLT_ZZZ_H
11977 325U, // UADDLT_ZZZ_S
11978 1U, // UADDLVv16i8v
11979 3U, // UADDLVv4i16v
11980 4U, // UADDLVv4i32v
11981 4U, // UADDLVv8i16v
11982 5U, // UADDLVv8i8v
11983 49673U, // UADDLv16i8_v8i16
11984 57865U, // UADDLv2i32_v2i64
11985 66058U, // UADDLv4i16_v4i32
11986 25095U, // UADDLv4i32_v2i64
11987 33287U, // UADDLv8i16_v4i32
11988 74250U, // UADDLv8i8_v8i16
11989 0U, // UADDV_VPZ_B
11990 0U, // UADDV_VPZ_D
11991 0U, // UADDV_VPZ_H
11992 0U, // UADDV_VPZ_S
11993 773U, // UADDWB_ZZZ_D
11994 31U, // UADDWB_ZZZ_H
11995 325U, // UADDWB_ZZZ_S
11996 773U, // UADDWT_ZZZ_D
11997 31U, // UADDWT_ZZZ_H
11998 325U, // UADDWT_ZZZ_S
11999 49671U, // UADDWv16i8_v8i16
12000 57862U, // UADDWv2i32_v2i64
12001 66055U, // UADDWv4i16_v4i32
12002 25094U, // UADDWv4i32_v2i64
12003 33287U, // UADDWv8i16_v4i32
12004 74247U, // UADDWv8i8_v8i16
12005 8389U, // UBFMWri
12006 8389U, // UBFMXri
12007 197U, // UCVTFSWDri
12008 197U, // UCVTFSWHri
12009 197U, // UCVTFSWSri
12010 197U, // UCVTFSXDri
12011 197U, // UCVTFSXHri
12012 197U, // UCVTFSXSri
12013 2U, // UCVTFUWDri
12014 2U, // UCVTFUWHri
12015 2U, // UCVTFUWSri
12016 2U, // UCVTFUXDri
12017 2U, // UCVTFUXHri
12018 2U, // UCVTFUXSri
12019 0U, // UCVTF_ZPmZ_DtoD
12020 0U, // UCVTF_ZPmZ_DtoH
12021 0U, // UCVTF_ZPmZ_DtoS
12022 0U, // UCVTF_ZPmZ_HtoH
12023 1U, // UCVTF_ZPmZ_StoD
12024 0U, // UCVTF_ZPmZ_StoH
12025 1U, // UCVTF_ZPmZ_StoS
12026 197U, // UCVTFd
12027 197U, // UCVTFh
12028 197U, // UCVTFs
12029 2U, // UCVTFv1i16
12030 2U, // UCVTFv1i32
12031 2U, // UCVTFv1i64
12032 2U, // UCVTFv2f32
12033 3U, // UCVTFv2f64
12034 201U, // UCVTFv2i32_shift
12035 198U, // UCVTFv2i64_shift
12036 3U, // UCVTFv4f16
12037 4U, // UCVTFv4f32
12038 202U, // UCVTFv4i16_shift
12039 199U, // UCVTFv4i32_shift
12040 4U, // UCVTFv8f16
12041 199U, // UCVTFv8i16_shift
12042 0U, // UDF
12043 1057160U, // UDIVR_ZPmZ_D
12044 2106120U, // UDIVR_ZPmZ_S
12045 197U, // UDIVWr
12046 197U, // UDIVXr
12047 1057160U, // UDIV_ZPmZ_D
12048 2106120U, // UDIV_ZPmZ_S
12049 1696197U, // UDOT_ZZZI_D
12050 2432U, // UDOT_ZZZI_S
12051 453U, // UDOT_ZZZ_D
12052 0U, // UDOT_ZZZ_S
12053 311881U, // UDOTlanev16i8
12054 311882U, // UDOTlanev8i8
12055 49737U, // UDOTv16i8
12056 74314U, // UDOTv8i8
12057 533128U, // UHADD_ZPmZ_B
12058 1057160U, // UHADD_ZPmZ_D
12059 1614536U, // UHADD_ZPmZ_H
12060 2106120U, // UHADD_ZPmZ_S
12061 49673U, // UHADDv16i8
12062 57865U, // UHADDv2i32
12063 66058U, // UHADDv4i16
12064 25095U, // UHADDv4i32
12065 33287U, // UHADDv8i16
12066 74250U, // UHADDv8i8
12067 533128U, // UHSUBR_ZPmZ_B
12068 1057160U, // UHSUBR_ZPmZ_D
12069 1614536U, // UHSUBR_ZPmZ_H
12070 2106120U, // UHSUBR_ZPmZ_S
12071 533128U, // UHSUB_ZPmZ_B
12072 1057160U, // UHSUB_ZPmZ_D
12073 1614536U, // UHSUB_ZPmZ_H
12074 2106120U, // UHSUB_ZPmZ_S
12075 49673U, // UHSUBv16i8
12076 57865U, // UHSUBv2i32
12077 66058U, // UHSUBv4i16
12078 25095U, // UHSUBv4i32
12079 33287U, // UHSUBv8i16
12080 74250U, // UHSUBv8i8
12081 8389U, // UMADDLrrr
12082 533128U, // UMAXP_ZPmZ_B
12083 1057160U, // UMAXP_ZPmZ_D
12084 1614536U, // UMAXP_ZPmZ_H
12085 2106120U, // UMAXP_ZPmZ_S
12086 49673U, // UMAXPv16i8
12087 57865U, // UMAXPv2i32
12088 66058U, // UMAXPv4i16
12089 25095U, // UMAXPv4i32
12090 33287U, // UMAXPv8i16
12091 74250U, // UMAXPv8i8
12092 0U, // UMAXV_VPZ_B
12093 0U, // UMAXV_VPZ_D
12094 0U, // UMAXV_VPZ_H
12095 0U, // UMAXV_VPZ_S
12096 1U, // UMAXVv16i8v
12097 3U, // UMAXVv4i16v
12098 4U, // UMAXVv4i32v
12099 4U, // UMAXVv8i16v
12100 5U, // UMAXVv8i8v
12101 5829U, // UMAX_ZI_B
12102 5829U, // UMAX_ZI_D
12103 23U, // UMAX_ZI_H
12104 5829U, // UMAX_ZI_S
12105 533128U, // UMAX_ZPmZ_B
12106 1057160U, // UMAX_ZPmZ_D
12107 1614536U, // UMAX_ZPmZ_H
12108 2106120U, // UMAX_ZPmZ_S
12109 49673U, // UMAXv16i8
12110 57865U, // UMAXv2i32
12111 66058U, // UMAXv4i16
12112 25095U, // UMAXv4i32
12113 33287U, // UMAXv8i16
12114 74250U, // UMAXv8i8
12115 533128U, // UMINP_ZPmZ_B
12116 1057160U, // UMINP_ZPmZ_D
12117 1614536U, // UMINP_ZPmZ_H
12118 2106120U, // UMINP_ZPmZ_S
12119 49673U, // UMINPv16i8
12120 57865U, // UMINPv2i32
12121 66058U, // UMINPv4i16
12122 25095U, // UMINPv4i32
12123 33287U, // UMINPv8i16
12124 74250U, // UMINPv8i8
12125 0U, // UMINV_VPZ_B
12126 0U, // UMINV_VPZ_D
12127 0U, // UMINV_VPZ_H
12128 0U, // UMINV_VPZ_S
12129 1U, // UMINVv16i8v
12130 3U, // UMINVv4i16v
12131 4U, // UMINVv4i32v
12132 4U, // UMINVv8i16v
12133 5U, // UMINVv8i8v
12134 5829U, // UMIN_ZI_B
12135 5829U, // UMIN_ZI_D
12136 23U, // UMIN_ZI_H
12137 5829U, // UMIN_ZI_S
12138 533128U, // UMIN_ZPmZ_B
12139 1057160U, // UMIN_ZPmZ_D
12140 1614536U, // UMIN_ZPmZ_H
12141 2106120U, // UMIN_ZPmZ_S
12142 49673U, // UMINv16i8
12143 57865U, // UMINv2i32
12144 66058U, // UMINv4i16
12145 25095U, // UMINv4i32
12146 33287U, // UMINv8i16
12147 74250U, // UMINv8i8
12148 1695877U, // UMLALB_ZZZI_D
12149 1696197U, // UMLALB_ZZZI_S
12150 133U, // UMLALB_ZZZ_D
12151 0U, // UMLALB_ZZZ_H
12152 453U, // UMLALB_ZZZ_S
12153 1695877U, // UMLALT_ZZZI_D
12154 1696197U, // UMLALT_ZZZI_S
12155 133U, // UMLALT_ZZZ_D
12156 0U, // UMLALT_ZZZ_H
12157 453U, // UMLALT_ZZZ_S
12158 49737U, // UMLALv16i8_v8i16
12159 3392073U, // UMLALv2i32_indexed
12160 57929U, // UMLALv2i32_v2i64
12161 3277386U, // UMLALv4i16_indexed
12162 66122U, // UMLALv4i16_v4i32
12163 3392071U, // UMLALv4i32_indexed
12164 25159U, // UMLALv4i32_v2i64
12165 3277383U, // UMLALv8i16_indexed
12166 33351U, // UMLALv8i16_v4i32
12167 74314U, // UMLALv8i8_v8i16
12168 1695877U, // UMLSLB_ZZZI_D
12169 1696197U, // UMLSLB_ZZZI_S
12170 133U, // UMLSLB_ZZZ_D
12171 0U, // UMLSLB_ZZZ_H
12172 453U, // UMLSLB_ZZZ_S
12173 1695877U, // UMLSLT_ZZZI_D
12174 1696197U, // UMLSLT_ZZZI_S
12175 133U, // UMLSLT_ZZZ_D
12176 0U, // UMLSLT_ZZZ_H
12177 453U, // UMLSLT_ZZZ_S
12178 49737U, // UMLSLv16i8_v8i16
12179 3392073U, // UMLSLv2i32_indexed
12180 57929U, // UMLSLv2i32_v2i64
12181 3277386U, // UMLSLv4i16_indexed
12182 66122U, // UMLSLv4i16_v4i32
12183 3392071U, // UMLSLv4i32_indexed
12184 25159U, // UMLSLv4i32_v2i64
12185 3277383U, // UMLSLv8i16_indexed
12186 33351U, // UMLSLv8i16_v4i32
12187 74314U, // UMLSLv8i8_v8i16
12188 49737U, // UMMLA
12189 0U, // UMMLA_ZZZ
12190 2709U, // UMOVvi16
12191 2709U, // UMOVvi32
12192 2710U, // UMOVvi64
12193 2710U, // UMOVvi8
12194 8389U, // UMSUBLrrr
12195 533128U, // UMULH_ZPmZ_B
12196 1057160U, // UMULH_ZPmZ_D
12197 1614536U, // UMULH_ZPmZ_H
12198 2106120U, // UMULH_ZPmZ_S
12199 645U, // UMULH_ZZZ_B
12200 389U, // UMULH_ZZZ_D
12201 8U, // UMULH_ZZZ_H
12202 773U, // UMULH_ZZZ_S
12203 197U, // UMULHrr
12204 279301U, // UMULLB_ZZZI_D
12205 278853U, // UMULLB_ZZZI_S
12206 773U, // UMULLB_ZZZ_D
12207 31U, // UMULLB_ZZZ_H
12208 325U, // UMULLB_ZZZ_S
12209 279301U, // UMULLT_ZZZI_D
12210 278853U, // UMULLT_ZZZI_S
12211 773U, // UMULLT_ZZZ_D
12212 31U, // UMULLT_ZZZ_H
12213 325U, // UMULLT_ZZZ_S
12214 49673U, // UMULLv16i8_v8i16
12215 10207753U, // UMULLv2i32_indexed
12216 57865U, // UMULLv2i32_v2i64
12217 10093066U, // UMULLv4i16_indexed
12218 66058U, // UMULLv4i16_v4i32
12219 10207751U, // UMULLv4i32_indexed
12220 25095U, // UMULLv4i32_v2i64
12221 10093063U, // UMULLv8i16_indexed
12222 33287U, // UMULLv8i16_v4i32
12223 74250U, // UMULLv8i8_v8i16
12224 1029U, // UQADD_ZI_B
12225 1093U, // UQADD_ZI_D
12226 11U, // UQADD_ZI_H
12227 1157U, // UQADD_ZI_S
12228 533128U, // UQADD_ZPmZ_B
12229 1057160U, // UQADD_ZPmZ_D
12230 1614536U, // UQADD_ZPmZ_H
12231 2106120U, // UQADD_ZPmZ_S
12232 645U, // UQADD_ZZZ_B
12233 389U, // UQADD_ZZZ_D
12234 8U, // UQADD_ZZZ_H
12235 773U, // UQADD_ZZZ_S
12236 49673U, // UQADDv16i8
12237 197U, // UQADDv1i16
12238 197U, // UQADDv1i32
12239 197U, // UQADDv1i64
12240 197U, // UQADDv1i8
12241 57865U, // UQADDv2i32
12242 16902U, // UQADDv2i64
12243 66058U, // UQADDv4i16
12244 25095U, // UQADDv4i32
12245 33287U, // UQADDv8i16
12246 74250U, // UQADDv8i8
12247 0U, // UQDECB_WPiI
12248 0U, // UQDECB_XPiI
12249 0U, // UQDECD_WPiI
12250 0U, // UQDECD_XPiI
12251 0U, // UQDECD_ZPiI
12252 0U, // UQDECH_WPiI
12253 0U, // UQDECH_XPiI
12254 0U, // UQDECH_ZPiI
12255 2U, // UQDECP_WP_B
12256 2U, // UQDECP_WP_D
12257 2U, // UQDECP_WP_H
12258 2U, // UQDECP_WP_S
12259 2U, // UQDECP_XP_B
12260 2U, // UQDECP_XP_D
12261 2U, // UQDECP_XP_H
12262 2U, // UQDECP_XP_S
12263 2U, // UQDECP_ZP_D
12264 0U, // UQDECP_ZP_H
12265 2U, // UQDECP_ZP_S
12266 0U, // UQDECW_WPiI
12267 0U, // UQDECW_XPiI
12268 0U, // UQDECW_ZPiI
12269 0U, // UQINCB_WPiI
12270 0U, // UQINCB_XPiI
12271 0U, // UQINCD_WPiI
12272 0U, // UQINCD_XPiI
12273 0U, // UQINCD_ZPiI
12274 0U, // UQINCH_WPiI
12275 0U, // UQINCH_XPiI
12276 0U, // UQINCH_ZPiI
12277 2U, // UQINCP_WP_B
12278 2U, // UQINCP_WP_D
12279 2U, // UQINCP_WP_H
12280 2U, // UQINCP_WP_S
12281 2U, // UQINCP_XP_B
12282 2U, // UQINCP_XP_D
12283 2U, // UQINCP_XP_H
12284 2U, // UQINCP_XP_S
12285 2U, // UQINCP_ZP_D
12286 0U, // UQINCP_ZP_H
12287 2U, // UQINCP_ZP_S
12288 0U, // UQINCW_WPiI
12289 0U, // UQINCW_XPiI
12290 0U, // UQINCW_ZPiI
12291 533128U, // UQRSHLR_ZPmZ_B
12292 1057160U, // UQRSHLR_ZPmZ_D
12293 1614536U, // UQRSHLR_ZPmZ_H
12294 2106120U, // UQRSHLR_ZPmZ_S
12295 533128U, // UQRSHL_ZPmZ_B
12296 1057160U, // UQRSHL_ZPmZ_D
12297 1614536U, // UQRSHL_ZPmZ_H
12298 2106120U, // UQRSHL_ZPmZ_S
12299 49673U, // UQRSHLv16i8
12300 197U, // UQRSHLv1i16
12301 197U, // UQRSHLv1i32
12302 197U, // UQRSHLv1i64
12303 197U, // UQRSHLv1i8
12304 57865U, // UQRSHLv2i32
12305 16902U, // UQRSHLv2i64
12306 66058U, // UQRSHLv4i16
12307 25095U, // UQRSHLv4i32
12308 33287U, // UQRSHLv8i16
12309 74250U, // UQRSHLv8i8
12310 197U, // UQRSHRNB_ZZI_B
12311 12U, // UQRSHRNB_ZZI_H
12312 197U, // UQRSHRNB_ZZI_S
12313 2373U, // UQRSHRNT_ZZI_B
12314 20U, // UQRSHRNT_ZZI_H
12315 2373U, // UQRSHRNT_ZZI_S
12316 197U, // UQRSHRNb
12317 197U, // UQRSHRNh
12318 197U, // UQRSHRNs
12319 2375U, // UQRSHRNv16i8_shift
12320 198U, // UQRSHRNv2i32_shift
12321 199U, // UQRSHRNv4i16_shift
12322 2374U, // UQRSHRNv4i32_shift
12323 2375U, // UQRSHRNv8i16_shift
12324 199U, // UQRSHRNv8i8_shift
12325 533128U, // UQSHLR_ZPmZ_B
12326 1057160U, // UQSHLR_ZPmZ_D
12327 1614536U, // UQSHLR_ZPmZ_H
12328 2106120U, // UQSHLR_ZPmZ_S
12329 8840U, // UQSHL_ZPmI_B
12330 8584U, // UQSHL_ZPmI_D
12331 90824U, // UQSHL_ZPmI_H
12332 8968U, // UQSHL_ZPmI_S
12333 533128U, // UQSHL_ZPmZ_B
12334 1057160U, // UQSHL_ZPmZ_D
12335 1614536U, // UQSHL_ZPmZ_H
12336 2106120U, // UQSHL_ZPmZ_S
12337 197U, // UQSHLb
12338 197U, // UQSHLd
12339 197U, // UQSHLh
12340 197U, // UQSHLs
12341 49673U, // UQSHLv16i8
12342 201U, // UQSHLv16i8_shift
12343 197U, // UQSHLv1i16
12344 197U, // UQSHLv1i32
12345 197U, // UQSHLv1i64
12346 197U, // UQSHLv1i8
12347 57865U, // UQSHLv2i32
12348 201U, // UQSHLv2i32_shift
12349 16902U, // UQSHLv2i64
12350 198U, // UQSHLv2i64_shift
12351 66058U, // UQSHLv4i16
12352 202U, // UQSHLv4i16_shift
12353 25095U, // UQSHLv4i32
12354 199U, // UQSHLv4i32_shift
12355 33287U, // UQSHLv8i16
12356 199U, // UQSHLv8i16_shift
12357 74250U, // UQSHLv8i8
12358 202U, // UQSHLv8i8_shift
12359 197U, // UQSHRNB_ZZI_B
12360 12U, // UQSHRNB_ZZI_H
12361 197U, // UQSHRNB_ZZI_S
12362 2373U, // UQSHRNT_ZZI_B
12363 20U, // UQSHRNT_ZZI_H
12364 2373U, // UQSHRNT_ZZI_S
12365 197U, // UQSHRNb
12366 197U, // UQSHRNh
12367 197U, // UQSHRNs
12368 2375U, // UQSHRNv16i8_shift
12369 198U, // UQSHRNv2i32_shift
12370 199U, // UQSHRNv4i16_shift
12371 2374U, // UQSHRNv4i32_shift
12372 2375U, // UQSHRNv8i16_shift
12373 199U, // UQSHRNv8i8_shift
12374 533128U, // UQSUBR_ZPmZ_B
12375 1057160U, // UQSUBR_ZPmZ_D
12376 1614536U, // UQSUBR_ZPmZ_H
12377 2106120U, // UQSUBR_ZPmZ_S
12378 1029U, // UQSUB_ZI_B
12379 1093U, // UQSUB_ZI_D
12380 11U, // UQSUB_ZI_H
12381 1157U, // UQSUB_ZI_S
12382 533128U, // UQSUB_ZPmZ_B
12383 1057160U, // UQSUB_ZPmZ_D
12384 1614536U, // UQSUB_ZPmZ_H
12385 2106120U, // UQSUB_ZPmZ_S
12386 645U, // UQSUB_ZZZ_B
12387 389U, // UQSUB_ZZZ_D
12388 8U, // UQSUB_ZZZ_H
12389 773U, // UQSUB_ZZZ_S
12390 49673U, // UQSUBv16i8
12391 197U, // UQSUBv1i16
12392 197U, // UQSUBv1i32
12393 197U, // UQSUBv1i64
12394 197U, // UQSUBv1i8
12395 57865U, // UQSUBv2i32
12396 16902U, // UQSUBv2i64
12397 66058U, // UQSUBv4i16
12398 25095U, // UQSUBv4i32
12399 33287U, // UQSUBv8i16
12400 74250U, // UQSUBv8i8
12401 2U, // UQXTNB_ZZ_B
12402 0U, // UQXTNB_ZZ_H
12403 2U, // UQXTNB_ZZ_S
12404 2U, // UQXTNT_ZZ_B
12405 0U, // UQXTNT_ZZ_H
12406 2U, // UQXTNT_ZZ_S
12407 4U, // UQXTNv16i8
12408 2U, // UQXTNv1i16
12409 2U, // UQXTNv1i32
12410 2U, // UQXTNv1i8
12411 3U, // UQXTNv2i32
12412 4U, // UQXTNv4i16
12413 3U, // UQXTNv4i32
12414 4U, // UQXTNv8i16
12415 4U, // UQXTNv8i8
12416 1U, // URECPE_ZPmZ_S
12417 2U, // URECPEv2i32
12418 4U, // URECPEv4i32
12419 533128U, // URHADD_ZPmZ_B
12420 1057160U, // URHADD_ZPmZ_D
12421 1614536U, // URHADD_ZPmZ_H
12422 2106120U, // URHADD_ZPmZ_S
12423 49673U, // URHADDv16i8
12424 57865U, // URHADDv2i32
12425 66058U, // URHADDv4i16
12426 25095U, // URHADDv4i32
12427 33287U, // URHADDv8i16
12428 74250U, // URHADDv8i8
12429 533128U, // URSHLR_ZPmZ_B
12430 1057160U, // URSHLR_ZPmZ_D
12431 1614536U, // URSHLR_ZPmZ_H
12432 2106120U, // URSHLR_ZPmZ_S
12433 533128U, // URSHL_ZPmZ_B
12434 1057160U, // URSHL_ZPmZ_D
12435 1614536U, // URSHL_ZPmZ_H
12436 2106120U, // URSHL_ZPmZ_S
12437 49673U, // URSHLv16i8
12438 197U, // URSHLv1i64
12439 57865U, // URSHLv2i32
12440 16902U, // URSHLv2i64
12441 66058U, // URSHLv4i16
12442 25095U, // URSHLv4i32
12443 33287U, // URSHLv8i16
12444 74250U, // URSHLv8i8
12445 8840U, // URSHR_ZPmI_B
12446 8584U, // URSHR_ZPmI_D
12447 90824U, // URSHR_ZPmI_H
12448 8968U, // URSHR_ZPmI_S
12449 197U, // URSHRd
12450 201U, // URSHRv16i8_shift
12451 201U, // URSHRv2i32_shift
12452 198U, // URSHRv2i64_shift
12453 202U, // URSHRv4i16_shift
12454 199U, // URSHRv4i32_shift
12455 199U, // URSHRv8i16_shift
12456 202U, // URSHRv8i8_shift
12457 1U, // URSQRTE_ZPmZ_S
12458 2U, // URSQRTEv2i32
12459 4U, // URSQRTEv4i32
12460 20U, // URSRA_ZZI_B
12461 2373U, // URSRA_ZZI_D
12462 20U, // URSRA_ZZI_H
12463 2373U, // URSRA_ZZI_S
12464 2373U, // URSRAd
12465 2377U, // URSRAv16i8_shift
12466 2377U, // URSRAv2i32_shift
12467 2374U, // URSRAv2i64_shift
12468 2378U, // URSRAv4i16_shift
12469 2375U, // URSRAv4i32_shift
12470 2375U, // URSRAv8i16_shift
12471 2378U, // URSRAv8i8_shift
12472 0U, // USDOT_ZZZ
12473 2432U, // USDOT_ZZZI
12474 311881U, // USDOTlanev16i8
12475 311882U, // USDOTlanev8i8
12476 49737U, // USDOTv16i8
12477 74314U, // USDOTv8i8
12478 197U, // USHLLB_ZZI_D
12479 12U, // USHLLB_ZZI_H
12480 197U, // USHLLB_ZZI_S
12481 197U, // USHLLT_ZZI_D
12482 12U, // USHLLT_ZZI_H
12483 197U, // USHLLT_ZZI_S
12484 201U, // USHLLv16i8_shift
12485 201U, // USHLLv2i32_shift
12486 202U, // USHLLv4i16_shift
12487 199U, // USHLLv4i32_shift
12488 199U, // USHLLv8i16_shift
12489 202U, // USHLLv8i8_shift
12490 49673U, // USHLv16i8
12491 197U, // USHLv1i64
12492 57865U, // USHLv2i32
12493 16902U, // USHLv2i64
12494 66058U, // USHLv4i16
12495 25095U, // USHLv4i32
12496 33287U, // USHLv8i16
12497 74250U, // USHLv8i8
12498 197U, // USHRd
12499 201U, // USHRv16i8_shift
12500 201U, // USHRv2i32_shift
12501 198U, // USHRv2i64_shift
12502 202U, // USHRv4i16_shift
12503 199U, // USHRv4i32_shift
12504 199U, // USHRv8i16_shift
12505 202U, // USHRv8i8_shift
12506 49737U, // USMMLA
12507 0U, // USMMLA_ZZZ
12508 533128U, // USQADD_ZPmZ_B
12509 1057160U, // USQADD_ZPmZ_D
12510 1614536U, // USQADD_ZPmZ_H
12511 2106120U, // USQADD_ZPmZ_S
12512 1U, // USQADDv16i8
12513 2U, // USQADDv1i16
12514 2U, // USQADDv1i32
12515 2U, // USQADDv1i64
12516 2U, // USQADDv1i8
12517 2U, // USQADDv2i32
12518 3U, // USQADDv2i64
12519 3U, // USQADDv4i16
12520 4U, // USQADDv4i32
12521 4U, // USQADDv8i16
12522 5U, // USQADDv8i8
12523 20U, // USRA_ZZI_B
12524 2373U, // USRA_ZZI_D
12525 20U, // USRA_ZZI_H
12526 2373U, // USRA_ZZI_S
12527 2373U, // USRAd
12528 2377U, // USRAv16i8_shift
12529 2377U, // USRAv2i32_shift
12530 2374U, // USRAv2i64_shift
12531 2378U, // USRAv4i16_shift
12532 2375U, // USRAv4i32_shift
12533 2375U, // USRAv8i16_shift
12534 2378U, // USRAv8i8_shift
12535 773U, // USUBLB_ZZZ_D
12536 31U, // USUBLB_ZZZ_H
12537 325U, // USUBLB_ZZZ_S
12538 773U, // USUBLT_ZZZ_D
12539 31U, // USUBLT_ZZZ_H
12540 325U, // USUBLT_ZZZ_S
12541 49673U, // USUBLv16i8_v8i16
12542 57865U, // USUBLv2i32_v2i64
12543 66058U, // USUBLv4i16_v4i32
12544 25095U, // USUBLv4i32_v2i64
12545 33287U, // USUBLv8i16_v4i32
12546 74250U, // USUBLv8i8_v8i16
12547 773U, // USUBWB_ZZZ_D
12548 31U, // USUBWB_ZZZ_H
12549 325U, // USUBWB_ZZZ_S
12550 773U, // USUBWT_ZZZ_D
12551 31U, // USUBWT_ZZZ_H
12552 325U, // USUBWT_ZZZ_S
12553 49671U, // USUBWv16i8_v8i16
12554 57862U, // USUBWv2i32_v2i64
12555 66055U, // USUBWv4i16_v4i32
12556 25094U, // USUBWv4i32_v2i64
12557 33287U, // USUBWv8i16_v4i32
12558 74247U, // USUBWv8i8_v8i16
12559 2U, // UUNPKHI_ZZ_D
12560 0U, // UUNPKHI_ZZ_H
12561 2U, // UUNPKHI_ZZ_S
12562 2U, // UUNPKLO_ZZ_D
12563 0U, // UUNPKLO_ZZ_H
12564 2U, // UUNPKLO_ZZ_S
12565 0U, // UXTB_ZPmZ_D
12566 0U, // UXTB_ZPmZ_H
12567 1U, // UXTB_ZPmZ_S
12568 0U, // UXTH_ZPmZ_D
12569 1U, // UXTH_ZPmZ_S
12570 0U, // UXTW_ZPmZ_D
12571 645U, // UZP1_PPP_B
12572 389U, // UZP1_PPP_D
12573 8U, // UZP1_PPP_H
12574 773U, // UZP1_PPP_S
12575 645U, // UZP1_ZZZ_B
12576 389U, // UZP1_ZZZ_D
12577 8U, // UZP1_ZZZ_H
12578 49U, // UZP1_ZZZ_Q
12579 773U, // UZP1_ZZZ_S
12580 49673U, // UZP1v16i8
12581 57865U, // UZP1v2i32
12582 16902U, // UZP1v2i64
12583 66058U, // UZP1v4i16
12584 25095U, // UZP1v4i32
12585 33287U, // UZP1v8i16
12586 74250U, // UZP1v8i8
12587 645U, // UZP2_PPP_B
12588 389U, // UZP2_PPP_D
12589 8U, // UZP2_PPP_H
12590 773U, // UZP2_PPP_S
12591 645U, // UZP2_ZZZ_B
12592 389U, // UZP2_ZZZ_D
12593 8U, // UZP2_ZZZ_H
12594 49U, // UZP2_ZZZ_Q
12595 773U, // UZP2_ZZZ_S
12596 49673U, // UZP2v16i8
12597 57865U, // UZP2v2i32
12598 16902U, // UZP2v2i64
12599 66058U, // UZP2v4i16
12600 25095U, // UZP2v4i32
12601 33287U, // UZP2v8i16
12602 74250U, // UZP2v8i8
12603 0U, // WFET
12604 0U, // WFIT
12605 197U, // WHILEGE_PWW_B
12606 197U, // WHILEGE_PWW_D
12607 12U, // WHILEGE_PWW_H
12608 197U, // WHILEGE_PWW_S
12609 197U, // WHILEGE_PXX_B
12610 197U, // WHILEGE_PXX_D
12611 12U, // WHILEGE_PXX_H
12612 197U, // WHILEGE_PXX_S
12613 197U, // WHILEGT_PWW_B
12614 197U, // WHILEGT_PWW_D
12615 12U, // WHILEGT_PWW_H
12616 197U, // WHILEGT_PWW_S
12617 197U, // WHILEGT_PXX_B
12618 197U, // WHILEGT_PXX_D
12619 12U, // WHILEGT_PXX_H
12620 197U, // WHILEGT_PXX_S
12621 197U, // WHILEHI_PWW_B
12622 197U, // WHILEHI_PWW_D
12623 12U, // WHILEHI_PWW_H
12624 197U, // WHILEHI_PWW_S
12625 197U, // WHILEHI_PXX_B
12626 197U, // WHILEHI_PXX_D
12627 12U, // WHILEHI_PXX_H
12628 197U, // WHILEHI_PXX_S
12629 197U, // WHILEHS_PWW_B
12630 197U, // WHILEHS_PWW_D
12631 12U, // WHILEHS_PWW_H
12632 197U, // WHILEHS_PWW_S
12633 197U, // WHILEHS_PXX_B
12634 197U, // WHILEHS_PXX_D
12635 12U, // WHILEHS_PXX_H
12636 197U, // WHILEHS_PXX_S
12637 197U, // WHILELE_PWW_B
12638 197U, // WHILELE_PWW_D
12639 12U, // WHILELE_PWW_H
12640 197U, // WHILELE_PWW_S
12641 197U, // WHILELE_PXX_B
12642 197U, // WHILELE_PXX_D
12643 12U, // WHILELE_PXX_H
12644 197U, // WHILELE_PXX_S
12645 197U, // WHILELO_PWW_B
12646 197U, // WHILELO_PWW_D
12647 12U, // WHILELO_PWW_H
12648 197U, // WHILELO_PWW_S
12649 197U, // WHILELO_PXX_B
12650 197U, // WHILELO_PXX_D
12651 12U, // WHILELO_PXX_H
12652 197U, // WHILELO_PXX_S
12653 197U, // WHILELS_PWW_B
12654 197U, // WHILELS_PWW_D
12655 12U, // WHILELS_PWW_H
12656 197U, // WHILELS_PWW_S
12657 197U, // WHILELS_PXX_B
12658 197U, // WHILELS_PXX_D
12659 12U, // WHILELS_PXX_H
12660 197U, // WHILELS_PXX_S
12661 197U, // WHILELT_PWW_B
12662 197U, // WHILELT_PWW_D
12663 12U, // WHILELT_PWW_H
12664 197U, // WHILELT_PWW_S
12665 197U, // WHILELT_PXX_B
12666 197U, // WHILELT_PXX_D
12667 12U, // WHILELT_PXX_H
12668 197U, // WHILELT_PXX_S
12669 197U, // WHILERW_PXX_B
12670 197U, // WHILERW_PXX_D
12671 12U, // WHILERW_PXX_H
12672 197U, // WHILERW_PXX_S
12673 197U, // WHILEWR_PXX_B
12674 197U, // WHILEWR_PXX_D
12675 12U, // WHILEWR_PXX_H
12676 197U, // WHILEWR_PXX_S
12677 0U, // WRFFR
12678 0U, // XAFLAG
12679 197126U, // XAR
12680 8837U, // XAR_ZZZI_B
12681 8581U, // XAR_ZZZI_D
12682 90824U, // XAR_ZZZI_H
12683 8965U, // XAR_ZZZI_S
12684 0U, // XPACD
12685 0U, // XPACI
12686 0U, // XPACLRI
12687 4U, // XTNv16i8
12688 3U, // XTNv2i32
12689 4U, // XTNv4i16
12690 3U, // XTNv4i32
12691 4U, // XTNv8i16
12692 4U, // XTNv8i8
12693 645U, // ZIP1_PPP_B
12694 389U, // ZIP1_PPP_D
12695 8U, // ZIP1_PPP_H
12696 773U, // ZIP1_PPP_S
12697 645U, // ZIP1_ZZZ_B
12698 389U, // ZIP1_ZZZ_D
12699 8U, // ZIP1_ZZZ_H
12700 49U, // ZIP1_ZZZ_Q
12701 773U, // ZIP1_ZZZ_S
12702 49673U, // ZIP1v16i8
12703 57865U, // ZIP1v2i32
12704 16902U, // ZIP1v2i64
12705 66058U, // ZIP1v4i16
12706 25095U, // ZIP1v4i32
12707 33287U, // ZIP1v8i16
12708 74250U, // ZIP1v8i8
12709 645U, // ZIP2_PPP_B
12710 389U, // ZIP2_PPP_D
12711 8U, // ZIP2_PPP_H
12712 773U, // ZIP2_PPP_S
12713 645U, // ZIP2_ZZZ_B
12714 389U, // ZIP2_ZZZ_D
12715 8U, // ZIP2_ZZZ_H
12716 49U, // ZIP2_ZZZ_Q
12717 773U, // ZIP2_ZZZ_S
12718 49673U, // ZIP2v16i8
12719 57865U, // ZIP2v2i32
12720 16902U, // ZIP2v2i64
12721 66058U, // ZIP2v4i16
12722 25095U, // ZIP2v4i32
12723 33287U, // ZIP2v8i16
12724 74250U, // ZIP2v8i8
12725 };
12726
12727 // Emit the opcode for the instruction.
12728 uint64_t Bits = 0;
12729 Bits |= (uint64_t)OpInfo0[MI->getOpcode()] << 0;
12730 Bits |= (uint64_t)OpInfo1[MI->getOpcode()] << 32;
12731 return {AsmStrs+(Bits & 8191)-1, Bits};
12732
12733}
12734/// printInstruction - This method is automatically generated by tablegen
12735/// from the instruction set description.
12736void AArch64InstPrinter::printInstruction(const MCInst *MI, uint64_t Address, const MCSubtargetInfo &STI, raw_ostream &O) {
12737 O << "\t";
12738
12739 auto MnemonicInfo = getMnemonic(MI);
12740
12741 O << MnemonicInfo.first;
12742
12743 uint64_t Bits = MnemonicInfo.second;
12744 assert(Bits != 0 && "Cannot print this instruction.");
12745
12746 // Fragment 0 encoded into 6 bits for 60 unique commands.
12747 switch ((Bits >> 13) & 63) {
12748 default: llvm_unreachable("Invalid command number.");
12749 case 0:
12750 // DBG_VALUE, DBG_INSTR_REF, DBG_LABEL, BUNDLE, LIFETIME_START, LIFETIME_...
12751 return;
12752 break;
12753 case 1:
12754 // TLSDESCCALL, ABSv1i64, ADCSWr, ADCSXr, ADCWr, ADCXr, ADDG, ADDPL_XXI, ...
12755 printOperand(MI, 0, STI, O);
12756 break;
12757 case 2:
12758 // ABS_ZPmZ_B, ADDHNB_ZZZ_B, ADDHNT_ZZZ_B, ADDP_ZPmZ_B, ADD_ZI_B, ADD_ZPm...
12759 printSVERegOp<'b'>(MI, 0, STI, O);
12760 break;
12761 case 3:
12762 // ABS_ZPmZ_D, ADCLB_ZZZ_D, ADCLT_ZZZ_D, ADDP_ZPmZ_D, ADD_ZI_D, ADD_ZPmZ_...
12763 printSVERegOp<'d'>(MI, 0, STI, O);
12764 break;
12765 case 4:
12766 // ABS_ZPmZ_H, ADDHNB_ZZZ_H, ADDHNT_ZZZ_H, ADDP_ZPmZ_H, ADD_ZI_H, ADD_ZPm...
12767 printSVERegOp<'h'>(MI, 0, STI, O);
12768 O << ", ";
12769 break;
12770 case 5:
12771 // ABS_ZPmZ_S, ADCLB_ZZZ_S, ADCLT_ZZZ_S, ADDHNB_ZZZ_S, ADDHNT_ZZZ_S, ADDP...
12772 printSVERegOp<'s'>(MI, 0, STI, O);
12773 break;
12774 case 6:
12775 // ABSv16i8, ABSv2i32, ABSv2i64, ABSv4i16, ABSv4i32, ABSv8i16, ABSv8i8, A...
12776 printVRegOperand(MI, 0, STI, O);
12777 break;
12778 case 7:
12779 // ADDHNv2i64_v4i32, ADDHNv4i32_v8i16, ADDHNv8i16_v16i8, AESDrr, AESErr, ...
12780 printVRegOperand(MI, 1, STI, O);
12781 break;
12782 case 8:
12783 // ANDV_VPZ_B, EORV_VPZ_B, ORV_VPZ_B, SMAXV_VPZ_B, SMINV_VPZ_B, UMAXV_VPZ...
12784 printZPRasFPR<8>(MI, 0, STI, O);
12785 O << ", ";
12786 printSVERegOp<>(MI, 1, STI, O);
12787 O << ", ";
12788 printSVERegOp<'b'>(MI, 2, STI, O);
12789 return;
12790 break;
12791 case 9:
12792 // ANDV_VPZ_D, EORV_VPZ_D, FADDA_VPZ_D, FADDV_VPZ_D, FMAXNMV_VPZ_D, FMAXV...
12793 printZPRasFPR<64>(MI, 0, STI, O);
12794 O << ", ";
12795 printSVERegOp<>(MI, 1, STI, O);
12796 O << ", ";
12797 break;
12798 case 10:
12799 // ANDV_VPZ_H, EORV_VPZ_H, FADDA_VPZ_H, FADDV_VPZ_H, FMAXNMV_VPZ_H, FMAXV...
12800 printZPRasFPR<16>(MI, 0, STI, O);
12801 O << ", ";
12802 printSVERegOp<>(MI, 1, STI, O);
12803 O << ", ";
12804 break;
12805 case 11:
12806 // ANDV_VPZ_S, EORV_VPZ_S, FADDA_VPZ_S, FADDV_VPZ_S, FMAXNMV_VPZ_S, FMAXV...
12807 printZPRasFPR<32>(MI, 0, STI, O);
12808 O << ", ";
12809 printSVERegOp<>(MI, 1, STI, O);
12810 O << ", ";
12811 break;
12812 case 12:
12813 // B, BL
12814 printAlignedLabel(MI, Address, 0, STI, O);
12815 return;
12816 break;
12817 case 13:
12818 // BRK, DCPS1, DCPS2, DCPS3, HLT, HVC, SMC, SVC, TCANCEL
12819 printImmHex(MI, 0, STI, O);
12820 return;
12821 break;
12822 case 14:
12823 // Bcc
12824 printCondCode(MI, 0, STI, O);
12825 O << "\t";
12826 printAlignedLabel(MI, Address, 1, STI, O);
12827 return;
12828 break;
12829 case 15:
12830 // CASAB, CASAH, CASALB, CASALH, CASALW, CASALX, CASAW, CASAX, CASB, CASH...
12831 printOperand(MI, 1, STI, O);
12832 break;
12833 case 16:
12834 // CASPALW, CASPAW, CASPLW, CASPW
12835 printGPRSeqPairsClassOperand<32>(MI, 1, STI, O);
12836 O << ", ";
12837 printGPRSeqPairsClassOperand<32>(MI, 2, STI, O);
12838 O << ", [";
12839 printOperand(MI, 3, STI, O);
12840 O << ']';
12841 return;
12842 break;
12843 case 17:
12844 // CASPALX, CASPAX, CASPLX, CASPX
12845 printGPRSeqPairsClassOperand<64>(MI, 1, STI, O);
12846 O << ", ";
12847 printGPRSeqPairsClassOperand<64>(MI, 2, STI, O);
12848 O << ", [";
12849 printOperand(MI, 3, STI, O);
12850 O << ']';
12851 return;
12852 break;
12853 case 18:
12854 // DMB, DSB, ISB, TSB
12855 printBarrierOption(MI, 0, STI, O);
12856 return;
12857 break;
12858 case 19:
12859 // DSBnXS
12860 printBarriernXSOption(MI, 0, STI, O);
12861 return;
12862 break;
12863 case 20:
12864 // DUP_ZZI_Q, PMULLB_ZZZ_Q, PMULLT_ZZZ_Q, TRN1_ZZZ_Q, TRN2_ZZZ_Q, UZP1_ZZ...
12865 printSVERegOp<'q'>(MI, 0, STI, O);
12866 O << ", ";
12867 break;
12868 case 21:
12869 // GLD1B_D_IMM_REAL, GLD1B_D_REAL, GLD1B_D_SXTW_REAL, GLD1B_D_UXTW_REAL, ...
12870 printTypedVectorList<0,'d'>(MI, 0, STI, O);
12871 O << ", ";
12872 printSVERegOp<>(MI, 1, STI, O);
12873 break;
12874 case 22:
12875 // GLD1B_S_IMM_REAL, GLD1B_S_SXTW_REAL, GLD1B_S_UXTW_REAL, GLD1H_S_IMM_RE...
12876 printTypedVectorList<0,'s'>(MI, 0, STI, O);
12877 O << ", ";
12878 printSVERegOp<>(MI, 1, STI, O);
12879 break;
12880 case 23:
12881 // HINT
12882 printImm(MI, 0, STI, O);
12883 return;
12884 break;
12885 case 24:
12886 // LD1B, LD1B_IMM_REAL, LD1RB_IMM, LD1RO_B, LD1RO_B_IMM, LD1RQ_B, LD1RQ_B...
12887 printTypedVectorList<0,'b'>(MI, 0, STI, O);
12888 O << ", ";
12889 printSVERegOp<>(MI, 1, STI, O);
12890 break;
12891 case 25:
12892 // LD1B_H, LD1B_H_IMM_REAL, LD1H, LD1H_IMM_REAL, LD1RB_H_IMM, LD1RH_IMM, ...
12893 printTypedVectorList<0,'h'>(MI, 0, STI, O);
12894 O << ", ";
12895 printSVERegOp<>(MI, 1, STI, O);
12896 break;
12897 case 26:
12898 // LD1Fourv16b, LD1Onev16b, LD1Rv16b, LD1Threev16b, LD1Twov16b, LD2Rv16b,...
12899 printTypedVectorList<16, 'b'>(MI, 0, STI, O);
12900 O << ", [";
12901 printOperand(MI, 1, STI, O);
12902 O << ']';
12903 return;
12904 break;
12905 case 27:
12906 // LD1Fourv16b_POST, LD1Onev16b_POST, LD1Rv16b_POST, LD1Threev16b_POST, L...
12907 printTypedVectorList<16, 'b'>(MI, 1, STI, O);
12908 O << ", [";
12909 printOperand(MI, 2, STI, O);
12910 O << "], ";
12911 break;
12912 case 28:
12913 // LD1Fourv1d, LD1Onev1d, LD1Rv1d, LD1Threev1d, LD1Twov1d, LD2Rv1d, LD3Rv...
12914 printTypedVectorList<1, 'd'>(MI, 0, STI, O);
12915 O << ", [";
12916 printOperand(MI, 1, STI, O);
12917 O << ']';
12918 return;
12919 break;
12920 case 29:
12921 // LD1Fourv1d_POST, LD1Onev1d_POST, LD1Rv1d_POST, LD1Threev1d_POST, LD1Tw...
12922 printTypedVectorList<1, 'd'>(MI, 1, STI, O);
12923 O << ", [";
12924 printOperand(MI, 2, STI, O);
12925 O << "], ";
12926 break;
12927 case 30:
12928 // LD1Fourv2d, LD1Onev2d, LD1Rv2d, LD1Threev2d, LD1Twov2d, LD2Rv2d, LD2Tw...
12929 printTypedVectorList<2, 'd'>(MI, 0, STI, O);
12930 O << ", [";
12931 printOperand(MI, 1, STI, O);
12932 O << ']';
12933 return;
12934 break;
12935 case 31:
12936 // LD1Fourv2d_POST, LD1Onev2d_POST, LD1Rv2d_POST, LD1Threev2d_POST, LD1Tw...
12937 printTypedVectorList<2, 'd'>(MI, 1, STI, O);
12938 O << ", [";
12939 printOperand(MI, 2, STI, O);
12940 O << "], ";
12941 break;
12942 case 32:
12943 // LD1Fourv2s, LD1Onev2s, LD1Rv2s, LD1Threev2s, LD1Twov2s, LD2Rv2s, LD2Tw...
12944 printTypedVectorList<2, 's'>(MI, 0, STI, O);
12945 O << ", [";
12946 printOperand(MI, 1, STI, O);
12947 O << ']';
12948 return;
12949 break;
12950 case 33:
12951 // LD1Fourv2s_POST, LD1Onev2s_POST, LD1Rv2s_POST, LD1Threev2s_POST, LD1Tw...
12952 printTypedVectorList<2, 's'>(MI, 1, STI, O);
12953 O << ", [";
12954 printOperand(MI, 2, STI, O);
12955 O << "], ";
12956 break;
12957 case 34:
12958 // LD1Fourv4h, LD1Onev4h, LD1Rv4h, LD1Threev4h, LD1Twov4h, LD2Rv4h, LD2Tw...
12959 printTypedVectorList<4, 'h'>(MI, 0, STI, O);
12960 O << ", [";
12961 printOperand(MI, 1, STI, O);
12962 O << ']';
12963 return;
12964 break;
12965 case 35:
12966 // LD1Fourv4h_POST, LD1Onev4h_POST, LD1Rv4h_POST, LD1Threev4h_POST, LD1Tw...
12967 printTypedVectorList<4, 'h'>(MI, 1, STI, O);
12968 O << ", [";
12969 printOperand(MI, 2, STI, O);
12970 O << "], ";
12971 break;
12972 case 36:
12973 // LD1Fourv4s, LD1Onev4s, LD1Rv4s, LD1Threev4s, LD1Twov4s, LD2Rv4s, LD2Tw...
12974 printTypedVectorList<4, 's'>(MI, 0, STI, O);
12975 O << ", [";
12976 printOperand(MI, 1, STI, O);
12977 O << ']';
12978 return;
12979 break;
12980 case 37:
12981 // LD1Fourv4s_POST, LD1Onev4s_POST, LD1Rv4s_POST, LD1Threev4s_POST, LD1Tw...
12982 printTypedVectorList<4, 's'>(MI, 1, STI, O);
12983 O << ", [";
12984 printOperand(MI, 2, STI, O);
12985 O << "], ";
12986 break;
12987 case 38:
12988 // LD1Fourv8b, LD1Onev8b, LD1Rv8b, LD1Threev8b, LD1Twov8b, LD2Rv8b, LD2Tw...
12989 printTypedVectorList<8, 'b'>(MI, 0, STI, O);
12990 O << ", [";
12991 printOperand(MI, 1, STI, O);
12992 O << ']';
12993 return;
12994 break;
12995 case 39:
12996 // LD1Fourv8b_POST, LD1Onev8b_POST, LD1Rv8b_POST, LD1Threev8b_POST, LD1Tw...
12997 printTypedVectorList<8, 'b'>(MI, 1, STI, O);
12998 O << ", [";
12999 printOperand(MI, 2, STI, O);
13000 O << "], ";
13001 break;
13002 case 40:
13003 // LD1Fourv8h, LD1Onev8h, LD1Rv8h, LD1Threev8h, LD1Twov8h, LD2Rv8h, LD2Tw...
13004 printTypedVectorList<8, 'h'>(MI, 0, STI, O);
13005 O << ", [";
13006 printOperand(MI, 1, STI, O);
13007 O << ']';
13008 return;
13009 break;
13010 case 41:
13011 // LD1Fourv8h_POST, LD1Onev8h_POST, LD1Rv8h_POST, LD1Threev8h_POST, LD1Tw...
13012 printTypedVectorList<8, 'h'>(MI, 1, STI, O);
13013 O << ", [";
13014 printOperand(MI, 2, STI, O);
13015 O << "], ";
13016 break;
13017 case 42:
13018 // LD1i16, LD2i16, LD3i16, LD4i16, ST1i16_POST, ST2i16_POST, ST3i16_POST,...
13019 printTypedVectorList<0, 'h'>(MI, 1, STI, O);
13020 printVectorIndex(MI, 2, STI, O);
13021 O << ", [";
13022 printOperand(MI, 3, STI, O);
13023 break;
13024 case 43:
13025 // LD1i16_POST, LD2i16_POST, LD3i16_POST, LD4i16_POST
13026 printTypedVectorList<0, 'h'>(MI, 2, STI, O);
13027 printVectorIndex(MI, 3, STI, O);
13028 O << ", [";
13029 printOperand(MI, 4, STI, O);
13030 O << "], ";
13031 break;
13032 case 44:
13033 // LD1i32, LD2i32, LD3i32, LD4i32, ST1i32_POST, ST2i32_POST, ST3i32_POST,...
13034 printTypedVectorList<0, 's'>(MI, 1, STI, O);
13035 printVectorIndex(MI, 2, STI, O);
13036 O << ", [";
13037 printOperand(MI, 3, STI, O);
13038 break;
13039 case 45:
13040 // LD1i32_POST, LD2i32_POST, LD3i32_POST, LD4i32_POST
13041 printTypedVectorList<0, 's'>(MI, 2, STI, O);
13042 printVectorIndex(MI, 3, STI, O);
13043 O << ", [";
13044 printOperand(MI, 4, STI, O);
13045 O << "], ";
13046 break;
13047 case 46:
13048 // LD1i64, LD2i64, LD3i64, LD4i64, ST1i64_POST, ST2i64_POST, ST3i64_POST,...
13049 printTypedVectorList<0, 'd'>(MI, 1, STI, O);
13050 printVectorIndex(MI, 2, STI, O);
13051 O << ", [";
13052 printOperand(MI, 3, STI, O);
13053 break;
13054 case 47:
13055 // LD1i64_POST, LD2i64_POST, LD3i64_POST, LD4i64_POST
13056 printTypedVectorList<0, 'd'>(MI, 2, STI, O);
13057 printVectorIndex(MI, 3, STI, O);
13058 O << ", [";
13059 printOperand(MI, 4, STI, O);
13060 O << "], ";
13061 break;
13062 case 48:
13063 // LD1i8, LD2i8, LD3i8, LD4i8, ST1i8_POST, ST2i8_POST, ST3i8_POST, ST4i8_...
13064 printTypedVectorList<0, 'b'>(MI, 1, STI, O);
13065 printVectorIndex(MI, 2, STI, O);
13066 O << ", [";
13067 printOperand(MI, 3, STI, O);
13068 break;
13069 case 49:
13070 // LD1i8_POST, LD2i8_POST, LD3i8_POST, LD4i8_POST
13071 printTypedVectorList<0, 'b'>(MI, 2, STI, O);
13072 printVectorIndex(MI, 3, STI, O);
13073 O << ", [";
13074 printOperand(MI, 4, STI, O);
13075 O << "], ";
13076 break;
13077 case 50:
13078 // LD64B, ST64B
13079 printGPR64x8(MI, 0, STI, O);
13080 O << ", [";
13081 printOperand(MI, 1, STI, O);
13082 O << ']';
13083 return;
13084 break;
13085 case 51:
13086 // LDR_PXI, LDR_ZXI, MOVPRFX_ZZ, PTEST_PP, STR_PXI, STR_ZXI
13087 printSVERegOp<>(MI, 0, STI, O);
13088 break;
13089 case 52:
13090 // MSR
13091 printMSRSystemRegister(MI, 0, STI, O);
13092 O << ", ";
13093 printOperand(MI, 1, STI, O);
13094 return;
13095 break;
13096 case 53:
13097 // MSRpstateImm1, MSRpstateImm4
13098 printSystemPStateField(MI, 0, STI, O);
13099 O << ", ";
13100 printOperand(MI, 1, STI, O);
13101 return;
13102 break;
13103 case 54:
13104 // PRFB_D_PZI, PRFB_D_SCALED, PRFB_D_SXTW_SCALED, PRFB_D_UXTW_SCALED, PRF...
13105 printPrefetchOp<true>(MI, 0, STI, O);
13106 O << ", ";
13107 printSVERegOp<>(MI, 1, STI, O);
13108 O << ", [";
13109 break;
13110 case 55:
13111 // PRFMl, PRFMroW, PRFMroX, PRFMui, PRFUMi
13112 printPrefetchOp(MI, 0, STI, O);
13113 break;
13114 case 56:
13115 // ST1i16, ST2i16, ST3i16, ST4i16
13116 printTypedVectorList<0, 'h'>(MI, 0, STI, O);
13117 printVectorIndex(MI, 1, STI, O);
13118 O << ", [";
13119 printOperand(MI, 2, STI, O);
13120 O << ']';
13121 return;
13122 break;
13123 case 57:
13124 // ST1i32, ST2i32, ST3i32, ST4i32
13125 printTypedVectorList<0, 's'>(MI, 0, STI, O);
13126 printVectorIndex(MI, 1, STI, O);
13127 O << ", [";
13128 printOperand(MI, 2, STI, O);
13129 O << ']';
13130 return;
13131 break;
13132 case 58:
13133 // ST1i64, ST2i64, ST3i64, ST4i64
13134 printTypedVectorList<0, 'd'>(MI, 0, STI, O);
13135 printVectorIndex(MI, 1, STI, O);
13136 O << ", [";
13137 printOperand(MI, 2, STI, O);
13138 O << ']';
13139 return;
13140 break;
13141 case 59:
13142 // ST1i8, ST2i8, ST3i8, ST4i8
13143 printTypedVectorList<0, 'b'>(MI, 0, STI, O);
13144 printVectorIndex(MI, 1, STI, O);
13145 O << ", [";
13146 printOperand(MI, 2, STI, O);
13147 O << ']';
13148 return;
13149 break;
13150 }
13151
13152
13153 // Fragment 1 encoded into 6 bits for 64 unique commands.
13154 switch ((Bits >> 19) & 63) {
13155 default: llvm_unreachable("Invalid command number.");
13156 case 0:
13157 // TLSDESCCALL, AUTDZA, AUTDZB, AUTIZA, AUTIZB, BLR, BLRAAZ, BLRABZ, BR, ...
13158 return;
13159 break;
13160 case 1:
13161 // ABS_ZPmZ_B, ABS_ZPmZ_D, ABS_ZPmZ_S, ABSv1i64, ADCLB_ZZZ_D, ADCLB_ZZZ_S...
13162 O << ", ";
13163 break;
13164 case 2:
13165 // ABS_ZPmZ_H, BFCVTNT_ZPmZ, BFCVT_ZPmZ, CLS_ZPmZ_H, CLZ_ZPmZ_H, CNOT_ZPm...
13166 printSVERegOp<>(MI, 2, STI, O);
13167 O << "/m, ";
13168 break;
13169 case 3:
13170 // ABSv16i8, ADDHNv8i16_v16i8, ADDPv16i8, ADDv16i8, AESDrr, AESErr, AESIM...
13171 O << ".16b, ";
13172 break;
13173 case 4:
13174 // ABSv2i32, ADDHNv2i64_v2i32, ADDPv2i32, ADDv2i32, BF16DOTlanev4bf16, BF...
13175 O << ".2s, ";
13176 break;
13177 case 5:
13178 // ABSv2i64, ADDPv2i64, ADDv2i64, CMEQv2i64, CMEQv2i64rz, CMGEv2i64, CMGE...
13179 O << ".2d, ";
13180 break;
13181 case 6:
13182 // ABSv4i16, ADDHNv4i32_v4i16, ADDPv4i16, ADDv4i16, BFCVTN, BICv4i16, CLS...
13183 O << ".4h, ";
13184 break;
13185 case 7:
13186 // ABSv4i32, ADDHNv2i64_v4i32, ADDPv4i32, ADDv4i32, BF16DOTlanev8bf16, BF...
13187 O << ".4s, ";
13188 break;
13189 case 8:
13190 // ABSv8i16, ADDHNv4i32_v8i16, ADDPv8i16, ADDv8i16, BFCVTN2, BICv8i16, CL...
13191 O << ".8h, ";
13192 break;
13193 case 9:
13194 // ABSv8i8, ADDHNv8i16_v8i8, ADDPv8i8, ADDv8i8, ANDv8i8, BICv8i8, BIFv8i8...
13195 O << ".8b, ";
13196 break;
13197 case 10:
13198 // ADDHNB_ZZZ_H, RADDHNB_ZZZ_H, RSHRNB_ZZI_H, RSUBHNB_ZZZ_H, SHRNB_ZZI_H,...
13199 printSVERegOp<'s'>(MI, 1, STI, O);
13200 break;
13201 case 11:
13202 // ADDHNT_ZZZ_H, ANDV_VPZ_S, EORV_VPZ_S, FADDV_VPZ_S, FMAXNMV_VPZ_S, FMAX...
13203 printSVERegOp<'s'>(MI, 2, STI, O);
13204 break;
13205 case 12:
13206 // ADDP_ZPmZ_H, ADD_ZPmZ_H, AND_ZPmZ_H, ASRD_ZPmI_H, ASRR_ZPmZ_H, ASR_WID...
13207 printSVERegOp<>(MI, 1, STI, O);
13208 break;
13209 case 13:
13210 // ADD_ZI_H, ADD_ZZZ_H, ASR_WIDE_ZZZ_H, ASR_ZZI_H, BDEP_ZZZ_H, BEXT_ZZZ_H...
13211 printSVERegOp<'h'>(MI, 1, STI, O);
13212 break;
13213 case 14:
13214 // ADR_LSL_ZZZ_D_0, ADR_LSL_ZZZ_D_1, ADR_LSL_ZZZ_D_2, ADR_LSL_ZZZ_D_3, AD...
13215 O << ", [";
13216 break;
13217 case 15:
13218 // ANDV_VPZ_D, EORV_VPZ_D, FADDV_VPZ_D, FMAXNMV_VPZ_D, FMAXV_VPZ_D, FMINN...
13219 printSVERegOp<'d'>(MI, 2, STI, O);
13220 break;
13221 case 16:
13222 // ANDV_VPZ_H, CMLA_ZZZI_H, CMLA_ZZZ_H, DECP_ZP_H, EORBT_ZZZ_H, EORTB_ZZZ...
13223 printSVERegOp<'h'>(MI, 2, STI, O);
13224 break;
13225 case 17:
13226 // DECH_ZPiI, INCH_ZPiI, SQDECH_ZPiI, SQINCH_ZPiI, UQDECH_ZPiI, UQINCH_ZP...
13227 printSVEPattern(MI, 2, STI, O);
13228 O << ", mul ";
13229 printOperand(MI, 3, STI, O);
13230 return;
13231 break;
13232 case 18:
13233 // DUP_ZI_H
13234 printImm8OptLsl<int16_t>(MI, 1, STI, O);
13235 return;
13236 break;
13237 case 19:
13238 // DUP_ZR_H, INDEX_RI_H, INDEX_RR_H, WHILEGE_PWW_H, WHILEGE_PXX_H, WHILEG...
13239 printOperand(MI, 1, STI, O);
13240 break;
13241 case 20:
13242 // DUP_ZZI_Q, TRN1_ZZZ_Q, TRN2_ZZZ_Q, UZP1_ZZZ_Q, UZP2_ZZZ_Q, ZIP1_ZZZ_Q,...
13243 printSVERegOp<'q'>(MI, 1, STI, O);
13244 break;
13245 case 21:
13246 // FADDA_VPZ_D
13247 printZPRasFPR<64>(MI, 2, STI, O);
13248 O << ", ";
13249 printSVERegOp<'d'>(MI, 3, STI, O);
13250 return;
13251 break;
13252 case 22:
13253 // FADDA_VPZ_H
13254 printZPRasFPR<16>(MI, 2, STI, O);
13255 O << ", ";
13256 printSVERegOp<'h'>(MI, 3, STI, O);
13257 return;
13258 break;
13259 case 23:
13260 // FADDA_VPZ_S
13261 printZPRasFPR<32>(MI, 2, STI, O);
13262 O << ", ";
13263 printSVERegOp<'s'>(MI, 3, STI, O);
13264 return;
13265 break;
13266 case 24:
13267 // FCMPDri, FCMPEDri, FCMPEHri, FCMPESri, FCMPHri, FCMPSri
13268 O << ", #0.0";
13269 return;
13270 break;
13271 case 25:
13272 // FDUP_ZI_H
13273 printFPImmOperand(MI, 1, STI, O);
13274 return;
13275 break;
13276 case 26:
13277 // FMOVXDHighr, INSvi64gpr, INSvi64lane
13278 O << ".d";
13279 printVectorIndex(MI, 2, STI, O);
13280 O << ", ";
13281 break;
13282 case 27:
13283 // GLD1B_D_IMM_REAL, GLD1B_D_REAL, GLD1B_D_SXTW_REAL, GLD1B_D_UXTW_REAL, ...
13284 O << "/z, [";
13285 break;
13286 case 28:
13287 // INDEX_II_H, INDEX_IR_H
13288 printSImm<16>(MI, 1, STI, O);
13289 O << ", ";
13290 break;
13291 case 29:
13292 // INSR_ZR_H, INSR_ZV_H, PRFB_D_SCALED, PRFB_D_SXTW_SCALED, PRFB_D_UXTW_S...
13293 printOperand(MI, 2, STI, O);
13294 break;
13295 case 30:
13296 // INSvi16gpr, INSvi16lane
13297 O << ".h";
13298 printVectorIndex(MI, 2, STI, O);
13299 O << ", ";
13300 break;
13301 case 31:
13302 // INSvi32gpr, INSvi32lane
13303 O << ".s";
13304 printVectorIndex(MI, 2, STI, O);
13305 O << ", ";
13306 break;
13307 case 32:
13308 // INSvi8gpr, INSvi8lane
13309 O << ".b";
13310 printVectorIndex(MI, 2, STI, O);
13311 O << ", ";
13312 break;
13313 case 33:
13314 // LD1Fourv16b_POST, LD1Fourv2d_POST, LD1Fourv4s_POST, LD1Fourv8h_POST, L...
13315 printPostIncOperand<64>(MI, 3, STI, O);
13316 return;
13317 break;
13318 case 34:
13319 // LD1Fourv1d_POST, LD1Fourv2s_POST, LD1Fourv4h_POST, LD1Fourv8b_POST, LD...
13320 printPostIncOperand<32>(MI, 3, STI, O);
13321 return;
13322 break;
13323 case 35:
13324 // LD1Onev16b_POST, LD1Onev2d_POST, LD1Onev4s_POST, LD1Onev8h_POST, LD1Tw...
13325 printPostIncOperand<16>(MI, 3, STI, O);
13326 return;
13327 break;
13328 case 36:
13329 // LD1Onev1d_POST, LD1Onev2s_POST, LD1Onev4h_POST, LD1Onev8b_POST, LD1Rv1...
13330 printPostIncOperand<8>(MI, 3, STI, O);
13331 return;
13332 break;
13333 case 37:
13334 // LD1Rv16b_POST, LD1Rv8b_POST
13335 printPostIncOperand<1>(MI, 3, STI, O);
13336 return;
13337 break;
13338 case 38:
13339 // LD1Rv2s_POST, LD1Rv4s_POST, LD2Rv4h_POST, LD2Rv8h_POST, LD4Rv16b_POST,...
13340 printPostIncOperand<4>(MI, 3, STI, O);
13341 return;
13342 break;
13343 case 39:
13344 // LD1Rv4h_POST, LD1Rv8h_POST, LD2Rv16b_POST, LD2Rv8b_POST
13345 printPostIncOperand<2>(MI, 3, STI, O);
13346 return;
13347 break;
13348 case 40:
13349 // LD1Threev16b_POST, LD1Threev2d_POST, LD1Threev4s_POST, LD1Threev8h_POS...
13350 printPostIncOperand<48>(MI, 3, STI, O);
13351 return;
13352 break;
13353 case 41:
13354 // LD1Threev1d_POST, LD1Threev2s_POST, LD1Threev4h_POST, LD1Threev8b_POST...
13355 printPostIncOperand<24>(MI, 3, STI, O);
13356 return;
13357 break;
13358 case 42:
13359 // LD1i16, LD1i32, LD1i64, LD1i8, LD2i16, LD2i32, LD2i64, LD2i8, LD3i16, ...
13360 O << ']';
13361 return;
13362 break;
13363 case 43:
13364 // LD1i16_POST, LD2i8_POST
13365 printPostIncOperand<2>(MI, 5, STI, O);
13366 return;
13367 break;
13368 case 44:
13369 // LD1i32_POST, LD2i16_POST, LD4i8_POST
13370 printPostIncOperand<4>(MI, 5, STI, O);
13371 return;
13372 break;
13373 case 45:
13374 // LD1i64_POST, LD2i32_POST, LD4i16_POST
13375 printPostIncOperand<8>(MI, 5, STI, O);
13376 return;
13377 break;
13378 case 46:
13379 // LD1i8_POST
13380 printPostIncOperand<1>(MI, 5, STI, O);
13381 return;
13382 break;
13383 case 47:
13384 // LD2i64_POST, LD4i32_POST
13385 printPostIncOperand<16>(MI, 5, STI, O);
13386 return;
13387 break;
13388 case 48:
13389 // LD3Rv16b_POST, LD3Rv8b_POST
13390 printPostIncOperand<3>(MI, 3, STI, O);
13391 return;
13392 break;
13393 case 49:
13394 // LD3Rv2s_POST, LD3Rv4s_POST
13395 printPostIncOperand<12>(MI, 3, STI, O);
13396 return;
13397 break;
13398 case 50:
13399 // LD3Rv4h_POST, LD3Rv8h_POST
13400 printPostIncOperand<6>(MI, 3, STI, O);
13401 return;
13402 break;
13403 case 51:
13404 // LD3i16_POST
13405 printPostIncOperand<6>(MI, 5, STI, O);
13406 return;
13407 break;
13408 case 52:
13409 // LD3i32_POST
13410 printPostIncOperand<12>(MI, 5, STI, O);
13411 return;
13412 break;
13413 case 53:
13414 // LD3i64_POST
13415 printPostIncOperand<24>(MI, 5, STI, O);
13416 return;
13417 break;
13418 case 54:
13419 // LD3i8_POST
13420 printPostIncOperand<3>(MI, 5, STI, O);
13421 return;
13422 break;
13423 case 55:
13424 // LD4i64_POST
13425 printPostIncOperand<32>(MI, 5, STI, O);
13426 return;
13427 break;
13428 case 56:
13429 // PMULLB_ZZZ_H, PMULLT_ZZZ_H, PUNPKHI_PP, PUNPKLO_PP, SABDLB_ZZZ_H, SABD...
13430 printSVERegOp<'b'>(MI, 1, STI, O);
13431 break;
13432 case 57:
13433 // PMULLB_ZZZ_Q, PMULLT_ZZZ_Q
13434 printSVERegOp<'d'>(MI, 1, STI, O);
13435 O << ", ";
13436 printSVERegOp<'d'>(MI, 2, STI, O);
13437 return;
13438 break;
13439 case 58:
13440 // PMULLv1i64, PMULLv2i64
13441 O << ".1q, ";
13442 printVRegOperand(MI, 1, STI, O);
13443 break;
13444 case 59:
13445 // PTRUES_H, PTRUE_H
13446 printSVEPattern(MI, 1, STI, O);
13447 return;
13448 break;
13449 case 60:
13450 // SABALB_ZZZ_H, SABALT_ZZZ_H, SADDV_VPZ_B, SMLALB_ZZZ_H, SMLALT_ZZZ_H, S...
13451 printSVERegOp<'b'>(MI, 2, STI, O);
13452 break;
13453 case 61:
13454 // SADALPv2i32_v1i64, SADDLPv2i32_v1i64, UADALPv2i32_v1i64, UADDLPv2i32_v...
13455 O << ".1d, ";
13456 break;
13457 case 62:
13458 // ST1i16_POST, ST1i32_POST, ST1i64_POST, ST1i8_POST, ST2i16_POST, ST2i32...
13459 O << "], ";
13460 break;
13461 case 63:
13462 // TBL_ZZZZ_H, TBL_ZZZ_H
13463 printTypedVectorList<0,'h'>(MI, 1, STI, O);
13464 O << ", ";
13465 printSVERegOp<'h'>(MI, 2, STI, O);
13466 return;
13467 break;
13468 }
13469
13470
13471 // Fragment 2 encoded into 6 bits for 62 unique commands.
13472 switch ((Bits >> 25) & 63) {
13473 default: llvm_unreachable("Invalid command number.");
13474 case 0:
13475 // ABS_ZPmZ_B, ABS_ZPmZ_D, ABS_ZPmZ_S, BRKA_PPmP, BRKB_PPmP, CLS_ZPmZ_B, ...
13476 printSVERegOp<>(MI, 2, STI, O);
13477 O << "/m, ";
13478 break;
13479 case 1:
13480 // ABS_ZPmZ_H, CLS_ZPmZ_H, CLZ_ZPmZ_H, CNOT_ZPmZ_H, CNT_ZPmZ_H, FABS_ZPmZ...
13481 printSVERegOp<'h'>(MI, 3, STI, O);
13482 return;
13483 break;
13484 case 2:
13485 // ABSv16i8, ABSv2i32, ABSv2i64, ABSv4i16, ABSv4i32, ABSv8i16, ABSv8i8, A...
13486 printVRegOperand(MI, 1, STI, O);
13487 break;
13488 case 3:
13489 // ABSv1i64, ADCSWr, ADCSXr, ADCWr, ADCXr, ADDG, ADDPL_XXI, ADDSWri, ADDS...
13490 printOperand(MI, 1, STI, O);
13491 break;
13492 case 4:
13493 // ADCLB_ZZZ_D, ADCLT_ZZZ_D, ADDHNT_ZZZ_S, CMLA_ZZZ_D, DECP_ZP_D, EORBT_Z...
13494 printSVERegOp<'d'>(MI, 2, STI, O);
13495 break;
13496 case 5:
13497 // ADCLB_ZZZ_S, ADCLT_ZZZ_S, CMLA_ZZZI_S, CMLA_ZZZ_S, DECP_ZP_S, EORBT_ZZ...
13498 printSVERegOp<'s'>(MI, 2, STI, O);
13499 break;
13500 case 6:
13501 // ADDHNB_ZZZ_B, DECP_XP_H, INCP_XP_H, RADDHNB_ZZZ_B, RSHRNB_ZZI_B, RSUBH...
13502 printSVERegOp<'h'>(MI, 1, STI, O);
13503 break;
13504 case 7:
13505 // ADDHNB_ZZZ_H, ADDHNT_ZZZ_H, ADD_ZI_H, ADD_ZZZ_H, ASR_WIDE_ZZZ_H, ASR_Z...
13506 O << ", ";
13507 break;
13508 case 8:
13509 // ADDHNB_ZZZ_S, ADD_ZI_D, ADD_ZZZ_D, ADR_LSL_ZZZ_D_0, ADR_LSL_ZZZ_D_1, A...
13510 printSVERegOp<'d'>(MI, 1, STI, O);
13511 break;
13512 case 9:
13513 // ADDHNT_ZZZ_B, BFDOT_ZZI, BFDOT_ZZZ, BFMMLA_B_ZZI, BFMMLA_B_ZZZ, BFMMLA...
13514 printSVERegOp<'h'>(MI, 2, STI, O);
13515 break;
13516 case 10:
13517 // ADDHNv2i64_v4i32, ADDHNv4i32_v8i16, ADDHNv8i16_v16i8, AESDrr, AESErr, ...
13518 printVRegOperand(MI, 2, STI, O);
13519 break;
13520 case 11:
13521 // ADDP_ZPmZ_B, ADDP_ZPmZ_D, ADDP_ZPmZ_S, ADD_ZPmZ_B, ADD_ZPmZ_D, ADD_ZPm...
13522 printSVERegOp<>(MI, 1, STI, O);
13523 break;
13524 case 12:
13525 // ADDP_ZPmZ_H, ADD_ZPmZ_H, AND_ZPmZ_H, ASRD_ZPmI_H, ASRR_ZPmZ_H, ASR_WID...
13526 O << "/m, ";
13527 break;
13528 case 13:
13529 // ADD_ZI_B, ADD_ZZZ_B, AESD_ZZZ_B, AESE_ZZZ_B, AESIMC_ZZ_B, AESMC_ZZ_B, ...
13530 printSVERegOp<'b'>(MI, 1, STI, O);
13531 break;
13532 case 14:
13533 // ADD_ZI_S, ADD_ZZZ_S, ADR_LSL_ZZZ_S_0, ADR_LSL_ZZZ_S_1, ADR_LSL_ZZZ_S_2...
13534 printSVERegOp<'s'>(MI, 1, STI, O);
13535 break;
13536 case 15:
13537 // ADRP
13538 printAdrpLabel(MI, Address, 1, STI, O);
13539 return;
13540 break;
13541 case 16:
13542 // ANDV_VPZ_D, ANDV_VPZ_H, ANDV_VPZ_S, DECP_ZP_H, DUP_ZR_H, EORV_VPZ_D, E...
13543 return;
13544 break;
13545 case 17:
13546 // BFCVTNT_ZPmZ, BFCVT_ZPmZ, FCVTNT_ZPmZ_StoH, FCVT_ZPmZ_StoH, SCVTF_ZPmZ...
13547 printSVERegOp<'s'>(MI, 3, STI, O);
13548 return;
13549 break;
13550 case 18:
13551 // BFMWri, BFMXri, CASAB, CASAH, CASALB, CASALH, CASALW, CASALX, CASAW, C...
13552 printOperand(MI, 2, STI, O);
13553 break;
13554 case 19:
13555 // BICv2i32, BICv4i16, BICv4i32, BICv8i16, MOVKWi, MOVKXi, ORRv2i32, ORRv...
13556 printImm(MI, 2, STI, O);
13557 printShifter(MI, 3, STI, O);
13558 return;
13559 break;
13560 case 20:
13561 // CBNZW, CBNZX, CBZW, CBZX, LDRDl, LDRQl, LDRSWl, LDRSl, LDRWl, LDRXl, P...
13562 printAlignedLabel(MI, Address, 1, STI, O);
13563 return;
13564 break;
13565 case 21:
13566 // CDOT_ZZZI_S, CDOT_ZZZ_S, CMLA_ZZZ_B, EORBT_ZZZ_B, EORTB_ZZZ_B, SABA_ZZ...
13567 printSVERegOp<'b'>(MI, 2, STI, O);
13568 O << ", ";
13569 break;
13570 case 22:
13571 // CMPEQ_PPzZI_H, CMPEQ_PPzZZ_H, CMPEQ_WIDE_PPzZZ_H, CMPGE_PPzZI_H, CMPGE...
13572 O << "/z, ";
13573 break;
13574 case 23:
13575 // CNTB_XPiI, CNTD_XPiI, CNTH_XPiI, CNTW_XPiI, PTRUES_B, PTRUES_D, PTRUES...
13576 printSVEPattern(MI, 1, STI, O);
13577 break;
13578 case 24:
13579 // CPY_ZPmI_H
13580 printImm8OptLsl<int16_t>(MI, 3, STI, O);
13581 return;
13582 break;
13583 case 25:
13584 // CPY_ZPmR_H, CPY_ZPmV_H, INSvi16gpr, INSvi32gpr, INSvi64gpr, INSvi8gpr
13585 printOperand(MI, 3, STI, O);
13586 return;
13587 break;
13588 case 26:
13589 // DECB_XPiI, DECD_XPiI, DECD_ZPiI, DECH_XPiI, DECW_XPiI, DECW_ZPiI, INCB...
13590 printSVEPattern(MI, 2, STI, O);
13591 O << ", mul ";
13592 printOperand(MI, 3, STI, O);
13593 return;
13594 break;
13595 case 27:
13596 // DUPM_ZI
13597 printLogicalImm<int64_t>(MI, 1, STI, O);
13598 return;
13599 break;
13600 case 28:
13601 // DUP_ZI_B
13602 printImm8OptLsl<int8_t>(MI, 1, STI, O);
13603 return;
13604 break;
13605 case 29:
13606 // DUP_ZI_D
13607 printImm8OptLsl<int64_t>(MI, 1, STI, O);
13608 return;
13609 break;
13610 case 30:
13611 // DUP_ZI_S
13612 printImm8OptLsl<int32_t>(MI, 1, STI, O);
13613 return;
13614 break;
13615 case 31:
13616 // DUP_ZZI_H, DUP_ZZI_Q
13617 printVectorIndex(MI, 2, STI, O);
13618 return;
13619 break;
13620 case 32:
13621 // EXT_ZZI_B, TBL_ZZZZ_B, TBL_ZZZ_B
13622 printTypedVectorList<0,'b'>(MI, 1, STI, O);
13623 O << ", ";
13624 break;
13625 case 33:
13626 // FCPY_ZPmI_H
13627 printFPImmOperand(MI, 3, STI, O);
13628 return;
13629 break;
13630 case 34:
13631 // FCVT_ZPmZ_DtoH, SCVTF_ZPmZ_DtoH, UCVTF_ZPmZ_DtoH
13632 printSVERegOp<'d'>(MI, 3, STI, O);
13633 return;
13634 break;
13635 case 35:
13636 // FDUP_ZI_D, FDUP_ZI_S, FMOVDi, FMOVHi, FMOVSi, FMOVv2f32_ns, FMOVv2f64_...
13637 printFPImmOperand(MI, 1, STI, O);
13638 return;
13639 break;
13640 case 36:
13641 // INDEX_II_B, INDEX_IR_B
13642 printSImm<8>(MI, 1, STI, O);
13643 O << ", ";
13644 break;
13645 case 37:
13646 // INDEX_II_H
13647 printSImm<16>(MI, 2, STI, O);
13648 return;
13649 break;
13650 case 38:
13651 // INSvi16lane, INSvi32lane, INSvi64lane, INSvi8lane
13652 printVRegOperand(MI, 3, STI, O);
13653 break;
13654 case 39:
13655 // LDADDAB, LDADDAH, LDADDALB, LDADDALH, LDADDALW, LDADDALX, LDADDAW, LDA...
13656 printOperand(MI, 0, STI, O);
13657 O << ", [";
13658 printOperand(MI, 2, STI, O);
13659 O << ']';
13660 return;
13661 break;
13662 case 40:
13663 // MOVID, MOVIv2d_ns
13664 printSIMDType10Operand(MI, 1, STI, O);
13665 return;
13666 break;
13667 case 41:
13668 // MOVIv16b_ns, MOVIv2i32, MOVIv2s_msl, MOVIv4i16, MOVIv4i32, MOVIv4s_msl...
13669 printImm(MI, 1, STI, O);
13670 break;
13671 case 42:
13672 // MRS
13673 printMRSSystemRegister(MI, 1, STI, O);
13674 return;
13675 break;
13676 case 43:
13677 // PMULLv1i64
13678 O << ".1d, ";
13679 printVRegOperand(MI, 2, STI, O);
13680 O << ".1d";
13681 return;
13682 break;
13683 case 44:
13684 // PMULLv2i64
13685 O << ".2d, ";
13686 printVRegOperand(MI, 2, STI, O);
13687 O << ".2d";
13688 return;
13689 break;
13690 case 45:
13691 // SQDECB_XPiWdI, SQDECD_XPiWdI, SQDECH_XPiWdI, SQDECW_XPiWdI, SQINCB_XPi...
13692 printGPR64as32(MI, 1, STI, O);
13693 O << ", ";
13694 printSVEPattern(MI, 2, STI, O);
13695 O << ", mul ";
13696 printOperand(MI, 3, STI, O);
13697 return;
13698 break;
13699 case 46:
13700 // ST1i16_POST, ST2i8_POST
13701 printPostIncOperand<2>(MI, 4, STI, O);
13702 return;
13703 break;
13704 case 47:
13705 // ST1i32_POST, ST2i16_POST, ST4i8_POST
13706 printPostIncOperand<4>(MI, 4, STI, O);
13707 return;
13708 break;
13709 case 48:
13710 // ST1i64_POST, ST2i32_POST, ST4i16_POST
13711 printPostIncOperand<8>(MI, 4, STI, O);
13712 return;
13713 break;
13714 case 49:
13715 // ST1i8_POST
13716 printPostIncOperand<1>(MI, 4, STI, O);
13717 return;
13718 break;
13719 case 50:
13720 // ST2i64_POST, ST4i32_POST
13721 printPostIncOperand<16>(MI, 4, STI, O);
13722 return;
13723 break;
13724 case 51:
13725 // ST3i16_POST
13726 printPostIncOperand<6>(MI, 4, STI, O);
13727 return;
13728 break;
13729 case 52:
13730 // ST3i32_POST
13731 printPostIncOperand<12>(MI, 4, STI, O);
13732 return;
13733 break;
13734 case 53:
13735 // ST3i64_POST
13736 printPostIncOperand<24>(MI, 4, STI, O);
13737 return;
13738 break;
13739 case 54:
13740 // ST3i8_POST
13741 printPostIncOperand<3>(MI, 4, STI, O);
13742 return;
13743 break;
13744 case 55:
13745 // ST4i64_POST
13746 printPostIncOperand<32>(MI, 4, STI, O);
13747 return;
13748 break;
13749 case 56:
13750 // ST64BV, ST64BV0
13751 printGPR64x8(MI, 1, STI, O);
13752 O << ", [";
13753 printOperand(MI, 2, STI, O);
13754 O << ']';
13755 return;
13756 break;
13757 case 57:
13758 // SYSxt
13759 printSysCROperand(MI, 1, STI, O);
13760 O << ", ";
13761 printSysCROperand(MI, 2, STI, O);
13762 O << ", ";
13763 printOperand(MI, 3, STI, O);
13764 O << ", ";
13765 printOperand(MI, 4, STI, O);
13766 return;
13767 break;
13768 case 58:
13769 // TBL_ZZZZ_D, TBL_ZZZ_D
13770 printTypedVectorList<0,'d'>(MI, 1, STI, O);
13771 O << ", ";
13772 printSVERegOp<'d'>(MI, 2, STI, O);
13773 return;
13774 break;
13775 case 59:
13776 // TBL_ZZZZ_S, TBL_ZZZ_S
13777 printTypedVectorList<0,'s'>(MI, 1, STI, O);
13778 O << ", ";
13779 printSVERegOp<'s'>(MI, 2, STI, O);
13780 return;
13781 break;
13782 case 60:
13783 // TBLv16i8Four, TBLv16i8One, TBLv16i8Three, TBLv16i8Two, TBLv8i8Four, TB...
13784 printTypedVectorList<16, 'b'>(MI, 1, STI, O);
13785 O << ", ";
13786 printVRegOperand(MI, 2, STI, O);
13787 break;
13788 case 61:
13789 // TBXv16i8Four, TBXv16i8One, TBXv16i8Three, TBXv16i8Two, TBXv8i8Four, TB...
13790 printTypedVectorList<16, 'b'>(MI, 2, STI, O);
13791 O << ", ";
13792 printVRegOperand(MI, 3, STI, O);
13793 break;
13794 }
13795
13796
13797 // Fragment 3 encoded into 7 bits for 99 unique commands.
13798 switch ((Bits >> 31) & 127) {
13799 default: llvm_unreachable("Invalid command number.");
13800 case 0:
13801 // ABS_ZPmZ_B, BRKA_PPmP, BRKB_PPmP, CDOT_ZZZI_S, CDOT_ZZZ_S, CLS_ZPmZ_B,...
13802 printSVERegOp<'b'>(MI, 3, STI, O);
13803 break;
13804 case 1:
13805 // ABS_ZPmZ_D, CLS_ZPmZ_D, CLZ_ZPmZ_D, CNOT_ZPmZ_D, CNT_ZPmZ_D, FABS_ZPmZ...
13806 printSVERegOp<'d'>(MI, 3, STI, O);
13807 return;
13808 break;
13809 case 2:
13810 // ABS_ZPmZ_S, ADDHNT_ZZZ_H, CLS_ZPmZ_S, CLZ_ZPmZ_S, CNOT_ZPmZ_S, CNT_ZPm...
13811 printSVERegOp<'s'>(MI, 3, STI, O);
13812 return;
13813 break;
13814 case 3:
13815 // ABSv16i8, ADDVv16i8v, AESDrr, AESErr, AESIMCrr, AESMCrr, CLSv16i8, CLZ...
13816 O << ".16b";
13817 return;
13818 break;
13819 case 4:
13820 // ABSv1i64, ADR, AESIMC_ZZ_B, AESMC_ZZ_B, AUTDA, AUTDB, AUTIA, AUTIB, BF...
13821 return;
13822 break;
13823 case 5:
13824 // ABSv2i32, CLSv2i32, CLZv2i32, FABSv2f32, FADDPv2i32p, FCVTASv2f32, FCV...
13825 O << ".2s";
13826 return;
13827 break;
13828 case 6:
13829 // ABSv2i64, ADDPv2i64p, FABSv2f64, FADDPv2i64p, FCVTASv2f64, FCVTAUv2f64...
13830 O << ".2d";
13831 return;
13832 break;
13833 case 7:
13834 // ABSv4i16, ADDVv4i16v, CLSv4i16, CLZv4i16, FABSv4f16, FCVTASv4f16, FCVT...
13835 O << ".4h";
13836 return;
13837 break;
13838 case 8:
13839 // ABSv4i32, ADDVv4i32v, BFCVTN, BFCVTN2, CLSv4i32, CLZv4i32, FABSv4f32, ...
13840 O << ".4s";
13841 return;
13842 break;
13843 case 9:
13844 // ABSv8i16, ADDVv8i16v, CLSv8i16, CLZv8i16, FABSv8f16, FCVTASv8f16, FCVT...
13845 O << ".8h";
13846 return;
13847 break;
13848 case 10:
13849 // ABSv8i8, ADDVv8i8v, CLSv8i8, CLZv8i8, CNTv8i8, NEGv8i8, NOTv8i8, RBITv...
13850 O << ".8b";
13851 return;
13852 break;
13853 case 11:
13854 // ADCLB_ZZZ_D, ADCLB_ZZZ_S, ADCLT_ZZZ_D, ADCLT_ZZZ_S, ADCSWr, ADCSXr, AD...
13855 O << ", ";
13856 break;
13857 case 12:
13858 // ADDHNB_ZZZ_H, RADDHNB_ZZZ_H, RSUBHNB_ZZZ_H, SUBHNB_ZZZ_H
13859 printSVERegOp<'s'>(MI, 2, STI, O);
13860 return;
13861 break;
13862 case 13:
13863 // ADDHNv2i64_v2i32, ADDHNv2i64_v4i32, ADDPv2i64, ADDv2i64, CMEQv2i64, CM...
13864 O << ".2d, ";
13865 break;
13866 case 14:
13867 // ADDHNv4i32_v4i16, ADDHNv4i32_v8i16, ADDPv4i32, ADDv4i32, CMEQv4i32, CM...
13868 O << ".4s, ";
13869 break;
13870 case 15:
13871 // ADDHNv8i16_v16i8, ADDHNv8i16_v8i8, ADDPv8i16, ADDv8i16, BF16DOTlanev8b...
13872 O << ".8h, ";
13873 break;
13874 case 16:
13875 // ADDP_ZPmZ_B, ADDP_ZPmZ_D, ADDP_ZPmZ_S, ADD_ZPmZ_B, ADD_ZPmZ_D, ADD_ZPm...
13876 O << "/m, ";
13877 break;
13878 case 17:
13879 // ADDP_ZPmZ_H, ADD_ZPmZ_H, ADD_ZZZ_H, AND_ZPmZ_H, ASRD_ZPmI_H, ASRR_ZPmZ...
13880 printSVERegOp<'h'>(MI, 2, STI, O);
13881 break;
13882 case 18:
13883 // ADDPv16i8, ADDv16i8, ANDv16i8, BCAX, BICv16i8, BIFv16i8, BITv16i8, BSL...
13884 O << ".16b, ";
13885 break;
13886 case 19:
13887 // ADDPv2i32, ADDv2i32, CMEQv2i32, CMGEv2i32, CMGTv2i32, CMHIv2i32, CMHSv...
13888 O << ".2s, ";
13889 break;
13890 case 20:
13891 // ADDPv4i16, ADDv4i16, BF16DOTlanev4bf16, BFDOTv4bf16, CMEQv4i16, CMGEv4...
13892 O << ".4h, ";
13893 break;
13894 case 21:
13895 // ADDPv8i8, ADDv8i8, ANDv8i8, BICv8i8, BIFv8i8, BITv8i8, BSLv8i8, CMEQv8...
13896 O << ".8b, ";
13897 break;
13898 case 22:
13899 // ADD_ZI_H, SQADD_ZI_H, SQSUB_ZI_H, SUBR_ZI_H, SUB_ZI_H, UQADD_ZI_H, UQS...
13900 printImm8OptLsl<uint16_t>(MI, 2, STI, O);
13901 return;
13902 break;
13903 case 23:
13904 // ANDS_PPzPP, AND_PPzPP, BICS_PPzPP, BIC_PPzPP, BRKAS_PPzP, BRKA_PPzP, B...
13905 O << "/z, ";
13906 break;
13907 case 24:
13908 // ASR_WIDE_ZZZ_H, LSL_WIDE_ZZZ_H, LSR_WIDE_ZZZ_H
13909 printSVERegOp<'d'>(MI, 2, STI, O);
13910 return;
13911 break;
13912 case 25:
13913 // ASR_ZZI_H, INDEX_IR_B, INDEX_RR_H, LSL_ZZI_H, LSR_ZZI_H, MUL_ZI_H, RSH...
13914 printOperand(MI, 2, STI, O);
13915 return;
13916 break;
13917 case 26:
13918 // CASAB, CASAH, CASALB, CASALH, CASALW, CASALX, CASAW, CASAX, CASB, CASH...
13919 O << ", [";
13920 break;
13921 case 27:
13922 // CMEQv16i8rz, CMGEv16i8rz, CMGTv16i8rz, CMLEv16i8rz, CMLTv16i8rz
13923 O << ".16b, #0";
13924 return;
13925 break;
13926 case 28:
13927 // CMEQv1i64rz, CMGEv1i64rz, CMGTv1i64rz, CMLEv1i64rz, CMLTv1i64rz
13928 O << ", #0";
13929 return;
13930 break;
13931 case 29:
13932 // CMEQv2i32rz, CMGEv2i32rz, CMGTv2i32rz, CMLEv2i32rz, CMLTv2i32rz
13933 O << ".2s, #0";
13934 return;
13935 break;
13936 case 30:
13937 // CMEQv2i64rz, CMGEv2i64rz, CMGTv2i64rz, CMLEv2i64rz, CMLTv2i64rz
13938 O << ".2d, #0";
13939 return;
13940 break;
13941 case 31:
13942 // CMEQv4i16rz, CMGEv4i16rz, CMGTv4i16rz, CMLEv4i16rz, CMLTv4i16rz
13943 O << ".4h, #0";
13944 return;
13945 break;
13946 case 32:
13947 // CMEQv4i32rz, CMGEv4i32rz, CMGTv4i32rz, CMLEv4i32rz, CMLTv4i32rz
13948 O << ".4s, #0";
13949 return;
13950 break;
13951 case 33:
13952 // CMEQv8i16rz, CMGEv8i16rz, CMGTv8i16rz, CMLEv8i16rz, CMLTv8i16rz
13953 O << ".8h, #0";
13954 return;
13955 break;
13956 case 34:
13957 // CMEQv8i8rz, CMGEv8i8rz, CMGTv8i8rz, CMLEv8i8rz, CMLTv8i8rz
13958 O << ".8b, #0";
13959 return;
13960 break;
13961 case 35:
13962 // CMLA_ZZZI_H, CMLA_ZZZ_H, EORBT_ZZZ_H, EORTB_ZZZ_H, FCMLA_ZPmZZ_H, FCML...
13963 printSVERegOp<'h'>(MI, 3, STI, O);
13964 break;
13965 case 36:
13966 // CNTB_XPiI, CNTD_XPiI, CNTH_XPiI, CNTW_XPiI
13967 O << ", mul ";
13968 printOperand(MI, 2, STI, O);
13969 return;
13970 break;
13971 case 37:
13972 // CPY_ZPmI_B
13973 printImm8OptLsl<int8_t>(MI, 3, STI, O);
13974 return;
13975 break;
13976 case 38:
13977 // CPY_ZPmI_D
13978 printImm8OptLsl<int64_t>(MI, 3, STI, O);
13979 return;
13980 break;
13981 case 39:
13982 // CPY_ZPmI_S
13983 printImm8OptLsl<int32_t>(MI, 3, STI, O);
13984 return;
13985 break;
13986 case 40:
13987 // CPY_ZPmR_B, CPY_ZPmR_D, CPY_ZPmR_S, CPY_ZPmV_B, CPY_ZPmV_D, CPY_ZPmV_S...
13988 printOperand(MI, 3, STI, O);
13989 break;
13990 case 41:
13991 // CPY_ZPzI_H
13992 printImm8OptLsl<int16_t>(MI, 2, STI, O);
13993 return;
13994 break;
13995 case 42:
13996 // CPYi16, DUPv4i16lane, DUPv8i16lane, INSvi16lane, SMOVvi16to32, SMOVvi1...
13997 O << ".h";
13998 break;
13999 case 43:
14000 // CPYi32, DUPv2i32lane, DUPv4i32lane, INSvi32lane, SMOVvi32to64, UMOVvi3...
14001 O << ".s";
14002 break;
14003 case 44:
14004 // CPYi64, DUPv2i64lane, FMOVDXHighr, INSvi64lane, UMOVvi64
14005 O << ".d";
14006 break;
14007 case 45:
14008 // CPYi8, DUPv16i8lane, DUPv8i8lane, INSvi8lane, SMOVvi8to32, SMOVvi8to64...
14009 O << ".b";
14010 break;
14011 case 46:
14012 // DUP_ZZI_B, DUP_ZZI_D, DUP_ZZI_S
14013 printVectorIndex(MI, 2, STI, O);
14014 return;
14015 break;
14016 case 47:
14017 // EXT_ZZI_B, UMAX_ZI_H, UMIN_ZI_H
14018 printImm(MI, 2, STI, O);
14019 return;
14020 break;
14021 case 48:
14022 // FADDPv2i16p, FMAXNMPv2i16p, FMAXPv2i16p, FMINNMPv2i16p, FMINPv2i16p
14023 O << ".2h";
14024 return;
14025 break;
14026 case 49:
14027 // FCMEQv1i16rz, FCMEQv1i32rz, FCMEQv1i64rz, FCMGEv1i16rz, FCMGEv1i32rz, ...
14028 O << ", #0.0";
14029 return;
14030 break;
14031 case 50:
14032 // FCMEQv2i32rz, FCMGEv2i32rz, FCMGTv2i32rz, FCMLEv2i32rz, FCMLTv2i32rz
14033 O << ".2s, #0.0";
14034 return;
14035 break;
14036 case 51:
14037 // FCMEQv2i64rz, FCMGEv2i64rz, FCMGTv2i64rz, FCMLEv2i64rz, FCMLTv2i64rz
14038 O << ".2d, #0.0";
14039 return;
14040 break;
14041 case 52:
14042 // FCMEQv4i16rz, FCMGEv4i16rz, FCMGTv4i16rz, FCMLEv4i16rz, FCMLTv4i16rz
14043 O << ".4h, #0.0";
14044 return;
14045 break;
14046 case 53:
14047 // FCMEQv4i32rz, FCMGEv4i32rz, FCMGTv4i32rz, FCMLEv4i32rz, FCMLTv4i32rz
14048 O << ".4s, #0.0";
14049 return;
14050 break;
14051 case 54:
14052 // FCMEQv8i16rz, FCMGEv8i16rz, FCMGTv8i16rz, FCMLEv8i16rz, FCMLTv8i16rz
14053 O << ".8h, #0.0";
14054 return;
14055 break;
14056 case 55:
14057 // FCPY_ZPmI_D, FCPY_ZPmI_S
14058 printFPImmOperand(MI, 3, STI, O);
14059 return;
14060 break;
14061 case 56:
14062 // FMLAL2lanev4f16, FMLAL2v4f16, FMLALlanev4f16, FMLALv4f16, FMLSL2lanev4...
14063 O << ".2h, ";
14064 printVRegOperand(MI, 3, STI, O);
14065 break;
14066 case 57:
14067 // INDEX_II_B
14068 printSImm<8>(MI, 2, STI, O);
14069 return;
14070 break;
14071 case 58:
14072 // INDEX_RI_H
14073 printSImm<16>(MI, 2, STI, O);
14074 return;
14075 break;
14076 case 59:
14077 // LDAPRB, LDAPRH, LDAPRW, LDAPRX, LDARB, LDARH, LDARW, LDARX, LDAXRB, LD...
14078 O << ']';
14079 return;
14080 break;
14081 case 60:
14082 // LDRBBpost, LDRBpost, LDRDpost, LDRHHpost, LDRHpost, LDRQpost, LDRSBWpo...
14083 O << "], ";
14084 break;
14085 case 61:
14086 // MOVIv2i32, MOVIv2s_msl, MOVIv4i16, MOVIv4i32, MOVIv4s_msl, MOVIv8i16, ...
14087 printShifter(MI, 2, STI, O);
14088 return;
14089 break;
14090 case 62:
14091 // PMULLB_ZZZ_H, PMULLT_ZZZ_H, SABDLB_ZZZ_H, SABDLT_ZZZ_H, SADDLBT_ZZZ_H,...
14092 printSVERegOp<'b'>(MI, 2, STI, O);
14093 return;
14094 break;
14095 case 63:
14096 // PRFB_D_SCALED
14097 printRegWithShiftExtend<false, 8, 'x', 'd'>(MI, 3, STI, O);
14098 O << ']';
14099 return;
14100 break;
14101 case 64:
14102 // PRFB_D_SXTW_SCALED
14103 printRegWithShiftExtend<true, 8, 'w', 'd'>(MI, 3, STI, O);
14104 O << ']';
14105 return;
14106 break;
14107 case 65:
14108 // PRFB_D_UXTW_SCALED
14109 printRegWithShiftExtend<false, 8, 'w', 'd'>(MI, 3, STI, O);
14110 O << ']';
14111 return;
14112 break;
14113 case 66:
14114 // PRFB_PRR
14115 printRegWithShiftExtend<false, 8, 'x', 0>(MI, 3, STI, O);
14116 O << ']';
14117 return;
14118 break;
14119 case 67:
14120 // PRFB_S_SXTW_SCALED
14121 printRegWithShiftExtend<true, 8, 'w', 's'>(MI, 3, STI, O);
14122 O << ']';
14123 return;
14124 break;
14125 case 68:
14126 // PRFB_S_UXTW_SCALED
14127 printRegWithShiftExtend<false, 8, 'w', 's'>(MI, 3, STI, O);
14128 O << ']';
14129 return;
14130 break;
14131 case 69:
14132 // PRFD_D_PZI, PRFD_S_PZI
14133 printImmScale<8>(MI, 3, STI, O);
14134 O << ']';
14135 return;
14136 break;
14137 case 70:
14138 // PRFD_D_SCALED
14139 printRegWithShiftExtend<false, 64, 'x', 'd'>(MI, 3, STI, O);
14140 O << ']';
14141 return;
14142 break;
14143 case 71:
14144 // PRFD_D_SXTW_SCALED
14145 printRegWithShiftExtend<true, 64, 'w', 'd'>(MI, 3, STI, O);
14146 O << ']';
14147 return;
14148 break;
14149 case 72:
14150 // PRFD_D_UXTW_SCALED
14151 printRegWithShiftExtend<false, 64, 'w', 'd'>(MI, 3, STI, O);
14152 O << ']';
14153 return;
14154 break;
14155 case 73:
14156 // PRFD_PRR
14157 printRegWithShiftExtend<false, 64, 'x', 0>(MI, 3, STI, O);
14158 O << ']';
14159 return;
14160 break;
14161 case 74:
14162 // PRFD_S_SXTW_SCALED
14163 printRegWithShiftExtend<true, 64, 'w', 's'>(MI, 3, STI, O);
14164 O << ']';
14165 return;
14166 break;
14167 case 75:
14168 // PRFD_S_UXTW_SCALED
14169 printRegWithShiftExtend<false, 64, 'w', 's'>(MI, 3, STI, O);
14170 O << ']';
14171 return;
14172 break;
14173 case 76:
14174 // PRFH_D_PZI, PRFH_S_PZI
14175 printImmScale<2>(MI, 3, STI, O);
14176 O << ']';
14177 return;
14178 break;
14179 case 77:
14180 // PRFH_D_SCALED
14181 printRegWithShiftExtend<false, 16, 'x', 'd'>(MI, 3, STI, O);
14182 O << ']';
14183 return;
14184 break;
14185 case 78:
14186 // PRFH_D_SXTW_SCALED
14187 printRegWithShiftExtend<true, 16, 'w', 'd'>(MI, 3, STI, O);
14188 O << ']';
14189 return;
14190 break;
14191 case 79:
14192 // PRFH_D_UXTW_SCALED
14193 printRegWithShiftExtend<false, 16, 'w', 'd'>(MI, 3, STI, O);
14194 O << ']';
14195 return;
14196 break;
14197 case 80:
14198 // PRFH_PRR
14199 printRegWithShiftExtend<false, 16, 'x', 0>(MI, 3, STI, O);
14200 O << ']';
14201 return;
14202 break;
14203 case 81:
14204 // PRFH_S_SXTW_SCALED
14205 printRegWithShiftExtend<true, 16, 'w', 's'>(MI, 3, STI, O);
14206 O << ']';
14207 return;
14208 break;
14209 case 82:
14210 // PRFH_S_UXTW_SCALED
14211 printRegWithShiftExtend<false, 16, 'w', 's'>(MI, 3, STI, O);
14212 O << ']';
14213 return;
14214 break;
14215 case 83:
14216 // PRFS_PRR
14217 printRegWithShiftExtend<false, 32, 'x', 0>(MI, 3, STI, O);
14218 O << ']';
14219 return;
14220 break;
14221 case 84:
14222 // PRFW_D_PZI, PRFW_S_PZI
14223 printImmScale<4>(MI, 3, STI, O);
14224 O << ']';
14225 return;
14226 break;
14227 case 85:
14228 // PRFW_D_SCALED
14229 printRegWithShiftExtend<false, 32, 'x', 'd'>(MI, 3, STI, O);
14230 O << ']';
14231 return;
14232 break;
14233 case 86:
14234 // PRFW_D_SXTW_SCALED
14235 printRegWithShiftExtend<true, 32, 'w', 'd'>(MI, 3, STI, O);
14236 O << ']';
14237 return;
14238 break;
14239 case 87:
14240 // PRFW_D_UXTW_SCALED
14241 printRegWithShiftExtend<false, 32, 'w', 'd'>(MI, 3, STI, O);
14242 O << ']';
14243 return;
14244 break;
14245 case 88:
14246 // PRFW_S_SXTW_SCALED
14247 printRegWithShiftExtend<true, 32, 'w', 's'>(MI, 3, STI, O);
14248 O << ']';
14249 return;
14250 break;
14251 case 89:
14252 // PRFW_S_UXTW_SCALED
14253 printRegWithShiftExtend<false, 32, 'w', 's'>(MI, 3, STI, O);
14254 O << ']';
14255 return;
14256 break;
14257 case 90:
14258 // RDFFRS_PPz, RDFFR_PPz_REAL
14259 O << "/z";
14260 return;
14261 break;
14262 case 91:
14263 // SHLLv16i8
14264 O << ".16b, #8";
14265 return;
14266 break;
14267 case 92:
14268 // SHLLv2i32
14269 O << ".2s, #32";
14270 return;
14271 break;
14272 case 93:
14273 // SHLLv4i16
14274 O << ".4h, #16";
14275 return;
14276 break;
14277 case 94:
14278 // SHLLv4i32
14279 O << ".4s, #32";
14280 return;
14281 break;
14282 case 95:
14283 // SHLLv8i16
14284 O << ".8h, #16";
14285 return;
14286 break;
14287 case 96:
14288 // SHLLv8i8
14289 O << ".8b, #8";
14290 return;
14291 break;
14292 case 97:
14293 // SPLICE_ZPZZ_H
14294 printTypedVectorList<0,'h'>(MI, 2, STI, O);
14295 return;
14296 break;
14297 case 98:
14298 // TRN1_ZZZ_Q, TRN2_ZZZ_Q, UZP1_ZZZ_Q, UZP2_ZZZ_Q, ZIP1_ZZZ_Q, ZIP2_ZZZ_Q
14299 printSVERegOp<'q'>(MI, 2, STI, O);
14300 return;
14301 break;
14302 }
14303
14304
14305 // Fragment 4 encoded into 7 bits for 92 unique commands.
14306 switch ((Bits >> 38) & 127) {
14307 default: llvm_unreachable("Invalid command number.");
14308 case 0:
14309 // ABS_ZPmZ_B, ADD_ZZZ_H, BDEP_ZZZ_H, BEXT_ZZZ_H, BGRP_ZZZ_H, BRKA_PPmP, ...
14310 return;
14311 break;
14312 case 1:
14313 // ADCLB_ZZZ_D, ADCLT_ZZZ_D, ADDHNT_ZZZ_S, CMLA_ZZZ_D, EORBT_ZZZ_D, EORTB...
14314 printSVERegOp<'d'>(MI, 3, STI, O);
14315 break;
14316 case 2:
14317 // ADCLB_ZZZ_S, ADCLT_ZZZ_S, CMLA_ZZZI_S, CMLA_ZZZ_S, EORBT_ZZZ_S, EORTB_...
14318 printSVERegOp<'s'>(MI, 3, STI, O);
14319 break;
14320 case 3:
14321 // ADCSWr, ADCSXr, ADCWr, ADCXr, ADDPL_XXI, ADDSXrx64, ADDVL_XXI, ADDXrx6...
14322 printOperand(MI, 2, STI, O);
14323 break;
14324 case 4:
14325 // ADDG, ST2GOffset, STGOffset, STZ2GOffset, STZGOffset, SUBG
14326 printImmScale<16>(MI, 2, STI, O);
14327 break;
14328 case 5:
14329 // ADDHNB_ZZZ_B, CNTP_XPP_H, LASTA_RPZ_H, LASTA_VPZ_H, LASTB_RPZ_H, LASTB...
14330 printSVERegOp<'h'>(MI, 2, STI, O);
14331 break;
14332 case 6:
14333 // ADDHNB_ZZZ_S, ADDP_ZPmZ_D, ADD_ZPmZ_D, ADD_ZZZ_D, AND_ZPmZ_D, AND_ZZZ,...
14334 printSVERegOp<'d'>(MI, 2, STI, O);
14335 break;
14336 case 7:
14337 // ADDHNT_ZZZ_B, BFDOT_ZZI, BFDOT_ZZZ, BFMMLA_B_ZZI, BFMMLA_B_ZZZ, BFMMLA...
14338 printSVERegOp<'h'>(MI, 3, STI, O);
14339 break;
14340 case 8:
14341 // ADDHNv2i64_v2i32, ADDHNv4i32_v4i16, ADDHNv8i16_v8i8, ADDPv16i8, ADDPv2...
14342 printVRegOperand(MI, 2, STI, O);
14343 break;
14344 case 9:
14345 // ADDHNv2i64_v4i32, ADDHNv4i32_v8i16, ADDHNv8i16_v16i8, BF16DOTlanev4bf1...
14346 printVRegOperand(MI, 3, STI, O);
14347 break;
14348 case 10:
14349 // ADDP_ZPmZ_B, ADD_ZPmZ_B, ADD_ZZZ_B, AESD_ZZZ_B, AESE_ZZZ_B, ANDS_PPzPP...
14350 printSVERegOp<'b'>(MI, 2, STI, O);
14351 break;
14352 case 11:
14353 // ADDP_ZPmZ_H, ADD_ZPmZ_H, AND_ZPmZ_H, ASRD_ZPmI_H, ASRR_ZPmZ_H, ASR_WID...
14354 O << ", ";
14355 break;
14356 case 12:
14357 // ADDP_ZPmZ_S, ADD_ZPmZ_S, ADD_ZZZ_S, AND_ZPmZ_S, ASRD_ZPmI_S, ASRR_ZPmZ...
14358 printSVERegOp<'s'>(MI, 2, STI, O);
14359 break;
14360 case 13:
14361 // ADDSWri, ADDSXri, ADDWri, ADDXri, SUBSWri, SUBSXri, SUBWri, SUBXri
14362 printAddSubImm(MI, 2, STI, O);
14363 return;
14364 break;
14365 case 14:
14366 // ADDSWrs, ADDSXrs, ADDWrs, ADDXrs, ANDSWrs, ANDSXrs, ANDWrs, ANDXrs, BI...
14367 printShiftedRegister(MI, 2, STI, O);
14368 return;
14369 break;
14370 case 15:
14371 // ADDSWrx, ADDSXrx, ADDWrx, ADDXrx, SUBSWrx, SUBSXrx, SUBWrx, SUBXrx
14372 printExtendedRegister(MI, 2, STI, O);
14373 return;
14374 break;
14375 case 16:
14376 // ADD_ZI_B, SQADD_ZI_B, SQSUB_ZI_B, SUBR_ZI_B, SUB_ZI_B, UQADD_ZI_B, UQS...
14377 printImm8OptLsl<uint8_t>(MI, 2, STI, O);
14378 return;
14379 break;
14380 case 17:
14381 // ADD_ZI_D, SQADD_ZI_D, SQSUB_ZI_D, SUBR_ZI_D, SUB_ZI_D, UQADD_ZI_D, UQS...
14382 printImm8OptLsl<uint64_t>(MI, 2, STI, O);
14383 return;
14384 break;
14385 case 18:
14386 // ADD_ZI_S, SQADD_ZI_S, SQSUB_ZI_S, SUBR_ZI_S, SUB_ZI_S, UQADD_ZI_S, UQS...
14387 printImm8OptLsl<uint32_t>(MI, 2, STI, O);
14388 return;
14389 break;
14390 case 19:
14391 // ADR_LSL_ZZZ_D_0
14392 printRegWithShiftExtend<false, 8, 'x', 'd'>(MI, 2, STI, O);
14393 O << ']';
14394 return;
14395 break;
14396 case 20:
14397 // ADR_LSL_ZZZ_D_1
14398 printRegWithShiftExtend<false, 16, 'x', 'd'>(MI, 2, STI, O);
14399 O << ']';
14400 return;
14401 break;
14402 case 21:
14403 // ADR_LSL_ZZZ_D_2
14404 printRegWithShiftExtend<false, 32, 'x', 'd'>(MI, 2, STI, O);
14405 O << ']';
14406 return;
14407 break;
14408 case 22:
14409 // ADR_LSL_ZZZ_D_3
14410 printRegWithShiftExtend<false, 64, 'x', 'd'>(MI, 2, STI, O);
14411 O << ']';
14412 return;
14413 break;
14414 case 23:
14415 // ADR_LSL_ZZZ_S_0
14416 printRegWithShiftExtend<false, 8, 'x', 's'>(MI, 2, STI, O);
14417 O << ']';
14418 return;
14419 break;
14420 case 24:
14421 // ADR_LSL_ZZZ_S_1
14422 printRegWithShiftExtend<false, 16, 'x', 's'>(MI, 2, STI, O);
14423 O << ']';
14424 return;
14425 break;
14426 case 25:
14427 // ADR_LSL_ZZZ_S_2
14428 printRegWithShiftExtend<false, 32, 'x', 's'>(MI, 2, STI, O);
14429 O << ']';
14430 return;
14431 break;
14432 case 26:
14433 // ADR_LSL_ZZZ_S_3
14434 printRegWithShiftExtend<false, 64, 'x', 's'>(MI, 2, STI, O);
14435 O << ']';
14436 return;
14437 break;
14438 case 27:
14439 // ADR_SXTW_ZZZ_D_0
14440 printRegWithShiftExtend<true, 8, 'w', 'd'>(MI, 2, STI, O);
14441 O << ']';
14442 return;
14443 break;
14444 case 28:
14445 // ADR_SXTW_ZZZ_D_1
14446 printRegWithShiftExtend<true, 16, 'w', 'd'>(MI, 2, STI, O);
14447 O << ']';
14448 return;
14449 break;
14450 case 29:
14451 // ADR_SXTW_ZZZ_D_2
14452 printRegWithShiftExtend<true, 32, 'w', 'd'>(MI, 2, STI, O);
14453 O << ']';
14454 return;
14455 break;
14456 case 30:
14457 // ADR_SXTW_ZZZ_D_3
14458 printRegWithShiftExtend<true, 64, 'w', 'd'>(MI, 2, STI, O);
14459 O << ']';
14460 return;
14461 break;
14462 case 31:
14463 // ADR_UXTW_ZZZ_D_0
14464 printRegWithShiftExtend<false, 8, 'w', 'd'>(MI, 2, STI, O);
14465 O << ']';
14466 return;
14467 break;
14468 case 32:
14469 // ADR_UXTW_ZZZ_D_1
14470 printRegWithShiftExtend<false, 16, 'w', 'd'>(MI, 2, STI, O);
14471 O << ']';
14472 return;
14473 break;
14474 case 33:
14475 // ADR_UXTW_ZZZ_D_2
14476 printRegWithShiftExtend<false, 32, 'w', 'd'>(MI, 2, STI, O);
14477 O << ']';
14478 return;
14479 break;
14480 case 34:
14481 // ADR_UXTW_ZZZ_D_3
14482 printRegWithShiftExtend<false, 64, 'w', 'd'>(MI, 2, STI, O);
14483 O << ']';
14484 return;
14485 break;
14486 case 35:
14487 // ANDSWri, ANDWri, EORWri, ORRWri
14488 printLogicalImm<int32_t>(MI, 2, STI, O);
14489 return;
14490 break;
14491 case 36:
14492 // ANDSXri, ANDXri, AND_ZI, EORXri, EOR_ZI, ORRXri, ORR_ZI
14493 printLogicalImm<int64_t>(MI, 2, STI, O);
14494 return;
14495 break;
14496 case 37:
14497 // BFMWri, BFMXri, CASAB, CASAH, CASALB, CASALH, CASALW, CASALX, CASAW, C...
14498 printOperand(MI, 3, STI, O);
14499 break;
14500 case 38:
14501 // CDOT_ZZZI_S, CMLA_ZZZI_H, FCMLA_ZZZI_H, FMLA_ZZZI_H, FMLS_ZZZI_H, INSv...
14502 printVectorIndex(MI, 4, STI, O);
14503 break;
14504 case 39:
14505 // CPY_ZPzI_B
14506 printImm8OptLsl<int8_t>(MI, 2, STI, O);
14507 return;
14508 break;
14509 case 40:
14510 // CPY_ZPzI_D
14511 printImm8OptLsl<int64_t>(MI, 2, STI, O);
14512 return;
14513 break;
14514 case 41:
14515 // CPY_ZPzI_S
14516 printImm8OptLsl<int32_t>(MI, 2, STI, O);
14517 return;
14518 break;
14519 case 42:
14520 // CPYi16, CPYi32, CPYi64, CPYi8, DUPv16i8lane, DUPv2i32lane, DUPv2i64lan...
14521 printVectorIndex(MI, 2, STI, O);
14522 return;
14523 break;
14524 case 43:
14525 // FCMEQ_PPzZ0_H, FCMGE_PPzZ0_H, FCMGT_PPzZ0_H, FCMLE_PPzZ0_H, FCMLT_PPzZ...
14526 O << ", #0.0";
14527 return;
14528 break;
14529 case 44:
14530 // FMLAL2lanev4f16, FMLALlanev4f16, FMLSL2lanev4f16, FMLSLlanev4f16
14531 O << ".h";
14532 printVectorIndex(MI, 4, STI, O);
14533 return;
14534 break;
14535 case 45:
14536 // FMLAL2v4f16, FMLALv4f16, FMLSL2v4f16, FMLSLv4f16
14537 O << ".2h";
14538 return;
14539 break;
14540 case 46:
14541 // FMUL_ZZZI_H, MUL_ZZZI_H, SQDMULH_ZZZI_H, SQRDMULH_ZZZI_H
14542 printVectorIndex(MI, 3, STI, O);
14543 return;
14544 break;
14545 case 47:
14546 // GLD1B_D_REAL, GLD1D_REAL, GLD1H_D_REAL, GLD1SB_D_REAL, GLD1SH_D_REAL, ...
14547 printRegWithShiftExtend<false, 8, 'x', 'd'>(MI, 3, STI, O);
14548 O << ']';
14549 return;
14550 break;
14551 case 48:
14552 // GLD1B_D_SXTW_REAL, GLD1D_SXTW_REAL, GLD1H_D_SXTW_REAL, GLD1SB_D_SXTW_R...
14553 printRegWithShiftExtend<true, 8, 'w', 'd'>(MI, 3, STI, O);
14554 O << ']';
14555 return;
14556 break;
14557 case 49:
14558 // GLD1B_D_UXTW_REAL, GLD1D_UXTW_REAL, GLD1H_D_UXTW_REAL, GLD1SB_D_UXTW_R...
14559 printRegWithShiftExtend<false, 8, 'w', 'd'>(MI, 3, STI, O);
14560 O << ']';
14561 return;
14562 break;
14563 case 50:
14564 // GLD1B_S_SXTW_REAL, GLD1H_S_SXTW_REAL, GLD1SB_S_SXTW_REAL, GLD1SH_S_SXT...
14565 printRegWithShiftExtend<true, 8, 'w', 's'>(MI, 3, STI, O);
14566 O << ']';
14567 return;
14568 break;
14569 case 51:
14570 // GLD1B_S_UXTW_REAL, GLD1H_S_UXTW_REAL, GLD1SB_S_UXTW_REAL, GLD1SH_S_UXT...
14571 printRegWithShiftExtend<false, 8, 'w', 's'>(MI, 3, STI, O);
14572 O << ']';
14573 return;
14574 break;
14575 case 52:
14576 // GLD1D_IMM_REAL, GLDFF1D_IMM_REAL, LD1RD_IMM, LDRAAwriteback, LDRABwrit...
14577 printImmScale<8>(MI, 3, STI, O);
14578 break;
14579 case 53:
14580 // GLD1D_SCALED_REAL, GLDFF1D_SCALED_REAL, SST1D_SCALED_SCALED_REAL
14581 printRegWithShiftExtend<false, 64, 'x', 'd'>(MI, 3, STI, O);
14582 O << ']';
14583 return;
14584 break;
14585 case 54:
14586 // GLD1D_SXTW_SCALED_REAL, GLDFF1D_SXTW_SCALED_REAL, SST1D_SXTW_SCALED
14587 printRegWithShiftExtend<true, 64, 'w', 'd'>(MI, 3, STI, O);
14588 O << ']';
14589 return;
14590 break;
14591 case 55:
14592 // GLD1D_UXTW_SCALED_REAL, GLDFF1D_UXTW_SCALED_REAL, SST1D_UXTW_SCALED
14593 printRegWithShiftExtend<false, 64, 'w', 'd'>(MI, 3, STI, O);
14594 O << ']';
14595 return;
14596 break;
14597 case 56:
14598 // GLD1H_D_IMM_REAL, GLD1H_S_IMM_REAL, GLD1SH_D_IMM_REAL, GLD1SH_S_IMM_RE...
14599 printImmScale<2>(MI, 3, STI, O);
14600 break;
14601 case 57:
14602 // GLD1H_D_SCALED_REAL, GLD1SH_D_SCALED_REAL, GLDFF1H_D_SCALED_REAL, GLDF...
14603 printRegWithShiftExtend<false, 16, 'x', 'd'>(MI, 3, STI, O);
14604 O << ']';
14605 return;
14606 break;
14607 case 58:
14608 // GLD1H_D_SXTW_SCALED_REAL, GLD1SH_D_SXTW_SCALED_REAL, GLDFF1H_D_SXTW_SC...
14609 printRegWithShiftExtend<true, 16, 'w', 'd'>(MI, 3, STI, O);
14610 O << ']';
14611 return;
14612 break;
14613 case 59:
14614 // GLD1H_D_UXTW_SCALED_REAL, GLD1SH_D_UXTW_SCALED_REAL, GLDFF1H_D_UXTW_SC...
14615 printRegWithShiftExtend<false, 16, 'w', 'd'>(MI, 3, STI, O);
14616 O << ']';
14617 return;
14618 break;
14619 case 60:
14620 // GLD1H_S_SXTW_SCALED_REAL, GLD1SH_S_SXTW_SCALED_REAL, GLDFF1H_S_SXTW_SC...
14621 printRegWithShiftExtend<true, 16, 'w', 's'>(MI, 3, STI, O);
14622 O << ']';
14623 return;
14624 break;
14625 case 61:
14626 // GLD1H_S_UXTW_SCALED_REAL, GLD1SH_S_UXTW_SCALED_REAL, GLDFF1H_S_UXTW_SC...
14627 printRegWithShiftExtend<false, 16, 'w', 's'>(MI, 3, STI, O);
14628 O << ']';
14629 return;
14630 break;
14631 case 62:
14632 // GLD1SW_D_IMM_REAL, GLD1W_D_IMM_REAL, GLD1W_IMM_REAL, GLDFF1SW_D_IMM_RE...
14633 printImmScale<4>(MI, 3, STI, O);
14634 break;
14635 case 63:
14636 // GLD1SW_D_SCALED_REAL, GLD1W_D_SCALED_REAL, GLDFF1SW_D_SCALED_REAL, GLD...
14637 printRegWithShiftExtend<false, 32, 'x', 'd'>(MI, 3, STI, O);
14638 O << ']';
14639 return;
14640 break;
14641 case 64:
14642 // GLD1SW_D_SXTW_SCALED_REAL, GLD1W_D_SXTW_SCALED_REAL, GLDFF1SW_D_SXTW_S...
14643 printRegWithShiftExtend<true, 32, 'w', 'd'>(MI, 3, STI, O);
14644 O << ']';
14645 return;
14646 break;
14647 case 65:
14648 // GLD1SW_D_UXTW_SCALED_REAL, GLD1W_D_UXTW_SCALED_REAL, GLDFF1SW_D_UXTW_S...
14649 printRegWithShiftExtend<false, 32, 'w', 'd'>(MI, 3, STI, O);
14650 O << ']';
14651 return;
14652 break;
14653 case 66:
14654 // GLD1W_SXTW_SCALED_REAL, GLDFF1W_SXTW_SCALED_REAL, SST1W_SXTW_SCALED
14655 printRegWithShiftExtend<true, 32, 'w', 's'>(MI, 3, STI, O);
14656 O << ']';
14657 return;
14658 break;
14659 case 67:
14660 // GLD1W_UXTW_SCALED_REAL, GLDFF1W_UXTW_SCALED_REAL, SST1W_UXTW_SCALED
14661 printRegWithShiftExtend<false, 32, 'w', 's'>(MI, 3, STI, O);
14662 O << ']';
14663 return;
14664 break;
14665 case 68:
14666 // INDEX_RI_B
14667 printSImm<8>(MI, 2, STI, O);
14668 return;
14669 break;
14670 case 69:
14671 // LD1B, LD1B_D, LD1B_H, LD1B_S, LD1RO_B, LD1RQ_B, LD1SB_D, LD1SB_H, LD1S...
14672 printRegWithShiftExtend<false, 8, 'x', 0>(MI, 3, STI, O);
14673 O << ']';
14674 return;
14675 break;
14676 case 70:
14677 // LD1D, LD1RO_D, LD1RQ_D, LD2D, LD3D, LD4D, LDFF1D_REAL, LDNT1D_ZRR, ST1...
14678 printRegWithShiftExtend<false, 64, 'x', 0>(MI, 3, STI, O);
14679 O << ']';
14680 return;
14681 break;
14682 case 71:
14683 // LD1H, LD1H_D, LD1H_S, LD1RO_H, LD1RQ_H, LD1SH_D, LD1SH_S, LD2H, LD3H, ...
14684 printRegWithShiftExtend<false, 16, 'x', 0>(MI, 3, STI, O);
14685 O << ']';
14686 return;
14687 break;
14688 case 72:
14689 // LD1RO_B_IMM, LD1RO_D_IMM, LD1RO_H_IMM, LD1RO_W_IMM
14690 printImmScale<32>(MI, 3, STI, O);
14691 O << ']';
14692 return;
14693 break;
14694 case 73:
14695 // LD1RO_W, LD1RQ_W, LD1SW_D, LD1W, LD1W_D, LD2W, LD3W, LD4W, LDFF1SW_D_R...
14696 printRegWithShiftExtend<false, 32, 'x', 0>(MI, 3, STI, O);
14697 O << ']';
14698 return;
14699 break;
14700 case 74:
14701 // LD1RQ_B_IMM, LD1RQ_D_IMM, LD1RQ_H_IMM, LD1RQ_W_IMM, LDG, ST2GPostIndex...
14702 printImmScale<16>(MI, 3, STI, O);
14703 break;
14704 case 75:
14705 // LD3B_IMM, LD3D_IMM, LD3H_IMM, LD3W_IMM, ST3B_IMM, ST3D_IMM, ST3H_IMM, ...
14706 printImmScale<3>(MI, 3, STI, O);
14707 O << ", mul vl]";
14708 return;
14709 break;
14710 case 76:
14711 // LDRAAindexed, LDRABindexed
14712 printImmScale<8>(MI, 2, STI, O);
14713 O << ']';
14714 return;
14715 break;
14716 case 77:
14717 // LDRBBui, LDRBui, LDRSBWui, LDRSBXui, STRBBui, STRBui
14718 printUImm12Offset<1>(MI, 2, STI, O);
14719 O << ']';
14720 return;
14721 break;
14722 case 78:
14723 // LDRDui, LDRXui, PRFMui, STRDui, STRXui
14724 printUImm12Offset<8>(MI, 2, STI, O);
14725 O << ']';
14726 return;
14727 break;
14728 case 79:
14729 // LDRHHui, LDRHui, LDRSHWui, LDRSHXui, STRHHui, STRHui
14730 printUImm12Offset<2>(MI, 2, STI, O);
14731 O << ']';
14732 return;
14733 break;
14734 case 80:
14735 // LDRQui, STRQui
14736 printUImm12Offset<16>(MI, 2, STI, O);
14737 O << ']';
14738 return;
14739 break;
14740 case 81:
14741 // LDRSWui, LDRSui, LDRWui, STRSui, STRWui
14742 printUImm12Offset<4>(MI, 2, STI, O);
14743 O << ']';
14744 return;
14745 break;
14746 case 82:
14747 // MAD_ZPmZZ_B, MLA_ZPmZZ_B, MLS_ZPmZZ_B, MSB_ZPmZZ_B
14748 printSVERegOp<'b'>(MI, 3, STI, O);
14749 O << ", ";
14750 printSVERegOp<'b'>(MI, 4, STI, O);
14751 return;
14752 break;
14753 case 83:
14754 // PRFB_D_PZI, PRFB_S_PZI
14755 O << ']';
14756 return;
14757 break;
14758 case 84:
14759 // PRFB_PRI, PRFD_PRI, PRFH_PRI, PRFW_PRI
14760 O << ", mul vl]";
14761 return;
14762 break;
14763 case 85:
14764 // SPLICE_ZPZZ_B
14765 printTypedVectorList<0,'b'>(MI, 2, STI, O);
14766 return;
14767 break;
14768 case 86:
14769 // SPLICE_ZPZZ_D
14770 printTypedVectorList<0,'d'>(MI, 2, STI, O);
14771 return;
14772 break;
14773 case 87:
14774 // SPLICE_ZPZZ_S
14775 printTypedVectorList<0,'s'>(MI, 2, STI, O);
14776 return;
14777 break;
14778 case 88:
14779 // SQDECP_XPWd_B, SQDECP_XPWd_D, SQDECP_XPWd_H, SQDECP_XPWd_S, SQINCP_XPW...
14780 printGPR64as32(MI, 2, STI, O);
14781 return;
14782 break;
14783 case 89:
14784 // SYSLxt
14785 printSysCROperand(MI, 2, STI, O);
14786 O << ", ";
14787 printSysCROperand(MI, 3, STI, O);
14788 O << ", ";
14789 printOperand(MI, 4, STI, O);
14790 return;
14791 break;
14792 case 90:
14793 // TBNZW, TBNZX, TBZW, TBZX
14794 printAlignedLabel(MI, Address, 2, STI, O);
14795 return;
14796 break;
14797 case 91:
14798 // UMAX_ZI_B, UMAX_ZI_D, UMAX_ZI_S, UMIN_ZI_B, UMIN_ZI_D, UMIN_ZI_S
14799 printImm(MI, 2, STI, O);
14800 return;
14801 break;
14802 }
14803
14804
14805 // Fragment 5 encoded into 6 bits for 40 unique commands.
14806 switch ((Bits >> 45) & 63) {
14807 default: llvm_unreachable("Invalid command number.");
14808 case 0:
14809 // ADCLB_ZZZ_D, ADCLB_ZZZ_S, ADCLT_ZZZ_D, ADCLT_ZZZ_S, ADCSWr, ADCSXr, AD...
14810 return;
14811 break;
14812 case 1:
14813 // ADDG, ADDP_ZPmZ_B, ADDP_ZPmZ_D, ADDP_ZPmZ_S, ADD_ZPmZ_B, ADD_ZPmZ_D, A...
14814 O << ", ";
14815 break;
14816 case 2:
14817 // ADDHNv2i64_v2i32, ADDHNv2i64_v4i32, ADDPv2i64, ADDv2i64, CMEQv2i64, CM...
14818 O << ".2d";
14819 return;
14820 break;
14821 case 3:
14822 // ADDHNv4i32_v4i16, ADDHNv4i32_v8i16, ADDPv4i32, ADDv4i32, CMEQv4i32, CM...
14823 O << ".4s";
14824 return;
14825 break;
14826 case 4:
14827 // ADDHNv8i16_v16i8, ADDHNv8i16_v8i8, ADDPv8i16, ADDv8i16, BFDOTv8bf16, B...
14828 O << ".8h";
14829 return;
14830 break;
14831 case 5:
14832 // ADDP_ZPmZ_H, ADD_ZPmZ_H, AND_ZPmZ_H, ASRR_ZPmZ_H, ASR_ZPmZ_H, BIC_ZPmZ...
14833 printSVERegOp<'h'>(MI, 3, STI, O);
14834 break;
14835 case 6:
14836 // ADDPv16i8, ADDv16i8, ANDv16i8, BICv16i8, BIFv16i8, BITv16i8, BSLv16i8,...
14837 O << ".16b";
14838 return;
14839 break;
14840 case 7:
14841 // ADDPv2i32, ADDv2i32, CMEQv2i32, CMGEv2i32, CMGTv2i32, CMHIv2i32, CMHSv...
14842 O << ".2s";
14843 return;
14844 break;
14845 case 8:
14846 // ADDPv4i16, ADDv4i16, BFDOTv4bf16, CMEQv4i16, CMGEv4i16, CMGTv4i16, CMH...
14847 O << ".4h";
14848 return;
14849 break;
14850 case 9:
14851 // ADDPv8i8, ADDv8i8, ANDv8i8, BICv8i8, BIFv8i8, BITv8i8, BSLv8i8, CMEQv8...
14852 O << ".8b";
14853 return;
14854 break;
14855 case 10:
14856 // ADDSXrx64, ADDXrx64, SUBSXrx64, SUBXrx64
14857 printArithExtend(MI, 3, STI, O);
14858 return;
14859 break;
14860 case 11:
14861 // ASRD_ZPmI_H, ASR_ZPmI_H, CMPEQ_PPzZI_H, CMPGE_PPzZI_H, CMPGT_PPzZI_H, ...
14862 printOperand(MI, 3, STI, O);
14863 return;
14864 break;
14865 case 12:
14866 // ASR_WIDE_ZPmZ_H, CMPEQ_WIDE_PPzZZ_H, CMPGE_WIDE_PPzZZ_H, CMPGT_WIDE_PP...
14867 printSVERegOp<'d'>(MI, 3, STI, O);
14868 return;
14869 break;
14870 case 13:
14871 // BCAX, EOR3, EXTv16i8
14872 O << ".16b, ";
14873 break;
14874 case 14:
14875 // BF16DOTlanev4bf16, BF16DOTlanev8bf16
14876 O << ".2h";
14877 printVectorIndex(MI, 4, STI, O);
14878 return;
14879 break;
14880 case 15:
14881 // BFDOT_ZZI, BFMMLA_B_ZZI, BFMMLA_T_ZZI, CDOT_ZZZI_D, CMLA_ZZZI_S, FCMLA...
14882 printVectorIndex(MI, 4, STI, O);
14883 break;
14884 case 16:
14885 // BFMLALBIdx, BFMLALTIdx, FCMLAv4f16_indexed, FCMLAv8f16_indexed, FMLAL2...
14886 O << ".h";
14887 break;
14888 case 17:
14889 // CADD_ZZI_H, SQCADD_ZZI_H
14890 printComplexRotationOp<180, 90>(MI, 3, STI, O);
14891 return;
14892 break;
14893 case 18:
14894 // CASAB, CASAH, CASALB, CASALH, CASALW, CASALX, CASAW, CASAX, CASB, CASH...
14895 O << ']';
14896 return;
14897 break;
14898 case 19:
14899 // CDOT_ZZZ_S, CMLA_ZZZ_B, CMLA_ZZZ_H, SQRDCMLAH_ZZZ_B, SQRDCMLAH_ZZZ_H
14900 printComplexRotationOp<90, 0>(MI, 4, STI, O);
14901 return;
14902 break;
14903 case 20:
14904 // CMPHI_PPzZI_H, CMPHS_PPzZI_H, CMPLO_PPzZI_H, CMPLS_PPzZI_H
14905 printImm(MI, 3, STI, O);
14906 return;
14907 break;
14908 case 21:
14909 // EXTv8i8
14910 O << ".8b, ";
14911 printOperand(MI, 3, STI, O);
14912 return;
14913 break;
14914 case 22:
14915 // FADD_ZPmI_H, FSUBR_ZPmI_H, FSUB_ZPmI_H
14916 printExactFPImm<AArch64ExactFPImm::half, AArch64ExactFPImm::one>(MI, 3, STI, O);
14917 return;
14918 break;
14919 case 23:
14920 // FCADDv2f32, FCMLAv2f32
14921 O << ".2s, ";
14922 break;
14923 case 24:
14924 // FCADDv2f64, FCMLAv2f64, XAR
14925 O << ".2d, ";
14926 break;
14927 case 25:
14928 // FCADDv4f16, FCMLAv4f16
14929 O << ".4h, ";
14930 break;
14931 case 26:
14932 // FCADDv4f32, FCMLAv4f32, SM3SS1
14933 O << ".4s, ";
14934 break;
14935 case 27:
14936 // FCADDv8f16, FCMLAv8f16
14937 O << ".8h, ";
14938 break;
14939 case 28:
14940 // FCMEQ_PPzZ0_D, FCMEQ_PPzZ0_S, FCMGE_PPzZ0_D, FCMGE_PPzZ0_S, FCMGT_PPzZ...
14941 O << ", #0.0";
14942 return;
14943 break;
14944 case 29:
14945 // FCMLA_ZPmZZ_H, FMAD_ZPmZZ_H, FMLA_ZPmZZ_H, FMLS_ZPmZZ_H, FMSB_ZPmZZ_H,...
14946 printSVERegOp<'h'>(MI, 4, STI, O);
14947 break;
14948 case 30:
14949 // FCMLAv4f32_indexed, FMLAv1i32_indexed, FMLAv2i32_indexed, FMLAv4i32_in...
14950 O << ".s";
14951 break;
14952 case 31:
14953 // FMAXNM_ZPmI_H, FMAX_ZPmI_H, FMINNM_ZPmI_H, FMIN_ZPmI_H
14954 printExactFPImm<AArch64ExactFPImm::zero, AArch64ExactFPImm::one>(MI, 3, STI, O);
14955 return;
14956 break;
14957 case 32:
14958 // FMLAv1i64_indexed, FMLAv2i64_indexed, FMLSv1i64_indexed, FMLSv2i64_ind...
14959 O << ".d";
14960 break;
14961 case 33:
14962 // FMUL_ZPmI_H
14963 printExactFPImm<AArch64ExactFPImm::half, AArch64ExactFPImm::two>(MI, 3, STI, O);
14964 return;
14965 break;
14966 case 34:
14967 // FMUL_ZZZI_D, FMUL_ZZZI_S, MUL_ZZZI_D, MUL_ZZZI_S, SMULLB_ZZZI_D, SMULL...
14968 printVectorIndex(MI, 3, STI, O);
14969 return;
14970 break;
14971 case 35:
14972 // LD1B_D_IMM_REAL, LD1B_H_IMM_REAL, LD1B_IMM_REAL, LD1B_S_IMM_REAL, LD1D...
14973 O << ", mul vl]";
14974 return;
14975 break;
14976 case 36:
14977 // LDPDpost, LDPQpost, LDPSWpost, LDPSpost, LDPWpost, LDPXpost, STGPpost,...
14978 O << "], ";
14979 break;
14980 case 37:
14981 // LDRAAwriteback, LDRABwriteback, LDRBBpre, LDRBpre, LDRDpre, LDRHHpre, ...
14982 O << "]!";
14983 return;
14984 break;
14985 case 38:
14986 // SDOTlanev16i8, SDOTlanev8i8, SUDOTlanev16i8, SUDOTlanev8i8, UDOTlanev1...
14987 O << ".4b";
14988 printVectorIndex(MI, 4, STI, O);
14989 return;
14990 break;
14991 case 39:
14992 // STLXPW, STLXPX, STXPW, STXPX
14993 O << ", [";
14994 printOperand(MI, 3, STI, O);
14995 O << ']';
14996 return;
14997 break;
14998 }
14999
15000
15001 // Fragment 6 encoded into 6 bits for 37 unique commands.
15002 switch ((Bits >> 51) & 63) {
15003 default: llvm_unreachable("Invalid command number.");
15004 case 0:
15005 // ADDG, ASRD_ZPmI_B, ASRD_ZPmI_D, ASRD_ZPmI_S, ASR_ZPmI_B, ASR_ZPmI_D, A...
15006 printOperand(MI, 3, STI, O);
15007 return;
15008 break;
15009 case 1:
15010 // ADDP_ZPmZ_B, ADD_ZPmZ_B, ANDS_PPzPP, AND_PPzPP, AND_ZPmZ_B, ASRR_ZPmZ_...
15011 printSVERegOp<'b'>(MI, 3, STI, O);
15012 return;
15013 break;
15014 case 2:
15015 // ADDP_ZPmZ_D, ADD_ZPmZ_D, AND_ZPmZ_D, ASRR_ZPmZ_D, ASR_WIDE_ZPmZ_B, ASR...
15016 printSVERegOp<'d'>(MI, 3, STI, O);
15017 break;
15018 case 3:
15019 // ADDP_ZPmZ_H, ADD_ZPmZ_H, AND_ZPmZ_H, ASRR_ZPmZ_H, ASR_ZPmZ_H, BFDOT_ZZ...
15020 return;
15021 break;
15022 case 4:
15023 // ADDP_ZPmZ_S, ADD_ZPmZ_S, AND_ZPmZ_S, ASRR_ZPmZ_S, ASR_ZPmZ_S, BIC_ZPmZ...
15024 printSVERegOp<'s'>(MI, 3, STI, O);
15025 break;
15026 case 5:
15027 // BCAX, EOR3, SM3SS1
15028 printVRegOperand(MI, 3, STI, O);
15029 break;
15030 case 6:
15031 // BFMLALBIdx, BFMLALTIdx, FCMLAv4f16_indexed, FCMLAv4f32_indexed, FCMLAv...
15032 printVectorIndex(MI, 4, STI, O);
15033 break;
15034 case 7:
15035 // BFMWri, BFMXri
15036 printOperand(MI, 4, STI, O);
15037 return;
15038 break;
15039 case 8:
15040 // CADD_ZZI_B, CADD_ZZI_D, CADD_ZZI_S, FCADDv2f32, FCADDv2f64, FCADDv4f16...
15041 printComplexRotationOp<180, 90>(MI, 3, STI, O);
15042 return;
15043 break;
15044 case 9:
15045 // CCMNWi, CCMNWr, CCMNXi, CCMNXr, CCMPWi, CCMPWr, CCMPXi, CCMPXr, CSELWr...
15046 printCondCode(MI, 3, STI, O);
15047 return;
15048 break;
15049 case 10:
15050 // CDOT_ZZZI_D, CMLA_ZZZI_S, FCADD_ZPmZ_H, FCMLA_ZPmZZ_H, FCMLA_ZZZI_S, S...
15051 O << ", ";
15052 break;
15053 case 11:
15054 // CDOT_ZZZI_S, CMLA_ZZZI_H, FCMLA_ZZZI_H, SQRDCMLAH_ZZZI_H
15055 printComplexRotationOp<90, 0>(MI, 5, STI, O);
15056 return;
15057 break;
15058 case 12:
15059 // CDOT_ZZZ_D, CMLA_ZZZ_D, CMLA_ZZZ_S, FCMLAv2f32, FCMLAv2f64, FCMLAv4f16...
15060 printComplexRotationOp<90, 0>(MI, 4, STI, O);
15061 return;
15062 break;
15063 case 13:
15064 // CLASTA_RPZ_H, CLASTA_VPZ_H, CLASTB_RPZ_H, CLASTB_VPZ_H
15065 printSVERegOp<'h'>(MI, 3, STI, O);
15066 return;
15067 break;
15068 case 14:
15069 // CMPHI_PPzZI_B, CMPHI_PPzZI_D, CMPHI_PPzZI_S, CMPHS_PPzZI_B, CMPHS_PPzZ...
15070 printImm(MI, 3, STI, O);
15071 return;
15072 break;
15073 case 15:
15074 // FADD_ZPmI_D, FADD_ZPmI_S, FSUBR_ZPmI_D, FSUBR_ZPmI_S, FSUB_ZPmI_D, FSU...
15075 printExactFPImm<AArch64ExactFPImm::half, AArch64ExactFPImm::one>(MI, 3, STI, O);
15076 return;
15077 break;
15078 case 16:
15079 // FCMLA_ZPmZZ_D, FMAD_ZPmZZ_D, FMLA_ZPmZZ_D, FMLS_ZPmZZ_D, FMSB_ZPmZZ_D,...
15080 printSVERegOp<'d'>(MI, 4, STI, O);
15081 break;
15082 case 17:
15083 // FCMLA_ZPmZZ_S, FMAD_ZPmZZ_S, FMLA_ZPmZZ_S, FMLS_ZPmZZ_S, FMSB_ZPmZZ_S,...
15084 printSVERegOp<'s'>(MI, 4, STI, O);
15085 break;
15086 case 18:
15087 // FMAXNM_ZPmI_D, FMAXNM_ZPmI_S, FMAX_ZPmI_D, FMAX_ZPmI_S, FMINNM_ZPmI_D,...
15088 printExactFPImm<AArch64ExactFPImm::zero, AArch64ExactFPImm::one>(MI, 3, STI, O);
15089 return;
15090 break;
15091 case 19:
15092 // FMULXv1i16_indexed, FMULXv1i32_indexed, FMULXv1i64_indexed, FMULXv2i32...
15093 printVectorIndex(MI, 3, STI, O);
15094 return;
15095 break;
15096 case 20:
15097 // FMUL_ZPmI_D, FMUL_ZPmI_S
15098 printExactFPImm<AArch64ExactFPImm::half, AArch64ExactFPImm::two>(MI, 3, STI, O);
15099 return;
15100 break;
15101 case 21:
15102 // LDNPDi, LDNPXi, LDPDi, LDPXi, STNPDi, STNPXi, STPDi, STPXi
15103 printImmScale<8>(MI, 3, STI, O);
15104 O << ']';
15105 return;
15106 break;
15107 case 22:
15108 // LDNPQi, LDPQi, STGPi, STNPQi, STPQi
15109 printImmScale<16>(MI, 3, STI, O);
15110 O << ']';
15111 return;
15112 break;
15113 case 23:
15114 // LDNPSi, LDNPWi, LDPSWi, LDPSi, LDPWi, STNPSi, STNPWi, STPSi, STPWi
15115 printImmScale<4>(MI, 3, STI, O);
15116 O << ']';
15117 return;
15118 break;
15119 case 24:
15120 // LDPDpost, LDPDpre, LDPXpost, LDPXpre, STPDpost, STPDpre, STPXpost, STP...
15121 printImmScale<8>(MI, 4, STI, O);
15122 break;
15123 case 25:
15124 // LDPQpost, LDPQpre, STGPpost, STGPpre, STPQpost, STPQpre
15125 printImmScale<16>(MI, 4, STI, O);
15126 break;
15127 case 26:
15128 // LDPSWpost, LDPSWpre, LDPSpost, LDPSpre, LDPWpost, LDPWpre, STPSpost, S...
15129 printImmScale<4>(MI, 4, STI, O);
15130 break;
15131 case 27:
15132 // LDRBBroW, LDRBroW, LDRSBWroW, LDRSBXroW, STRBBroW, STRBroW
15133 printMemExtend<'w', 8>(MI, 3, STI, O);
15134 O << ']';
15135 return;
15136 break;
15137 case 28:
15138 // LDRBBroX, LDRBroX, LDRSBWroX, LDRSBXroX, STRBBroX, STRBroX
15139 printMemExtend<'x', 8>(MI, 3, STI, O);
15140 O << ']';
15141 return;
15142 break;
15143 case 29:
15144 // LDRDroW, LDRXroW, PRFMroW, STRDroW, STRXroW
15145 printMemExtend<'w', 64>(MI, 3, STI, O);
15146 O << ']';
15147 return;
15148 break;
15149 case 30:
15150 // LDRDroX, LDRXroX, PRFMroX, STRDroX, STRXroX
15151 printMemExtend<'x', 64>(MI, 3, STI, O);
15152 O << ']';
15153 return;
15154 break;
15155 case 31:
15156 // LDRHHroW, LDRHroW, LDRSHWroW, LDRSHXroW, STRHHroW, STRHroW
15157 printMemExtend<'w', 16>(MI, 3, STI, O);
15158 O << ']';
15159 return;
15160 break;
15161 case 32:
15162 // LDRHHroX, LDRHroX, LDRSHWroX, LDRSHXroX, STRHHroX, STRHroX
15163 printMemExtend<'x', 16>(MI, 3, STI, O);
15164 O << ']';
15165 return;
15166 break;
15167 case 33:
15168 // LDRQroW, STRQroW
15169 printMemExtend<'w', 128>(MI, 3, STI, O);
15170 O << ']';
15171 return;
15172 break;
15173 case 34:
15174 // LDRQroX, STRQroX
15175 printMemExtend<'x', 128>(MI, 3, STI, O);
15176 O << ']';
15177 return;
15178 break;
15179 case 35:
15180 // LDRSWroW, LDRSroW, LDRWroW, STRSroW, STRWroW
15181 printMemExtend<'w', 32>(MI, 3, STI, O);
15182 O << ']';
15183 return;
15184 break;
15185 case 36:
15186 // LDRSWroX, LDRSroX, LDRWroX, STRSroX, STRWroX
15187 printMemExtend<'x', 32>(MI, 3, STI, O);
15188 O << ']';
15189 return;
15190 break;
15191 }
15192
15193
15194 // Fragment 7 encoded into 3 bits for 7 unique commands.
15195 switch ((Bits >> 57) & 7) {
15196 default: llvm_unreachable("Invalid command number.");
15197 case 0:
15198 // ADDP_ZPmZ_D, ADDP_ZPmZ_S, ADD_ZPmZ_D, ADD_ZPmZ_S, AND_ZPmZ_D, AND_ZPmZ...
15199 return;
15200 break;
15201 case 1:
15202 // BCAX, EOR3
15203 O << ".16b";
15204 return;
15205 break;
15206 case 2:
15207 // CDOT_ZZZI_D, CMLA_ZZZI_S, FCMLA_ZPmZZ_H, FCMLA_ZZZI_S, SQRDCMLAH_ZZZI_...
15208 printComplexRotationOp<90, 0>(MI, 5, STI, O);
15209 return;
15210 break;
15211 case 3:
15212 // FCADD_ZPmZ_D, FCADD_ZPmZ_S, FCMLA_ZPmZZ_D, FCMLA_ZPmZZ_S, FCMLAv4f16_i...
15213 O << ", ";
15214 break;
15215 case 4:
15216 // FCADD_ZPmZ_H
15217 printComplexRotationOp<180, 90>(MI, 4, STI, O);
15218 return;
15219 break;
15220 case 5:
15221 // LDPDpre, LDPQpre, LDPSWpre, LDPSpre, LDPWpre, LDPXpre, STGPpre, STPDpr...
15222 O << "]!";
15223 return;
15224 break;
15225 case 6:
15226 // SM3SS1
15227 O << ".4s";
15228 return;
15229 break;
15230 }
15231
15232
15233 // Fragment 8 encoded into 1 bits for 2 unique commands.
15234 if ((Bits >> 60) & 1) {
15235 // FCMLA_ZPmZZ_D, FCMLA_ZPmZZ_S, FCMLAv4f16_indexed, FCMLAv4f32_indexed, ...
15236 printComplexRotationOp<90, 0>(MI, 5, STI, O);
15237 return;
15238 } else {
15239 // FCADD_ZPmZ_D, FCADD_ZPmZ_S
15240 printComplexRotationOp<180, 90>(MI, 4, STI, O);
15241 return;
15242 }
15243
15244}
15245
15246
15247/// getRegisterName - This method is automatically generated by tblgen
15248/// from the register set description. This returns the assembler name
15249/// for the specified register.
15250const char *AArch64InstPrinter::
15251getRegisterName(unsigned RegNo, unsigned AltIdx) {
15252 assert(RegNo && RegNo < 642 && "Invalid register number!");
15253
15254
15255#ifdef __GNUC__
15256#pragma GCC diagnostic push
15257#pragma GCC diagnostic ignored "-Woverlength-strings"
15258#endif
15259 static const char AsmStrsNoRegAltName[] = {
15260 /* 0 */ "D7_D8_D9_D10\0"
15261 /* 13 */ "Q7_Q8_Q9_Q10\0"
15262 /* 26 */ "Z7_Z8_Z9_Z10\0"
15263 /* 39 */ "b10\0"
15264 /* 43 */ "d10\0"
15265 /* 47 */ "h10\0"
15266 /* 51 */ "p10\0"
15267 /* 55 */ "q10\0"
15268 /* 59 */ "s10\0"
15269 /* 63 */ "w10\0"
15270 /* 67 */ "x10\0"
15271 /* 71 */ "z10\0"
15272 /* 75 */ "D17_D18_D19_D20\0"
15273 /* 91 */ "Q17_Q18_Q19_Q20\0"
15274 /* 107 */ "Z17_Z18_Z19_Z20\0"
15275 /* 123 */ "b20\0"
15276 /* 127 */ "d20\0"
15277 /* 131 */ "h20\0"
15278 /* 135 */ "q20\0"
15279 /* 139 */ "s20\0"
15280 /* 143 */ "w20\0"
15281 /* 147 */ "x20\0"
15282 /* 151 */ "z20\0"
15283 /* 155 */ "D27_D28_D29_D30\0"
15284 /* 171 */ "Q27_Q28_Q29_Q30\0"
15285 /* 187 */ "Z27_Z28_Z29_Z30\0"
15286 /* 203 */ "b30\0"
15287 /* 207 */ "d30\0"
15288 /* 211 */ "h30\0"
15289 /* 215 */ "q30\0"
15290 /* 219 */ "s30\0"
15291 /* 223 */ "w30\0"
15292 /* 227 */ "x30\0"
15293 /* 231 */ "z30\0"
15294 /* 235 */ "D29_D30_D31_D0\0"
15295 /* 250 */ "Q29_Q30_Q31_Q0\0"
15296 /* 265 */ "Z29_Z30_Z31_Z0\0"
15297 /* 280 */ "b0\0"
15298 /* 283 */ "d0\0"
15299 /* 286 */ "h0\0"
15300 /* 289 */ "p0\0"
15301 /* 292 */ "q0\0"
15302 /* 295 */ "s0\0"
15303 /* 298 */ "w0\0"
15304 /* 301 */ "x0\0"
15305 /* 304 */ "z0\0"
15306 /* 307 */ "D8_D9_D10_D11\0"
15307 /* 321 */ "Q8_Q9_Q10_Q11\0"
15308 /* 335 */ "W10_W11\0"
15309 /* 343 */ "X4_X5_X6_X7_X8_X9_X10_X11\0"
15310 /* 369 */ "Z8_Z9_Z10_Z11\0"
15311 /* 383 */ "b11\0"
15312 /* 387 */ "d11\0"
15313 /* 391 */ "h11\0"
15314 /* 395 */ "p11\0"
15315 /* 399 */ "q11\0"
15316 /* 403 */ "s11\0"
15317 /* 407 */ "w11\0"
15318 /* 411 */ "x11\0"
15319 /* 415 */ "z11\0"
15320 /* 419 */ "D18_D19_D20_D21\0"
15321 /* 435 */ "Q18_Q19_Q20_Q21\0"
15322 /* 451 */ "W20_W21\0"
15323 /* 459 */ "X14_X15_X16_X17_X18_X19_X20_X21\0"
15324 /* 491 */ "Z18_Z19_Z20_Z21\0"
15325 /* 507 */ "b21\0"
15326 /* 511 */ "d21\0"
15327 /* 515 */ "h21\0"
15328 /* 519 */ "q21\0"
15329 /* 523 */ "s21\0"
15330 /* 527 */ "w21\0"
15331 /* 531 */ "x21\0"
15332 /* 535 */ "z21\0"
15333 /* 539 */ "D28_D29_D30_D31\0"
15334 /* 555 */ "Q28_Q29_Q30_Q31\0"
15335 /* 571 */ "Z28_Z29_Z30_Z31\0"
15336 /* 587 */ "b31\0"
15337 /* 591 */ "d31\0"
15338 /* 595 */ "h31\0"
15339 /* 599 */ "q31\0"
15340 /* 603 */ "s31\0"
15341 /* 607 */ "z31\0"
15342 /* 611 */ "D30_D31_D0_D1\0"
15343 /* 625 */ "Q30_Q31_Q0_Q1\0"
15344 /* 639 */ "W0_W1\0"
15345 /* 645 */ "X0_X1\0"
15346 /* 651 */ "Z30_Z31_Z0_Z1\0"
15347 /* 665 */ "b1\0"
15348 /* 668 */ "d1\0"
15349 /* 671 */ "h1\0"
15350 /* 674 */ "p1\0"
15351 /* 677 */ "q1\0"
15352 /* 680 */ "s1\0"
15353 /* 683 */ "w1\0"
15354 /* 686 */ "x1\0"
15355 /* 689 */ "z1\0"
15356 /* 692 */ "D9_D10_D11_D12\0"
15357 /* 707 */ "Q9_Q10_Q11_Q12\0"
15358 /* 722 */ "Z9_Z10_Z11_Z12\0"
15359 /* 737 */ "b12\0"
15360 /* 741 */ "d12\0"
15361 /* 745 */ "h12\0"
15362 /* 749 */ "p12\0"
15363 /* 753 */ "q12\0"
15364 /* 757 */ "s12\0"
15365 /* 761 */ "w12\0"
15366 /* 765 */ "x12\0"
15367 /* 769 */ "z12\0"
15368 /* 773 */ "D19_D20_D21_D22\0"
15369 /* 789 */ "Q19_Q20_Q21_Q22\0"
15370 /* 805 */ "Z19_Z20_Z21_Z22\0"
15371 /* 821 */ "b22\0"
15372 /* 825 */ "d22\0"
15373 /* 829 */ "h22\0"
15374 /* 833 */ "q22\0"
15375 /* 837 */ "s22\0"
15376 /* 841 */ "w22\0"
15377 /* 845 */ "x22\0"
15378 /* 849 */ "z22\0"
15379 /* 853 */ "D31_D0_D1_D2\0"
15380 /* 866 */ "Q31_Q0_Q1_Q2\0"
15381 /* 879 */ "Z31_Z0_Z1_Z2\0"
15382 /* 892 */ "b2\0"
15383 /* 895 */ "d2\0"
15384 /* 898 */ "h2\0"
15385 /* 901 */ "p2\0"
15386 /* 904 */ "q2\0"
15387 /* 907 */ "s2\0"
15388 /* 910 */ "w2\0"
15389 /* 913 */ "x2\0"
15390 /* 916 */ "z2\0"
15391 /* 919 */ "D10_D11_D12_D13\0"
15392 /* 935 */ "Q10_Q11_Q12_Q13\0"
15393 /* 951 */ "W12_W13\0"
15394 /* 959 */ "X6_X7_X8_X9_X10_X11_X12_X13\0"
15395 /* 987 */ "Z10_Z11_Z12_Z13\0"
15396 /* 1003 */ "b13\0"
15397 /* 1007 */ "d13\0"
15398 /* 1011 */ "h13\0"
15399 /* 1015 */ "p13\0"
15400 /* 1019 */ "q13\0"
15401 /* 1023 */ "s13\0"
15402 /* 1027 */ "w13\0"
15403 /* 1031 */ "x13\0"
15404 /* 1035 */ "z13\0"
15405 /* 1039 */ "D20_D21_D22_D23\0"
15406 /* 1055 */ "Q20_Q21_Q22_Q23\0"
15407 /* 1071 */ "W22_W23\0"
15408 /* 1079 */ "X16_X17_X18_X19_X20_X21_X22_X23\0"
15409 /* 1111 */ "Z20_Z21_Z22_Z23\0"
15410 /* 1127 */ "b23\0"
15411 /* 1131 */ "d23\0"
15412 /* 1135 */ "h23\0"
15413 /* 1139 */ "q23\0"
15414 /* 1143 */ "s23\0"
15415 /* 1147 */ "w23\0"
15416 /* 1151 */ "x23\0"
15417 /* 1155 */ "z23\0"
15418 /* 1159 */ "D0_D1_D2_D3\0"
15419 /* 1171 */ "Q0_Q1_Q2_Q3\0"
15420 /* 1183 */ "W2_W3\0"
15421 /* 1189 */ "X2_X3\0"
15422 /* 1195 */ "Z0_Z1_Z2_Z3\0"
15423 /* 1207 */ "b3\0"
15424 /* 1210 */ "d3\0"
15425 /* 1213 */ "h3\0"
15426 /* 1216 */ "p3\0"
15427 /* 1219 */ "q3\0"
15428 /* 1222 */ "s3\0"
15429 /* 1225 */ "w3\0"
15430 /* 1228 */ "x3\0"
15431 /* 1231 */ "z3\0"
15432 /* 1234 */ "D11_D12_D13_D14\0"
15433 /* 1250 */ "Q11_Q12_Q13_Q14\0"
15434 /* 1266 */ "Z11_Z12_Z13_Z14\0"
15435 /* 1282 */ "b14\0"
15436 /* 1286 */ "d14\0"
15437 /* 1290 */ "h14\0"
15438 /* 1294 */ "p14\0"
15439 /* 1298 */ "q14\0"
15440 /* 1302 */ "s14\0"
15441 /* 1306 */ "w14\0"
15442 /* 1310 */ "x14\0"
15443 /* 1314 */ "z14\0"
15444 /* 1318 */ "D21_D22_D23_D24\0"
15445 /* 1334 */ "Q21_Q22_Q23_Q24\0"
15446 /* 1350 */ "Z21_Z22_Z23_Z24\0"
15447 /* 1366 */ "b24\0"
15448 /* 1370 */ "d24\0"
15449 /* 1374 */ "h24\0"
15450 /* 1378 */ "q24\0"
15451 /* 1382 */ "s24\0"
15452 /* 1386 */ "w24\0"
15453 /* 1390 */ "x24\0"
15454 /* 1394 */ "z24\0"
15455 /* 1398 */ "D1_D2_D3_D4\0"
15456 /* 1410 */ "Q1_Q2_Q3_Q4\0"
15457 /* 1422 */ "Z1_Z2_Z3_Z4\0"
15458 /* 1434 */ "b4\0"
15459 /* 1437 */ "d4\0"
15460 /* 1440 */ "h4\0"
15461 /* 1443 */ "p4\0"
15462 /* 1446 */ "q4\0"
15463 /* 1449 */ "s4\0"
15464 /* 1452 */ "w4\0"
15465 /* 1455 */ "x4\0"
15466 /* 1458 */ "z4\0"
15467 /* 1461 */ "D12_D13_D14_D15\0"
15468 /* 1477 */ "Q12_Q13_Q14_Q15\0"
15469 /* 1493 */ "W14_W15\0"
15470 /* 1501 */ "X8_X9_X10_X11_X12_X13_X14_X15\0"
15471 /* 1531 */ "Z12_Z13_Z14_Z15\0"
15472 /* 1547 */ "b15\0"
15473 /* 1551 */ "d15\0"
15474 /* 1555 */ "h15\0"
15475 /* 1559 */ "p15\0"
15476 /* 1563 */ "q15\0"
15477 /* 1567 */ "s15\0"
15478 /* 1571 */ "w15\0"
15479 /* 1575 */ "x15\0"
15480 /* 1579 */ "z15\0"
15481 /* 1583 */ "D22_D23_D24_D25\0"
15482 /* 1599 */ "Q22_Q23_Q24_Q25\0"
15483 /* 1615 */ "W24_W25\0"
15484 /* 1623 */ "X18_X19_X20_X21_X22_X23_X24_X25\0"
15485 /* 1655 */ "Z22_Z23_Z24_Z25\0"
15486 /* 1671 */ "b25\0"
15487 /* 1675 */ "d25\0"
15488 /* 1679 */ "h25\0"
15489 /* 1683 */ "q25\0"
15490 /* 1687 */ "s25\0"
15491 /* 1691 */ "w25\0"
15492 /* 1695 */ "x25\0"
15493 /* 1699 */ "z25\0"
15494 /* 1703 */ "D2_D3_D4_D5\0"
15495 /* 1715 */ "Q2_Q3_Q4_Q5\0"
15496 /* 1727 */ "W4_W5\0"
15497 /* 1733 */ "X4_X5\0"
15498 /* 1739 */ "Z2_Z3_Z4_Z5\0"
15499 /* 1751 */ "b5\0"
15500 /* 1754 */ "d5\0"
15501 /* 1757 */ "h5\0"
15502 /* 1760 */ "p5\0"
15503 /* 1763 */ "q5\0"
15504 /* 1766 */ "s5\0"
15505 /* 1769 */ "w5\0"
15506 /* 1772 */ "x5\0"
15507 /* 1775 */ "z5\0"
15508 /* 1778 */ "D13_D14_D15_D16\0"
15509 /* 1794 */ "Q13_Q14_Q15_Q16\0"
15510 /* 1810 */ "Z13_Z14_Z15_Z16\0"
15511 /* 1826 */ "b16\0"
15512 /* 1830 */ "d16\0"
15513 /* 1834 */ "h16\0"
15514 /* 1838 */ "q16\0"
15515 /* 1842 */ "s16\0"
15516 /* 1846 */ "w16\0"
15517 /* 1850 */ "x16\0"
15518 /* 1854 */ "z16\0"
15519 /* 1858 */ "D23_D24_D25_D26\0"
15520 /* 1874 */ "Q23_Q24_Q25_Q26\0"
15521 /* 1890 */ "Z23_Z24_Z25_Z26\0"
15522 /* 1906 */ "b26\0"
15523 /* 1910 */ "d26\0"
15524 /* 1914 */ "h26\0"
15525 /* 1918 */ "q26\0"
15526 /* 1922 */ "s26\0"
15527 /* 1926 */ "w26\0"
15528 /* 1930 */ "x26\0"
15529 /* 1934 */ "z26\0"
15530 /* 1938 */ "D3_D4_D5_D6\0"
15531 /* 1950 */ "Q3_Q4_Q5_Q6\0"
15532 /* 1962 */ "Z3_Z4_Z5_Z6\0"
15533 /* 1974 */ "b6\0"
15534 /* 1977 */ "d6\0"
15535 /* 1980 */ "h6\0"
15536 /* 1983 */ "p6\0"
15537 /* 1986 */ "q6\0"
15538 /* 1989 */ "s6\0"
15539 /* 1992 */ "w6\0"
15540 /* 1995 */ "x6\0"
15541 /* 1998 */ "z6\0"
15542 /* 2001 */ "D14_D15_D16_D17\0"
15543 /* 2017 */ "Q14_Q15_Q16_Q17\0"
15544 /* 2033 */ "W16_W17\0"
15545 /* 2041 */ "X10_X11_X12_X13_X14_X15_X16_X17\0"
15546 /* 2073 */ "Z14_Z15_Z16_Z17\0"
15547 /* 2089 */ "b17\0"
15548 /* 2093 */ "d17\0"
15549 /* 2097 */ "h17\0"
15550 /* 2101 */ "q17\0"
15551 /* 2105 */ "s17\0"
15552 /* 2109 */ "w17\0"
15553 /* 2113 */ "x17\0"
15554 /* 2117 */ "z17\0"
15555 /* 2121 */ "D24_D25_D26_D27\0"
15556 /* 2137 */ "Q24_Q25_Q26_Q27\0"
15557 /* 2153 */ "W26_W27\0"
15558 /* 2161 */ "X20_X21_X22_X23_X24_X25_X26_X27\0"
15559 /* 2193 */ "Z24_Z25_Z26_Z27\0"
15560 /* 2209 */ "b27\0"
15561 /* 2213 */ "d27\0"
15562 /* 2217 */ "h27\0"
15563 /* 2221 */ "q27\0"
15564 /* 2225 */ "s27\0"
15565 /* 2229 */ "w27\0"
15566 /* 2233 */ "x27\0"
15567 /* 2237 */ "z27\0"
15568 /* 2241 */ "D4_D5_D6_D7\0"
15569 /* 2253 */ "Q4_Q5_Q6_Q7\0"
15570 /* 2265 */ "W6_W7\0"
15571 /* 2271 */ "X0_X1_X2_X3_X4_X5_X6_X7\0"
15572 /* 2295 */ "Z4_Z5_Z6_Z7\0"
15573 /* 2307 */ "b7\0"
15574 /* 2310 */ "d7\0"
15575 /* 2313 */ "h7\0"
15576 /* 2316 */ "p7\0"
15577 /* 2319 */ "q7\0"
15578 /* 2322 */ "s7\0"
15579 /* 2325 */ "w7\0"
15580 /* 2328 */ "x7\0"
15581 /* 2331 */ "z7\0"
15582 /* 2334 */ "D15_D16_D17_D18\0"
15583 /* 2350 */ "Q15_Q16_Q17_Q18\0"
15584 /* 2366 */ "Z15_Z16_Z17_Z18\0"
15585 /* 2382 */ "b18\0"
15586 /* 2386 */ "d18\0"
15587 /* 2390 */ "h18\0"
15588 /* 2394 */ "q18\0"
15589 /* 2398 */ "s18\0"
15590 /* 2402 */ "w18\0"
15591 /* 2406 */ "x18\0"
15592 /* 2410 */ "z18\0"
15593 /* 2414 */ "D25_D26_D27_D28\0"
15594 /* 2430 */ "Q25_Q26_Q27_Q28\0"
15595 /* 2446 */ "Z25_Z26_Z27_Z28\0"
15596 /* 2462 */ "b28\0"
15597 /* 2466 */ "d28\0"
15598 /* 2470 */ "h28\0"
15599 /* 2474 */ "q28\0"
15600 /* 2478 */ "s28\0"
15601 /* 2482 */ "w28\0"
15602 /* 2486 */ "x28\0"
15603 /* 2490 */ "z28\0"
15604 /* 2494 */ "D5_D6_D7_D8\0"
15605 /* 2506 */ "Q5_Q6_Q7_Q8\0"
15606 /* 2518 */ "Z5_Z6_Z7_Z8\0"
15607 /* 2530 */ "b8\0"
15608 /* 2533 */ "d8\0"
15609 /* 2536 */ "h8\0"
15610 /* 2539 */ "p8\0"
15611 /* 2542 */ "q8\0"
15612 /* 2545 */ "s8\0"
15613 /* 2548 */ "w8\0"
15614 /* 2551 */ "x8\0"
15615 /* 2554 */ "z8\0"
15616 /* 2557 */ "D16_D17_D18_D19\0"
15617 /* 2573 */ "Q16_Q17_Q18_Q19\0"
15618 /* 2589 */ "W18_W19\0"
15619 /* 2597 */ "X12_X13_X14_X15_X16_X17_X18_X19\0"
15620 /* 2629 */ "Z16_Z17_Z18_Z19\0"
15621 /* 2645 */ "b19\0"
15622 /* 2649 */ "d19\0"
15623 /* 2653 */ "h19\0"
15624 /* 2657 */ "q19\0"
15625 /* 2661 */ "s19\0"
15626 /* 2665 */ "w19\0"
15627 /* 2669 */ "x19\0"
15628 /* 2673 */ "z19\0"
15629 /* 2677 */ "D26_D27_D28_D29\0"
15630 /* 2693 */ "Q26_Q27_Q28_Q29\0"
15631 /* 2709 */ "W28_W29\0"
15632 /* 2717 */ "Z26_Z27_Z28_Z29\0"
15633 /* 2733 */ "b29\0"
15634 /* 2737 */ "d29\0"
15635 /* 2741 */ "h29\0"
15636 /* 2745 */ "q29\0"
15637 /* 2749 */ "s29\0"
15638 /* 2753 */ "w29\0"
15639 /* 2757 */ "x29\0"
15640 /* 2761 */ "z29\0"
15641 /* 2765 */ "D6_D7_D8_D9\0"
15642 /* 2777 */ "Q6_Q7_Q8_Q9\0"
15643 /* 2789 */ "W8_W9\0"
15644 /* 2795 */ "X2_X3_X4_X5_X6_X7_X8_X9\0"
15645 /* 2819 */ "Z6_Z7_Z8_Z9\0"
15646 /* 2831 */ "b9\0"
15647 /* 2834 */ "d9\0"
15648 /* 2837 */ "h9\0"
15649 /* 2840 */ "p9\0"
15650 /* 2843 */ "q9\0"
15651 /* 2846 */ "s9\0"
15652 /* 2849 */ "w9\0"
15653 /* 2852 */ "x9\0"
15654 /* 2855 */ "z9\0"
15655 /* 2858 */ "X22_X23_X24_X25_X26_X27_X28_FP\0"
15656 /* 2889 */ "W30_WZR\0"
15657 /* 2897 */ "LR_XZR\0"
15658 /* 2904 */ "vg\0"
15659 /* 2907 */ "z10_hi\0"
15660 /* 2914 */ "z20_hi\0"
15661 /* 2921 */ "z30_hi\0"
15662 /* 2928 */ "z0_hi\0"
15663 /* 2934 */ "z11_hi\0"
15664 /* 2941 */ "z21_hi\0"
15665 /* 2948 */ "z31_hi\0"
15666 /* 2955 */ "z1_hi\0"
15667 /* 2961 */ "z12_hi\0"
15668 /* 2968 */ "z22_hi\0"
15669 /* 2975 */ "z2_hi\0"
15670 /* 2981 */ "z13_hi\0"
15671 /* 2988 */ "z23_hi\0"
15672 /* 2995 */ "z3_hi\0"
15673 /* 3001 */ "z14_hi\0"
15674 /* 3008 */ "z24_hi\0"
15675 /* 3015 */ "z4_hi\0"
15676 /* 3021 */ "z15_hi\0"
15677 /* 3028 */ "z25_hi\0"
15678 /* 3035 */ "z5_hi\0"
15679 /* 3041 */ "z16_hi\0"
15680 /* 3048 */ "z26_hi\0"
15681 /* 3055 */ "z6_hi\0"
15682 /* 3061 */ "z17_hi\0"
15683 /* 3068 */ "z27_hi\0"
15684 /* 3075 */ "z7_hi\0"
15685 /* 3081 */ "z18_hi\0"
15686 /* 3088 */ "z28_hi\0"
15687 /* 3095 */ "z8_hi\0"
15688 /* 3101 */ "z19_hi\0"
15689 /* 3108 */ "z29_hi\0"
15690 /* 3115 */ "z9_hi\0"
15691 /* 3121 */ "wsp\0"
15692 /* 3125 */ "ffr\0"
15693 /* 3129 */ "wzr\0"
15694 /* 3133 */ "xzr\0"
15695 /* 3137 */ "nzcv\0"
15696};
15697#ifdef __GNUC__
15698#pragma GCC diagnostic pop
15699#endif
15700
15701 static const uint16_t RegAsmOffsetNoRegAltName[] = {
15702 3125, 2757, 227, 3137, 3122, 2904, 3121, 3129, 3133, 280, 665, 892, 1207, 1434,
15703 1751, 1974, 2307, 2530, 2831, 39, 383, 737, 1003, 1282, 1547, 1826, 2089, 2382,
15704 2645, 123, 507, 821, 1127, 1366, 1671, 1906, 2209, 2462, 2733, 203, 587, 283,
15705 668, 895, 1210, 1437, 1754, 1977, 2310, 2533, 2834, 43, 387, 741, 1007, 1286,
15706 1551, 1830, 2093, 2386, 2649, 127, 511, 825, 1131, 1370, 1675, 1910, 2213, 2466,
15707 2737, 207, 591, 286, 671, 898, 1213, 1440, 1757, 1980, 2313, 2536, 2837, 47,
15708 391, 745, 1011, 1290, 1555, 1834, 2097, 2390, 2653, 131, 515, 829, 1135, 1374,
15709 1679, 1914, 2217, 2470, 2741, 211, 595, 289, 674, 901, 1216, 1443, 1760, 1983,
15710 2316, 2539, 2840, 51, 395, 749, 1015, 1294, 1559, 292, 677, 904, 1219, 1446,
15711 1763, 1986, 2319, 2542, 2843, 55, 399, 753, 1019, 1298, 1563, 1838, 2101, 2394,
15712 2657, 135, 519, 833, 1139, 1378, 1683, 1918, 2221, 2474, 2745, 215, 599, 295,
15713 680, 907, 1222, 1449, 1766, 1989, 2322, 2545, 2846, 59, 403, 757, 1023, 1302,
15714 1567, 1842, 2105, 2398, 2661, 139, 523, 837, 1143, 1382, 1687, 1922, 2225, 2478,
15715 2749, 219, 603, 298, 683, 910, 1225, 1452, 1769, 1992, 2325, 2548, 2849, 63,
15716 407, 761, 1027, 1306, 1571, 1846, 2109, 2402, 2665, 143, 527, 841, 1147, 1386,
15717 1691, 1926, 2229, 2482, 2753, 223, 301, 686, 913, 1228, 1455, 1772, 1995, 2328,
15718 2551, 2852, 67, 411, 765, 1031, 1310, 1575, 1850, 2113, 2406, 2669, 147, 531,
15719 845, 1151, 1390, 1695, 1930, 2233, 2486, 304, 689, 916, 1231, 1458, 1775, 1998,
15720 2331, 2554, 2855, 71, 415, 769, 1035, 1314, 1579, 1854, 2117, 2410, 2673, 151,
15721 535, 849, 1155, 1394, 1699, 1934, 2237, 2490, 2761, 231, 607, 2928, 2955, 2975,
15722 2995, 3015, 3035, 3055, 3075, 3095, 3115, 2907, 2934, 2961, 2981, 3001, 3021, 3041,
15723 3061, 3081, 3101, 2914, 2941, 2968, 2988, 3008, 3028, 3048, 3068, 3088, 3108, 2921,
15724 2948, 619, 860, 1165, 1404, 1709, 1944, 2247, 2500, 2771, 6, 313, 699, 927,
15725 1242, 1469, 1786, 2009, 2342, 2565, 83, 427, 781, 1047, 1326, 1591, 1866, 2129,
15726 2422, 2685, 163, 547, 243, 1159, 1398, 1703, 1938, 2241, 2494, 2765, 0, 307,
15727 692, 919, 1234, 1461, 1778, 2001, 2334, 2557, 75, 419, 773, 1039, 1318, 1583,
15728 1858, 2121, 2414, 2677, 155, 539, 235, 611, 853, 857, 1162, 1401, 1706, 1941,
15729 2244, 2497, 2768, 3, 310, 695, 923, 1238, 1465, 1782, 2005, 2338, 2561, 79,
15730 423, 777, 1043, 1322, 1587, 1862, 2125, 2418, 2681, 159, 543, 239, 615, 633,
15731 873, 1177, 1416, 1721, 1956, 2259, 2512, 2783, 19, 327, 714, 943, 1258, 1485,
15732 1802, 2025, 2358, 2581, 99, 443, 797, 1063, 1342, 1607, 1882, 2145, 2438, 2701,
15733 179, 563, 258, 1171, 1410, 1715, 1950, 2253, 2506, 2777, 13, 321, 707, 935,
15734 1250, 1477, 1794, 2017, 2350, 2573, 91, 435, 789, 1055, 1334, 1599, 1874, 2137,
15735 2430, 2693, 171, 555, 250, 625, 866, 870, 1174, 1413, 1718, 1953, 2256, 2509,
15736 2780, 16, 324, 710, 939, 1254, 1481, 1798, 2021, 2354, 2577, 95, 439, 793,
15737 1059, 1338, 1603, 1878, 2141, 2434, 2697, 175, 559, 254, 629, 2858, 2271, 2795,
15738 343, 959, 1501, 2041, 2597, 459, 1079, 1623, 2161, 2889, 639, 1183, 1727, 2265,
15739 2789, 335, 951, 1493, 2033, 2589, 451, 1071, 1615, 2153, 2709, 2897, 2882, 645,
15740 1189, 1733, 2289, 2813, 361, 979, 1523, 2065, 2621, 483, 1103, 1647, 2185, 659,
15741 886, 1201, 1428, 1745, 1968, 2301, 2524, 2825, 32, 375, 729, 995, 1274, 1539,
15742 1818, 2081, 2374, 2637, 115, 499, 813, 1119, 1358, 1663, 1898, 2201, 2454, 2725,
15743 195, 579, 273, 1195, 1422, 1739, 1962, 2295, 2518, 2819, 26, 369, 722, 987,
15744 1266, 1531, 1810, 2073, 2366, 2629, 107, 491, 805, 1111, 1350, 1655, 1890, 2193,
15745 2446, 2717, 187, 571, 265, 651, 879, 883, 1198, 1425, 1742, 1965, 2298, 2521,
15746 2822, 29, 372, 725, 991, 1270, 1535, 1814, 2077, 2370, 2633, 111, 495, 809,
15747 1115, 1354, 1659, 1894, 2197, 2450, 2721, 191, 575, 269, 655,
15748 };
15749
15750
15751#ifdef __GNUC__
15752#pragma GCC diagnostic push
15753#pragma GCC diagnostic ignored "-Woverlength-strings"
15754#endif
15755 static const char AsmStrsvlist1[] = {
15756 /* 0 */ "\0"
15757};
15758#ifdef __GNUC__
15759#pragma GCC diagnostic pop
15760#endif
15761
15762 static const uint8_t RegAsmOffsetvlist1[] = {
15763 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
15764 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
15765 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
15766 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
15767 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
15768 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
15769 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
15770 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
15771 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
15772 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
15773 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
15774 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
15775 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
15776 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
15777 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
15778 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
15779 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
15780 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
15781 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
15782 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
15783 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
15784 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
15785 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
15786 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
15787 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
15788 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
15789 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
15790 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
15791 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
15792 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
15793 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
15794 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
15795 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
15796 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
15797 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
15798 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
15799 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
15800 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
15801 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
15802 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
15803 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
15804 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
15805 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
15806 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
15807 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
15808 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
15809 };
15810
15811
15812#ifdef __GNUC__
15813#pragma GCC diagnostic push
15814#pragma GCC diagnostic ignored "-Woverlength-strings"
15815#endif
15816 static const char AsmStrsvreg[] = {
15817 /* 0 */ "v10\0"
15818 /* 4 */ "v20\0"
15819 /* 8 */ "v30\0"
15820 /* 12 */ "v0\0"
15821 /* 15 */ "v11\0"
15822 /* 19 */ "v21\0"
15823 /* 23 */ "v31\0"
15824 /* 27 */ "v1\0"
15825 /* 30 */ "v12\0"
15826 /* 34 */ "v22\0"
15827 /* 38 */ "v2\0"
15828 /* 41 */ "v13\0"
15829 /* 45 */ "v23\0"
15830 /* 49 */ "v3\0"
15831 /* 52 */ "v14\0"
15832 /* 56 */ "v24\0"
15833 /* 60 */ "v4\0"
15834 /* 63 */ "v15\0"
15835 /* 67 */ "v25\0"
15836 /* 71 */ "v5\0"
15837 /* 74 */ "v16\0"
15838 /* 78 */ "v26\0"
15839 /* 82 */ "v6\0"
15840 /* 85 */ "v17\0"
15841 /* 89 */ "v27\0"
15842 /* 93 */ "v7\0"
15843 /* 96 */ "v18\0"
15844 /* 100 */ "v28\0"
15845 /* 104 */ "v8\0"
15846 /* 107 */ "v19\0"
15847 /* 111 */ "v29\0"
15848 /* 115 */ "v9\0"
15849};
15850#ifdef __GNUC__
15851#pragma GCC diagnostic pop
15852#endif
15853
15854 static const uint8_t RegAsmOffsetvreg[] = {
15855 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
15856 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
15857 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 12,
15858 27, 38, 49, 60, 71, 82, 93, 104, 115, 0, 15, 30, 41, 52,
15859 63, 74, 85, 96, 107, 4, 19, 34, 45, 56, 67, 78, 89, 100,
15860 111, 8, 23, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
15861 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
15862 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
15863 3, 3, 3, 3, 3, 3, 3, 3, 3, 12, 27, 38, 49, 60,
15864 71, 82, 93, 104, 115, 0, 15, 30, 41, 52, 63, 74, 85, 96,
15865 107, 4, 19, 34, 45, 56, 67, 78, 89, 100, 111, 8, 23, 3,
15866 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
15867 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
15868 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
15869 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
15870 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
15871 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
15872 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
15873 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
15874 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
15875 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
15876 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
15877 3, 12, 27, 38, 49, 60, 71, 82, 93, 104, 115, 0, 15, 30,
15878 41, 52, 63, 74, 85, 96, 107, 4, 19, 34, 45, 56, 67, 78,
15879 89, 100, 111, 8, 23, 12, 27, 38, 49, 60, 71, 82, 93, 104,
15880 115, 0, 15, 30, 41, 52, 63, 74, 85, 96, 107, 4, 19, 34,
15881 45, 56, 67, 78, 89, 100, 111, 8, 23, 12, 27, 38, 49, 60,
15882 71, 82, 93, 104, 115, 0, 15, 30, 41, 52, 63, 74, 85, 96,
15883 107, 4, 19, 34, 45, 56, 67, 78, 89, 100, 111, 8, 23, 12,
15884 27, 38, 49, 60, 71, 82, 93, 104, 115, 0, 15, 30, 41, 52,
15885 63, 74, 85, 96, 107, 4, 19, 34, 45, 56, 67, 78, 89, 100,
15886 111, 8, 23, 12, 27, 38, 49, 60, 71, 82, 93, 104, 115, 0,
15887 15, 30, 41, 52, 63, 74, 85, 96, 107, 4, 19, 34, 45, 56,
15888 67, 78, 89, 100, 111, 8, 23, 12, 27, 38, 49, 60, 71, 82,
15889 93, 104, 115, 0, 15, 30, 41, 52, 63, 74, 85, 96, 107, 4,
15890 19, 34, 45, 56, 67, 78, 89, 100, 111, 8, 23, 3, 3, 3,
15891 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
15892 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
15893 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
15894 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
15895 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
15896 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
15897 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
15898 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
15899 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
15900 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
15901 };
15902
15903 switch(AltIdx) {
15904 default: llvm_unreachable("Invalid register alt name index!");
15905 case AArch64::NoRegAltName:
15906 assert(*(AsmStrsNoRegAltName+RegAsmOffsetNoRegAltName[RegNo-1]) &&
15907 "Invalid alt name index for register!");
15908 return AsmStrsNoRegAltName+RegAsmOffsetNoRegAltName[RegNo-1];
15909 case AArch64::vlist1:
15910 assert(*(AsmStrsvlist1+RegAsmOffsetvlist1[RegNo-1]) &&
15911 "Invalid alt name index for register!");
15912 return AsmStrsvlist1+RegAsmOffsetvlist1[RegNo-1];
15913 case AArch64::vreg:
15914 assert(*(AsmStrsvreg+RegAsmOffsetvreg[RegNo-1]) &&
15915 "Invalid alt name index for register!");
15916 return AsmStrsvreg+RegAsmOffsetvreg[RegNo-1];
15917 }
15918}
15919
15920#ifdef PRINT_ALIAS_INSTR
15921#undef PRINT_ALIAS_INSTR
15922
15923static bool AArch64InstPrinterValidateMCOperand(const MCOperand &MCOp,
15924 const MCSubtargetInfo &STI,
15925 unsigned PredicateIndex);
15926bool AArch64InstPrinter::printAliasInstr(const MCInst *MI, uint64_t Address, const MCSubtargetInfo &STI, raw_ostream &OS) {
15927 static const PatternsForOpcode OpToPatterns[] = {
15928 {AArch64::ADDSWri, 0, 1 },
15929 {AArch64::ADDSWrs, 1, 3 },
15930 {AArch64::ADDSWrx, 4, 3 },
15931 {AArch64::ADDSXri, 7, 1 },
15932 {AArch64::ADDSXrs, 8, 3 },
15933 {AArch64::ADDSXrx, 11, 1 },
15934 {AArch64::ADDSXrx64, 12, 3 },
15935 {AArch64::ADDWri, 15, 2 },
15936 {AArch64::ADDWrs, 17, 1 },
15937 {AArch64::ADDWrx, 18, 2 },
15938 {AArch64::ADDXri, 20, 2 },
15939 {AArch64::ADDXrs, 22, 1 },
15940 {AArch64::ADDXrx64, 23, 2 },
15941 {AArch64::ANDSWri, 25, 1 },
15942 {AArch64::ANDSWrs, 26, 3 },
15943 {AArch64::ANDSXri, 29, 1 },
15944 {AArch64::ANDSXrs, 30, 3 },
15945 {AArch64::ANDS_PPzPP, 33, 1 },
15946 {AArch64::ANDWrs, 34, 1 },
15947 {AArch64::ANDXrs, 35, 1 },
15948 {AArch64::AND_PPzPP, 36, 1 },
15949 {AArch64::AND_ZI, 37, 3 },
15950 {AArch64::AUTIA1716, 40, 1 },
15951 {AArch64::AUTIASP, 41, 1 },
15952 {AArch64::AUTIAZ, 42, 1 },
15953 {AArch64::AUTIB1716, 43, 1 },
15954 {AArch64::AUTIBSP, 44, 1 },
15955 {AArch64::AUTIBZ, 45, 1 },
15956 {AArch64::BICSWrs, 46, 1 },
15957 {AArch64::BICSXrs, 47, 1 },
15958 {AArch64::BICWrs, 48, 1 },
15959 {AArch64::BICXrs, 49, 1 },
15960 {AArch64::CLREX, 50, 1 },
15961 {AArch64::CNTB_XPiI, 51, 2 },
15962 {AArch64::CNTD_XPiI, 53, 2 },
15963 {AArch64::CNTH_XPiI, 55, 2 },
15964 {AArch64::CNTW_XPiI, 57, 2 },
15965 {AArch64::CPY_ZPmI_B, 59, 1 },
15966 {AArch64::CPY_ZPmI_D, 60, 1 },
15967 {AArch64::CPY_ZPmI_H, 61, 1 },
15968 {AArch64::CPY_ZPmI_S, 62, 1 },
15969 {AArch64::CPY_ZPmR_B, 63, 1 },
15970 {AArch64::CPY_ZPmR_D, 64, 1 },
15971 {AArch64::CPY_ZPmR_H, 65, 1 },
15972 {AArch64::CPY_ZPmR_S, 66, 1 },
15973 {AArch64::CPY_ZPmV_B, 67, 1 },
15974 {AArch64::CPY_ZPmV_D, 68, 1 },
15975 {AArch64::CPY_ZPmV_H, 69, 1 },
15976 {AArch64::CPY_ZPmV_S, 70, 1 },
15977 {AArch64::CPY_ZPzI_B, 71, 1 },
15978 {AArch64::CPY_ZPzI_D, 72, 1 },
15979 {AArch64::CPY_ZPzI_H, 73, 1 },
15980 {AArch64::CPY_ZPzI_S, 74, 1 },
15981 {AArch64::CSINCWr, 75, 2 },
15982 {AArch64::CSINCXr, 77, 2 },
15983 {AArch64::CSINVWr, 79, 2 },
15984 {AArch64::CSINVXr, 81, 2 },
15985 {AArch64::CSNEGWr, 83, 1 },
15986 {AArch64::CSNEGXr, 84, 1 },
15987 {AArch64::DCPS1, 85, 1 },
15988 {AArch64::DCPS2, 86, 1 },
15989 {AArch64::DCPS3, 87, 1 },
15990 {AArch64::DECB_XPiI, 88, 2 },
15991 {AArch64::DECD_XPiI, 90, 2 },
15992 {AArch64::DECD_ZPiI, 92, 2 },
15993 {AArch64::DECH_XPiI, 94, 2 },
15994 {AArch64::DECH_ZPiI, 96, 2 },
15995 {AArch64::DECW_XPiI, 98, 2 },
15996 {AArch64::DECW_ZPiI, 100, 2 },
15997 {AArch64::DSB, 102, 2 },
15998 {AArch64::DUPM_ZI, 104, 6 },
15999 {AArch64::DUP_ZI_B, 110, 1 },
16000 {AArch64::DUP_ZI_D, 111, 2 },
16001 {AArch64::DUP_ZI_H, 113, 2 },
16002 {AArch64::DUP_ZI_S, 115, 2 },
16003 {AArch64::DUP_ZR_B, 117, 1 },
16004 {AArch64::DUP_ZR_D, 118, 1 },
16005 {AArch64::DUP_ZR_H, 119, 1 },
16006 {AArch64::DUP_ZR_S, 120, 1 },
16007 {AArch64::DUP_ZZI_B, 121, 2 },
16008 {AArch64::DUP_ZZI_D, 123, 2 },
16009 {AArch64::DUP_ZZI_H, 125, 2 },
16010 {AArch64::DUP_ZZI_Q, 127, 2 },
16011 {AArch64::DUP_ZZI_S, 129, 2 },
16012 {AArch64::EONWrs, 131, 1 },
16013 {AArch64::EONXrs, 132, 1 },
16014 {AArch64::EORS_PPzPP, 133, 1 },
16015 {AArch64::EORWrs, 134, 1 },
16016 {AArch64::EORXrs, 135, 1 },
16017 {AArch64::EOR_PPzPP, 136, 1 },
16018 {AArch64::EOR_ZI, 137, 3 },
16019 {AArch64::EXTRWrri, 140, 1 },
16020 {AArch64::EXTRXrri, 141, 1 },
16021 {AArch64::FCPY_ZPmI_D, 142, 1 },
16022 {AArch64::FCPY_ZPmI_H, 143, 1 },
16023 {AArch64::FCPY_ZPmI_S, 144, 1 },
16024 {AArch64::FDUP_ZI_D, 145, 1 },
16025 {AArch64::FDUP_ZI_H, 146, 1 },
16026 {AArch64::FDUP_ZI_S, 147, 1 },
16027 {AArch64::GLD1B_D_IMM_REAL, 148, 1 },
16028 {AArch64::GLD1B_S_IMM_REAL, 149, 1 },
16029 {AArch64::GLD1D_IMM_REAL, 150, 1 },
16030 {AArch64::GLD1H_D_IMM_REAL, 151, 1 },
16031 {AArch64::GLD1H_S_IMM_REAL, 152, 1 },
16032 {AArch64::GLD1SB_D_IMM_REAL, 153, 1 },
16033 {AArch64::GLD1SB_S_IMM_REAL, 154, 1 },
16034 {AArch64::GLD1SH_D_IMM_REAL, 155, 1 },
16035 {AArch64::GLD1SH_S_IMM_REAL, 156, 1 },
16036 {AArch64::GLD1SW_D_IMM_REAL, 157, 1 },
16037 {AArch64::GLD1W_D_IMM_REAL, 158, 1 },
16038 {AArch64::GLD1W_IMM_REAL, 159, 1 },
16039 {AArch64::GLDFF1B_D_IMM_REAL, 160, 1 },
16040 {AArch64::GLDFF1B_S_IMM_REAL, 161, 1 },
16041 {AArch64::GLDFF1D_IMM_REAL, 162, 1 },
16042 {AArch64::GLDFF1H_D_IMM_REAL, 163, 1 },
16043 {AArch64::GLDFF1H_S_IMM_REAL, 164, 1 },
16044 {AArch64::GLDFF1SB_D_IMM_REAL, 165, 1 },
16045 {AArch64::GLDFF1SB_S_IMM_REAL, 166, 1 },
16046 {AArch64::GLDFF1SH_D_IMM_REAL, 167, 1 },
16047 {AArch64::GLDFF1SH_S_IMM_REAL, 168, 1 },
16048 {AArch64::GLDFF1SW_D_IMM_REAL, 169, 1 },
16049 {AArch64::GLDFF1W_D_IMM_REAL, 170, 1 },
16050 {AArch64::GLDFF1W_IMM_REAL, 171, 1 },
16051 {AArch64::HINT, 172, 12 },
16052 {AArch64::INCB_XPiI, 184, 2 },
16053 {AArch64::INCD_XPiI, 186, 2 },
16054 {AArch64::INCD_ZPiI, 188, 2 },
16055 {AArch64::INCH_XPiI, 190, 2 },
16056 {AArch64::INCH_ZPiI, 192, 2 },
16057 {AArch64::INCW_XPiI, 194, 2 },
16058 {AArch64::INCW_ZPiI, 196, 2 },
16059 {AArch64::INSvi16gpr, 198, 1 },
16060 {AArch64::INSvi16lane, 199, 1 },
16061 {AArch64::INSvi32gpr, 200, 1 },
16062 {AArch64::INSvi32lane, 201, 1 },
16063 {AArch64::INSvi64gpr, 202, 1 },
16064 {AArch64::INSvi64lane, 203, 1 },
16065 {AArch64::INSvi8gpr, 204, 1 },
16066 {AArch64::INSvi8lane, 205, 1 },
16067 {AArch64::IRG, 206, 1 },
16068 {AArch64::ISB, 207, 1 },
16069 {AArch64::LD1B_D_IMM_REAL, 208, 1 },
16070 {AArch64::LD1B_H_IMM_REAL, 209, 1 },
16071 {AArch64::LD1B_IMM_REAL, 210, 1 },
16072 {AArch64::LD1B_S_IMM_REAL, 211, 1 },
16073 {AArch64::LD1D_IMM_REAL, 212, 1 },
16074 {AArch64::LD1Fourv16b_POST, 213, 1 },
16075 {AArch64::LD1Fourv1d_POST, 214, 1 },
16076 {AArch64::LD1Fourv2d_POST, 215, 1 },
16077 {AArch64::LD1Fourv2s_POST, 216, 1 },
16078 {AArch64::LD1Fourv4h_POST, 217, 1 },
16079 {AArch64::LD1Fourv4s_POST, 218, 1 },
16080 {AArch64::LD1Fourv8b_POST, 219, 1 },
16081 {AArch64::LD1Fourv8h_POST, 220, 1 },
16082 {AArch64::LD1H_D_IMM_REAL, 221, 1 },
16083 {AArch64::LD1H_IMM_REAL, 222, 1 },
16084 {AArch64::LD1H_S_IMM_REAL, 223, 1 },
16085 {AArch64::LD1Onev16b_POST, 224, 1 },
16086 {AArch64::LD1Onev1d_POST, 225, 1 },
16087 {AArch64::LD1Onev2d_POST, 226, 1 },
16088 {AArch64::LD1Onev2s_POST, 227, 1 },
16089 {AArch64::LD1Onev4h_POST, 228, 1 },
16090 {AArch64::LD1Onev4s_POST, 229, 1 },
16091 {AArch64::LD1Onev8b_POST, 230, 1 },
16092 {AArch64::LD1Onev8h_POST, 231, 1 },
16093 {AArch64::LD1RB_D_IMM, 232, 1 },
16094 {AArch64::LD1RB_H_IMM, 233, 1 },
16095 {AArch64::LD1RB_IMM, 234, 1 },
16096 {AArch64::LD1RB_S_IMM, 235, 1 },
16097 {AArch64::LD1RD_IMM, 236, 1 },
16098 {AArch64::LD1RH_D_IMM, 237, 1 },
16099 {AArch64::LD1RH_IMM, 238, 1 },
16100 {AArch64::LD1RH_S_IMM, 239, 1 },
16101 {AArch64::LD1RO_B_IMM, 240, 1 },
16102 {AArch64::LD1RO_D_IMM, 241, 1 },
16103 {AArch64::LD1RO_H_IMM, 242, 1 },
16104 {AArch64::LD1RO_W_IMM, 243, 1 },
16105 {AArch64::LD1RQ_B_IMM, 244, 1 },
16106 {AArch64::LD1RQ_D_IMM, 245, 1 },
16107 {AArch64::LD1RQ_H_IMM, 246, 1 },
16108 {AArch64::LD1RQ_W_IMM, 247, 1 },
16109 {AArch64::LD1RSB_D_IMM, 248, 1 },
16110 {AArch64::LD1RSB_H_IMM, 249, 1 },
16111 {AArch64::LD1RSB_S_IMM, 250, 1 },
16112 {AArch64::LD1RSH_D_IMM, 251, 1 },
16113 {AArch64::LD1RSH_S_IMM, 252, 1 },
16114 {AArch64::LD1RSW_IMM, 253, 1 },
16115 {AArch64::LD1RW_D_IMM, 254, 1 },
16116 {AArch64::LD1RW_IMM, 255, 1 },
16117 {AArch64::LD1Rv16b_POST, 256, 1 },
16118 {AArch64::LD1Rv1d_POST, 257, 1 },
16119 {AArch64::LD1Rv2d_POST, 258, 1 },
16120 {AArch64::LD1Rv2s_POST, 259, 1 },
16121 {AArch64::LD1Rv4h_POST, 260, 1 },
16122 {AArch64::LD1Rv4s_POST, 261, 1 },
16123 {AArch64::LD1Rv8b_POST, 262, 1 },
16124 {AArch64::LD1Rv8h_POST, 263, 1 },
16125 {AArch64::LD1SB_D_IMM_REAL, 264, 1 },
16126 {AArch64::LD1SB_H_IMM_REAL, 265, 1 },
16127 {AArch64::LD1SB_S_IMM_REAL, 266, 1 },
16128 {AArch64::LD1SH_D_IMM_REAL, 267, 1 },
16129 {AArch64::LD1SH_S_IMM_REAL, 268, 1 },
16130 {AArch64::LD1SW_D_IMM_REAL, 269, 1 },
16131 {AArch64::LD1Threev16b_POST, 270, 1 },
16132 {AArch64::LD1Threev1d_POST, 271, 1 },
16133 {AArch64::LD1Threev2d_POST, 272, 1 },
16134 {AArch64::LD1Threev2s_POST, 273, 1 },
16135 {AArch64::LD1Threev4h_POST, 274, 1 },
16136 {AArch64::LD1Threev4s_POST, 275, 1 },
16137 {AArch64::LD1Threev8b_POST, 276, 1 },
16138 {AArch64::LD1Threev8h_POST, 277, 1 },
16139 {AArch64::LD1Twov16b_POST, 278, 1 },
16140 {AArch64::LD1Twov1d_POST, 279, 1 },
16141 {AArch64::LD1Twov2d_POST, 280, 1 },
16142 {AArch64::LD1Twov2s_POST, 281, 1 },
16143 {AArch64::LD1Twov4h_POST, 282, 1 },
16144 {AArch64::LD1Twov4s_POST, 283, 1 },
16145 {AArch64::LD1Twov8b_POST, 284, 1 },
16146 {AArch64::LD1Twov8h_POST, 285, 1 },
16147 {AArch64::LD1W_D_IMM_REAL, 286, 1 },
16148 {AArch64::LD1W_IMM_REAL, 287, 1 },
16149 {AArch64::LD1i16_POST, 288, 1 },
16150 {AArch64::LD1i32_POST, 289, 1 },
16151 {AArch64::LD1i64_POST, 290, 1 },
16152 {AArch64::LD1i8_POST, 291, 1 },
16153 {AArch64::LD2B_IMM, 292, 1 },
16154 {AArch64::LD2D_IMM, 293, 1 },
16155 {AArch64::LD2H_IMM, 294, 1 },
16156 {AArch64::LD2Rv16b_POST, 295, 1 },
16157 {AArch64::LD2Rv1d_POST, 296, 1 },
16158 {AArch64::LD2Rv2d_POST, 297, 1 },
16159 {AArch64::LD2Rv2s_POST, 298, 1 },
16160 {AArch64::LD2Rv4h_POST, 299, 1 },
16161 {AArch64::LD2Rv4s_POST, 300, 1 },
16162 {AArch64::LD2Rv8b_POST, 301, 1 },
16163 {AArch64::LD2Rv8h_POST, 302, 1 },
16164 {AArch64::LD2Twov16b_POST, 303, 1 },
16165 {AArch64::LD2Twov2d_POST, 304, 1 },
16166 {AArch64::LD2Twov2s_POST, 305, 1 },
16167 {AArch64::LD2Twov4h_POST, 306, 1 },
16168 {AArch64::LD2Twov4s_POST, 307, 1 },
16169 {AArch64::LD2Twov8b_POST, 308, 1 },
16170 {AArch64::LD2Twov8h_POST, 309, 1 },
16171 {AArch64::LD2W_IMM, 310, 1 },
16172 {AArch64::LD2i16_POST, 311, 1 },
16173 {AArch64::LD2i32_POST, 312, 1 },
16174 {AArch64::LD2i64_POST, 313, 1 },
16175 {AArch64::LD2i8_POST, 314, 1 },
16176 {AArch64::LD3B_IMM, 315, 1 },
16177 {AArch64::LD3D_IMM, 316, 1 },
16178 {AArch64::LD3H_IMM, 317, 1 },
16179 {AArch64::LD3Rv16b_POST, 318, 1 },
16180 {AArch64::LD3Rv1d_POST, 319, 1 },
16181 {AArch64::LD3Rv2d_POST, 320, 1 },
16182 {AArch64::LD3Rv2s_POST, 321, 1 },
16183 {AArch64::LD3Rv4h_POST, 322, 1 },
16184 {AArch64::LD3Rv4s_POST, 323, 1 },
16185 {AArch64::LD3Rv8b_POST, 324, 1 },
16186 {AArch64::LD3Rv8h_POST, 325, 1 },
16187 {AArch64::LD3Threev16b_POST, 326, 1 },
16188 {AArch64::LD3Threev2d_POST, 327, 1 },
16189 {AArch64::LD3Threev2s_POST, 328, 1 },
16190 {AArch64::LD3Threev4h_POST, 329, 1 },
16191 {AArch64::LD3Threev4s_POST, 330, 1 },
16192 {AArch64::LD3Threev8b_POST, 331, 1 },
16193 {AArch64::LD3Threev8h_POST, 332, 1 },
16194 {AArch64::LD3W_IMM, 333, 1 },
16195 {AArch64::LD3i16_POST, 334, 1 },
16196 {AArch64::LD3i32_POST, 335, 1 },
16197 {AArch64::LD3i64_POST, 336, 1 },
16198 {AArch64::LD3i8_POST, 337, 1 },
16199 {AArch64::LD4B_IMM, 338, 1 },
16200 {AArch64::LD4D_IMM, 339, 1 },
16201 {AArch64::LD4Fourv16b_POST, 340, 1 },
16202 {AArch64::LD4Fourv2d_POST, 341, 1 },
16203 {AArch64::LD4Fourv2s_POST, 342, 1 },
16204 {AArch64::LD4Fourv4h_POST, 343, 1 },
16205 {AArch64::LD4Fourv4s_POST, 344, 1 },
16206 {AArch64::LD4Fourv8b_POST, 345, 1 },
16207 {AArch64::LD4Fourv8h_POST, 346, 1 },
16208 {AArch64::LD4H_IMM, 347, 1 },
16209 {AArch64::LD4Rv16b_POST, 348, 1 },
16210 {AArch64::LD4Rv1d_POST, 349, 1 },
16211 {AArch64::LD4Rv2d_POST, 350, 1 },
16212 {AArch64::LD4Rv2s_POST, 351, 1 },
16213 {AArch64::LD4Rv4h_POST, 352, 1 },
16214 {AArch64::LD4Rv4s_POST, 353, 1 },
16215 {AArch64::LD4Rv8b_POST, 354, 1 },
16216 {AArch64::LD4Rv8h_POST, 355, 1 },
16217 {AArch64::LD4W_IMM, 356, 1 },
16218 {AArch64::LD4i16_POST, 357, 1 },
16219 {AArch64::LD4i32_POST, 358, 1 },
16220 {AArch64::LD4i64_POST, 359, 1 },
16221 {AArch64::LD4i8_POST, 360, 1 },
16222 {AArch64::LDADDB, 361, 1 },
16223 {AArch64::LDADDH, 362, 1 },
16224 {AArch64::LDADDLB, 363, 1 },
16225 {AArch64::LDADDLH, 364, 1 },
16226 {AArch64::LDADDLW, 365, 1 },
16227 {AArch64::LDADDLX, 366, 1 },
16228 {AArch64::LDADDW, 367, 1 },
16229 {AArch64::LDADDX, 368, 1 },
16230 {AArch64::LDAPURBi, 369, 1 },
16231 {AArch64::LDAPURHi, 370, 1 },
16232 {AArch64::LDAPURSBWi, 371, 1 },
16233 {AArch64::LDAPURSBXi, 372, 1 },
16234 {AArch64::LDAPURSHWi, 373, 1 },
16235 {AArch64::LDAPURSHXi, 374, 1 },
16236 {AArch64::LDAPURSWi, 375, 1 },
16237 {AArch64::LDAPURXi, 376, 1 },
16238 {AArch64::LDAPURi, 377, 1 },
16239 {AArch64::LDCLRB, 378, 1 },
16240 {AArch64::LDCLRH, 379, 1 },
16241 {AArch64::LDCLRLB, 380, 1 },
16242 {AArch64::LDCLRLH, 381, 1 },
16243 {AArch64::LDCLRLW, 382, 1 },
16244 {AArch64::LDCLRLX, 383, 1 },
16245 {AArch64::LDCLRW, 384, 1 },
16246 {AArch64::LDCLRX, 385, 1 },
16247 {AArch64::LDEORB, 386, 1 },
16248 {AArch64::LDEORH, 387, 1 },
16249 {AArch64::LDEORLB, 388, 1 },
16250 {AArch64::LDEORLH, 389, 1 },
16251 {AArch64::LDEORLW, 390, 1 },
16252 {AArch64::LDEORLX, 391, 1 },
16253 {AArch64::LDEORW, 392, 1 },
16254 {AArch64::LDEORX, 393, 1 },
16255 {AArch64::LDFF1B_D_REAL, 394, 1 },
16256 {AArch64::LDFF1B_H_REAL, 395, 1 },
16257 {AArch64::LDFF1B_REAL, 396, 1 },
16258 {AArch64::LDFF1B_S_REAL, 397, 1 },
16259 {AArch64::LDFF1D_REAL, 398, 1 },
16260 {AArch64::LDFF1H_D_REAL, 399, 1 },
16261 {AArch64::LDFF1H_REAL, 400, 1 },
16262 {AArch64::LDFF1H_S_REAL, 401, 1 },
16263 {AArch64::LDFF1SB_D_REAL, 402, 1 },
16264 {AArch64::LDFF1SB_H_REAL, 403, 1 },
16265 {AArch64::LDFF1SB_S_REAL, 404, 1 },
16266 {AArch64::LDFF1SH_D_REAL, 405, 1 },
16267 {AArch64::LDFF1SH_S_REAL, 406, 1 },
16268 {AArch64::LDFF1SW_D_REAL, 407, 1 },
16269 {AArch64::LDFF1W_D_REAL, 408, 1 },
16270 {AArch64::LDFF1W_REAL, 409, 1 },
16271 {AArch64::LDG, 410, 1 },
16272 {AArch64::LDNF1B_D_IMM_REAL, 411, 1 },
16273 {AArch64::LDNF1B_H_IMM_REAL, 412, 1 },
16274 {AArch64::LDNF1B_IMM_REAL, 413, 1 },
16275 {AArch64::LDNF1B_S_IMM_REAL, 414, 1 },
16276 {AArch64::LDNF1D_IMM_REAL, 415, 1 },
16277 {AArch64::LDNF1H_D_IMM_REAL, 416, 1 },
16278 {AArch64::LDNF1H_IMM_REAL, 417, 1 },
16279 {AArch64::LDNF1H_S_IMM_REAL, 418, 1 },
16280 {AArch64::LDNF1SB_D_IMM_REAL, 419, 1 },
16281 {AArch64::LDNF1SB_H_IMM_REAL, 420, 1 },
16282 {AArch64::LDNF1SB_S_IMM_REAL, 421, 1 },
16283 {AArch64::LDNF1SH_D_IMM_REAL, 422, 1 },
16284 {AArch64::LDNF1SH_S_IMM_REAL, 423, 1 },
16285 {AArch64::LDNF1SW_D_IMM_REAL, 424, 1 },
16286 {AArch64::LDNF1W_D_IMM_REAL, 425, 1 },
16287 {AArch64::LDNF1W_IMM_REAL, 426, 1 },
16288 {AArch64::LDNPDi, 427, 1 },
16289 {AArch64::LDNPQi, 428, 1 },
16290 {AArch64::LDNPSi, 429, 1 },
16291 {AArch64::LDNPWi, 430, 1 },
16292 {AArch64::LDNPXi, 431, 1 },
16293 {AArch64::LDNT1B_ZRI, 432, 1 },
16294 {AArch64::LDNT1B_ZZR_D_REAL, 433, 1 },
16295 {AArch64::LDNT1B_ZZR_S_REAL, 434, 1 },
16296 {AArch64::LDNT1D_ZRI, 435, 1 },
16297 {AArch64::LDNT1D_ZZR_D_REAL, 436, 1 },
16298 {AArch64::LDNT1H_ZRI, 437, 1 },
16299 {AArch64::LDNT1H_ZZR_D_REAL, 438, 1 },
16300 {AArch64::LDNT1H_ZZR_S_REAL, 439, 1 },
16301 {AArch64::LDNT1SB_ZZR_D_REAL, 440, 1 },
16302 {AArch64::LDNT1SB_ZZR_S_REAL, 441, 1 },
16303 {AArch64::LDNT1SH_ZZR_D_REAL, 442, 1 },
16304 {AArch64::LDNT1SH_ZZR_S_REAL, 443, 1 },
16305 {AArch64::LDNT1SW_ZZR_D_REAL, 444, 1 },
16306 {AArch64::LDNT1W_ZRI, 445, 1 },
16307 {AArch64::LDNT1W_ZZR_D_REAL, 446, 1 },
16308 {AArch64::LDNT1W_ZZR_S_REAL, 447, 1 },
16309 {AArch64::LDPDi, 448, 1 },
16310 {AArch64::LDPQi, 449, 1 },
16311 {AArch64::LDPSWi, 450, 1 },
16312 {AArch64::LDPSi, 451, 1 },
16313 {AArch64::LDPWi, 452, 1 },
16314 {AArch64::LDPXi, 453, 1 },
16315 {AArch64::LDRAAindexed, 454, 1 },
16316 {AArch64::LDRABindexed, 455, 1 },
16317 {AArch64::LDRBBroX, 456, 1 },
16318 {AArch64::LDRBBui, 457, 1 },
16319 {AArch64::LDRBroX, 458, 1 },
16320 {AArch64::LDRBui, 459, 1 },
16321 {AArch64::LDRDroX, 460, 1 },
16322 {AArch64::LDRDui, 461, 1 },
16323 {AArch64::LDRHHroX, 462, 1 },
16324 {AArch64::LDRHHui, 463, 1 },
16325 {AArch64::LDRHroX, 464, 1 },
16326 {AArch64::LDRHui, 465, 1 },
16327 {AArch64::LDRQroX, 466, 1 },
16328 {AArch64::LDRQui, 467, 1 },
16329 {AArch64::LDRSBWroX, 468, 1 },
16330 {AArch64::LDRSBWui, 469, 1 },
16331 {AArch64::LDRSBXroX, 470, 1 },
16332 {AArch64::LDRSBXui, 471, 1 },
16333 {AArch64::LDRSHWroX, 472, 1 },
16334 {AArch64::LDRSHWui, 473, 1 },
16335 {AArch64::LDRSHXroX, 474, 1 },
16336 {AArch64::LDRSHXui, 475, 1 },
16337 {AArch64::LDRSWroX, 476, 1 },
16338 {AArch64::LDRSWui, 477, 1 },
16339 {AArch64::LDRSroX, 478, 1 },
16340 {AArch64::LDRSui, 479, 1 },
16341 {AArch64::LDRWroX, 480, 1 },
16342 {AArch64::LDRWui, 481, 1 },
16343 {AArch64::LDRXroX, 482, 1 },
16344 {AArch64::LDRXui, 483, 1 },
16345 {AArch64::LDR_PXI, 484, 1 },
16346 {AArch64::LDR_ZXI, 485, 1 },
16347 {AArch64::LDSETB, 486, 1 },
16348 {AArch64::LDSETH, 487, 1 },
16349 {AArch64::LDSETLB, 488, 1 },
16350 {AArch64::LDSETLH, 489, 1 },
16351 {AArch64::LDSETLW, 490, 1 },
16352 {AArch64::LDSETLX, 491, 1 },
16353 {AArch64::LDSETW, 492, 1 },
16354 {AArch64::LDSETX, 493, 1 },
16355 {AArch64::LDSMAXB, 494, 1 },
16356 {AArch64::LDSMAXH, 495, 1 },
16357 {AArch64::LDSMAXLB, 496, 1 },
16358 {AArch64::LDSMAXLH, 497, 1 },
16359 {AArch64::LDSMAXLW, 498, 1 },
16360 {AArch64::LDSMAXLX, 499, 1 },
16361 {AArch64::LDSMAXW, 500, 1 },
16362 {AArch64::LDSMAXX, 501, 1 },
16363 {AArch64::LDSMINB, 502, 1 },
16364 {AArch64::LDSMINH, 503, 1 },
16365 {AArch64::LDSMINLB, 504, 1 },
16366 {AArch64::LDSMINLH, 505, 1 },
16367 {AArch64::LDSMINLW, 506, 1 },
16368 {AArch64::LDSMINLX, 507, 1 },
16369 {AArch64::LDSMINW, 508, 1 },
16370 {AArch64::LDSMINX, 509, 1 },
16371 {AArch64::LDTRBi, 510, 1 },
16372 {AArch64::LDTRHi, 511, 1 },
16373 {AArch64::LDTRSBWi, 512, 1 },
16374 {AArch64::LDTRSBXi, 513, 1 },
16375 {AArch64::LDTRSHWi, 514, 1 },
16376 {AArch64::LDTRSHXi, 515, 1 },
16377 {AArch64::LDTRSWi, 516, 1 },
16378 {AArch64::LDTRWi, 517, 1 },
16379 {AArch64::LDTRXi, 518, 1 },
16380 {AArch64::LDUMAXB, 519, 1 },
16381 {AArch64::LDUMAXH, 520, 1 },
16382 {AArch64::LDUMAXLB, 521, 1 },
16383 {AArch64::LDUMAXLH, 522, 1 },
16384 {AArch64::LDUMAXLW, 523, 1 },
16385 {AArch64::LDUMAXLX, 524, 1 },
16386 {AArch64::LDUMAXW, 525, 1 },
16387 {AArch64::LDUMAXX, 526, 1 },
16388 {AArch64::LDUMINB, 527, 1 },
16389 {AArch64::LDUMINH, 528, 1 },
16390 {AArch64::LDUMINLB, 529, 1 },
16391 {AArch64::LDUMINLH, 530, 1 },
16392 {AArch64::LDUMINLW, 531, 1 },
16393 {AArch64::LDUMINLX, 532, 1 },
16394 {AArch64::LDUMINW, 533, 1 },
16395 {AArch64::LDUMINX, 534, 1 },
16396 {AArch64::LDURBBi, 535, 1 },
16397 {AArch64::LDURBi, 536, 1 },
16398 {AArch64::LDURDi, 537, 1 },
16399 {AArch64::LDURHHi, 538, 1 },
16400 {AArch64::LDURHi, 539, 1 },
16401 {AArch64::LDURQi, 540, 1 },
16402 {AArch64::LDURSBWi, 541, 1 },
16403 {AArch64::LDURSBXi, 542, 1 },
16404 {AArch64::LDURSHWi, 543, 1 },
16405 {AArch64::LDURSHXi, 544, 1 },
16406 {AArch64::LDURSWi, 545, 1 },
16407 {AArch64::LDURSi, 546, 1 },
16408 {AArch64::LDURWi, 547, 1 },
16409 {AArch64::LDURXi, 548, 1 },
16410 {AArch64::MADDWrrr, 549, 1 },
16411 {AArch64::MADDXrrr, 550, 1 },
16412 {AArch64::MSUBWrrr, 551, 1 },
16413 {AArch64::MSUBXrrr, 552, 1 },
16414 {AArch64::NOTv16i8, 553, 1 },
16415 {AArch64::NOTv8i8, 554, 1 },
16416 {AArch64::ORNWrs, 555, 3 },
16417 {AArch64::ORNXrs, 558, 3 },
16418 {AArch64::ORRS_PPzPP, 561, 1 },
16419 {AArch64::ORRWrs, 562, 2 },
16420 {AArch64::ORRXrs, 564, 2 },
16421 {AArch64::ORR_PPzPP, 566, 1 },
16422 {AArch64::ORR_ZI, 567, 3 },
16423 {AArch64::ORR_ZZZ, 570, 1 },
16424 {AArch64::ORRv16i8, 571, 1 },
16425 {AArch64::ORRv8i8, 572, 1 },
16426 {AArch64::PACIA1716, 573, 1 },
16427 {AArch64::PACIASP, 574, 1 },
16428 {AArch64::PACIAZ, 575, 1 },
16429 {AArch64::PACIB1716, 576, 1 },
16430 {AArch64::PACIBSP, 577, 1 },
16431 {AArch64::PACIBZ, 578, 1 },
16432 {AArch64::PRFB_D_PZI, 579, 1 },
16433 {AArch64::PRFB_PRI, 580, 1 },
16434 {AArch64::PRFB_S_PZI, 581, 1 },
16435 {AArch64::PRFD_D_PZI, 582, 1 },
16436 {AArch64::PRFD_PRI, 583, 1 },
16437 {AArch64::PRFD_S_PZI, 584, 1 },
16438 {AArch64::PRFH_D_PZI, 585, 1 },
16439 {AArch64::PRFH_PRI, 586, 1 },
16440 {AArch64::PRFH_S_PZI, 587, 1 },
16441 {AArch64::PRFMroX, 588, 1 },
16442 {AArch64::PRFMui, 589, 1 },
16443 {AArch64::PRFUMi, 590, 1 },
16444 {AArch64::PRFW_D_PZI, 591, 1 },
16445 {AArch64::PRFW_PRI, 592, 1 },
16446 {AArch64::PRFW_S_PZI, 593, 1 },
16447 {AArch64::PTRUES_B, 594, 1 },
16448 {AArch64::PTRUES_D, 595, 1 },
16449 {AArch64::PTRUES_H, 596, 1 },
16450 {AArch64::PTRUES_S, 597, 1 },
16451 {AArch64::PTRUE_B, 598, 1 },
16452 {AArch64::PTRUE_D, 599, 1 },
16453 {AArch64::PTRUE_H, 600, 1 },
16454 {AArch64::PTRUE_S, 601, 1 },
16455 {AArch64::RET, 602, 1 },
16456 {AArch64::SBCSWr, 603, 1 },
16457 {AArch64::SBCSXr, 604, 1 },
16458 {AArch64::SBCWr, 605, 1 },
16459 {AArch64::SBCXr, 606, 1 },
16460 {AArch64::SBFMWri, 607, 3 },
16461 {AArch64::SBFMXri, 610, 4 },
16462 {AArch64::SEL_PPPP, 614, 1 },
16463 {AArch64::SEL_ZPZZ_B, 615, 1 },
16464 {AArch64::SEL_ZPZZ_D, 616, 1 },
16465 {AArch64::SEL_ZPZZ_H, 617, 1 },
16466 {AArch64::SEL_ZPZZ_S, 618, 1 },
16467 {AArch64::SMADDLrrr, 619, 1 },
16468 {AArch64::SMSUBLrrr, 620, 1 },
16469 {AArch64::SQDECB_XPiI, 621, 2 },
16470 {AArch64::SQDECB_XPiWdI, 623, 2 },
16471 {AArch64::SQDECD_XPiI, 625, 2 },
16472 {AArch64::SQDECD_XPiWdI, 627, 2 },
16473 {AArch64::SQDECD_ZPiI, 629, 2 },
16474 {AArch64::SQDECH_XPiI, 631, 2 },
16475 {AArch64::SQDECH_XPiWdI, 633, 2 },
16476 {AArch64::SQDECH_ZPiI, 635, 2 },
16477 {AArch64::SQDECW_XPiI, 637, 2 },
16478 {AArch64::SQDECW_XPiWdI, 639, 2 },
16479 {AArch64::SQDECW_ZPiI, 641, 2 },
16480 {AArch64::SQINCB_XPiI, 643, 2 },
16481 {AArch64::SQINCB_XPiWdI, 645, 2 },
16482 {AArch64::SQINCD_XPiI, 647, 2 },
16483 {AArch64::SQINCD_XPiWdI, 649, 2 },
16484 {AArch64::SQINCD_ZPiI, 651, 2 },
16485 {AArch64::SQINCH_XPiI, 653, 2 },
16486 {AArch64::SQINCH_XPiWdI, 655, 2 },
16487 {AArch64::SQINCH_ZPiI, 657, 2 },
16488 {AArch64::SQINCW_XPiI, 659, 2 },
16489 {AArch64::SQINCW_XPiWdI, 661, 2 },
16490 {AArch64::SQINCW_ZPiI, 663, 2 },
16491 {AArch64::SST1B_D_IMM, 665, 1 },
16492 {AArch64::SST1B_S_IMM, 666, 1 },
16493 {AArch64::SST1D_IMM, 667, 1 },
16494 {AArch64::SST1H_D_IMM, 668, 1 },
16495 {AArch64::SST1H_S_IMM, 669, 1 },
16496 {AArch64::SST1W_D_IMM, 670, 1 },
16497 {AArch64::SST1W_IMM, 671, 1 },
16498 {AArch64::ST1B_D_IMM, 672, 1 },
16499 {AArch64::ST1B_H_IMM, 673, 1 },
16500 {AArch64::ST1B_IMM, 674, 1 },
16501 {AArch64::ST1B_S_IMM, 675, 1 },
16502 {AArch64::ST1D_IMM, 676, 1 },
16503 {AArch64::ST1Fourv16b_POST, 677, 1 },
16504 {AArch64::ST1Fourv1d_POST, 678, 1 },
16505 {AArch64::ST1Fourv2d_POST, 679, 1 },
16506 {AArch64::ST1Fourv2s_POST, 680, 1 },
16507 {AArch64::ST1Fourv4h_POST, 681, 1 },
16508 {AArch64::ST1Fourv4s_POST, 682, 1 },
16509 {AArch64::ST1Fourv8b_POST, 683, 1 },
16510 {AArch64::ST1Fourv8h_POST, 684, 1 },
16511 {AArch64::ST1H_D_IMM, 685, 1 },
16512 {AArch64::ST1H_IMM, 686, 1 },
16513 {AArch64::ST1H_S_IMM, 687, 1 },
16514 {AArch64::ST1Onev16b_POST, 688, 1 },
16515 {AArch64::ST1Onev1d_POST, 689, 1 },
16516 {AArch64::ST1Onev2d_POST, 690, 1 },
16517 {AArch64::ST1Onev2s_POST, 691, 1 },
16518 {AArch64::ST1Onev4h_POST, 692, 1 },
16519 {AArch64::ST1Onev4s_POST, 693, 1 },
16520 {AArch64::ST1Onev8b_POST, 694, 1 },
16521 {AArch64::ST1Onev8h_POST, 695, 1 },
16522 {AArch64::ST1Threev16b_POST, 696, 1 },
16523 {AArch64::ST1Threev1d_POST, 697, 1 },
16524 {AArch64::ST1Threev2d_POST, 698, 1 },
16525 {AArch64::ST1Threev2s_POST, 699, 1 },
16526 {AArch64::ST1Threev4h_POST, 700, 1 },
16527 {AArch64::ST1Threev4s_POST, 701, 1 },
16528 {AArch64::ST1Threev8b_POST, 702, 1 },
16529 {AArch64::ST1Threev8h_POST, 703, 1 },
16530 {AArch64::ST1Twov16b_POST, 704, 1 },
16531 {AArch64::ST1Twov1d_POST, 705, 1 },
16532 {AArch64::ST1Twov2d_POST, 706, 1 },
16533 {AArch64::ST1Twov2s_POST, 707, 1 },
16534 {AArch64::ST1Twov4h_POST, 708, 1 },
16535 {AArch64::ST1Twov4s_POST, 709, 1 },
16536 {AArch64::ST1Twov8b_POST, 710, 1 },
16537 {AArch64::ST1Twov8h_POST, 711, 1 },
16538 {AArch64::ST1W_D_IMM, 712, 1 },
16539 {AArch64::ST1W_IMM, 713, 1 },
16540 {AArch64::ST1i16_POST, 714, 1 },
16541 {AArch64::ST1i32_POST, 715, 1 },
16542 {AArch64::ST1i64_POST, 716, 1 },
16543 {AArch64::ST1i8_POST, 717, 1 },
16544 {AArch64::ST2B_IMM, 718, 1 },
16545 {AArch64::ST2D_IMM, 719, 1 },
16546 {AArch64::ST2GOffset, 720, 1 },
16547 {AArch64::ST2H_IMM, 721, 1 },
16548 {AArch64::ST2Twov16b_POST, 722, 1 },
16549 {AArch64::ST2Twov2d_POST, 723, 1 },
16550 {AArch64::ST2Twov2s_POST, 724, 1 },
16551 {AArch64::ST2Twov4h_POST, 725, 1 },
16552 {AArch64::ST2Twov4s_POST, 726, 1 },
16553 {AArch64::ST2Twov8b_POST, 727, 1 },
16554 {AArch64::ST2Twov8h_POST, 728, 1 },
16555 {AArch64::ST2W_IMM, 729, 1 },
16556 {AArch64::ST2i16_POST, 730, 1 },
16557 {AArch64::ST2i32_POST, 731, 1 },
16558 {AArch64::ST2i64_POST, 732, 1 },
16559 {AArch64::ST2i8_POST, 733, 1 },
16560 {AArch64::ST3B_IMM, 734, 1 },
16561 {AArch64::ST3D_IMM, 735, 1 },
16562 {AArch64::ST3H_IMM, 736, 1 },
16563 {AArch64::ST3Threev16b_POST, 737, 1 },
16564 {AArch64::ST3Threev2d_POST, 738, 1 },
16565 {AArch64::ST3Threev2s_POST, 739, 1 },
16566 {AArch64::ST3Threev4h_POST, 740, 1 },
16567 {AArch64::ST3Threev4s_POST, 741, 1 },
16568 {AArch64::ST3Threev8b_POST, 742, 1 },
16569 {AArch64::ST3Threev8h_POST, 743, 1 },
16570 {AArch64::ST3W_IMM, 744, 1 },
16571 {AArch64::ST3i16_POST, 745, 1 },
16572 {AArch64::ST3i32_POST, 746, 1 },
16573 {AArch64::ST3i64_POST, 747, 1 },
16574 {AArch64::ST3i8_POST, 748, 1 },
16575 {AArch64::ST4B_IMM, 749, 1 },
16576 {AArch64::ST4D_IMM, 750, 1 },
16577 {AArch64::ST4Fourv16b_POST, 751, 1 },
16578 {AArch64::ST4Fourv2d_POST, 752, 1 },
16579 {AArch64::ST4Fourv2s_POST, 753, 1 },
16580 {AArch64::ST4Fourv4h_POST, 754, 1 },
16581 {AArch64::ST4Fourv4s_POST, 755, 1 },
16582 {AArch64::ST4Fourv8b_POST, 756, 1 },
16583 {AArch64::ST4Fourv8h_POST, 757, 1 },
16584 {AArch64::ST4H_IMM, 758, 1 },
16585 {AArch64::ST4W_IMM, 759, 1 },
16586 {AArch64::ST4i16_POST, 760, 1 },
16587 {AArch64::ST4i32_POST, 761, 1 },
16588 {AArch64::ST4i64_POST, 762, 1 },
16589 {AArch64::ST4i8_POST, 763, 1 },
16590 {AArch64::STGOffset, 764, 1 },
16591 {AArch64::STGPi, 765, 1 },
16592 {AArch64::STLURBi, 766, 1 },
16593 {AArch64::STLURHi, 767, 1 },
16594 {AArch64::STLURWi, 768, 1 },
16595 {AArch64::STLURXi, 769, 1 },
16596 {AArch64::STNPDi, 770, 1 },
16597 {AArch64::STNPQi, 771, 1 },
16598 {AArch64::STNPSi, 772, 1 },
16599 {AArch64::STNPWi, 773, 1 },
16600 {AArch64::STNPXi, 774, 1 },
16601 {AArch64::STNT1B_ZRI, 775, 1 },
16602 {AArch64::STNT1B_ZZR_D_REAL, 776, 1 },
16603 {AArch64::STNT1B_ZZR_S_REAL, 777, 1 },
16604 {AArch64::STNT1D_ZRI, 778, 1 },
16605 {AArch64::STNT1D_ZZR_D_REAL, 779, 1 },
16606 {AArch64::STNT1H_ZRI, 780, 1 },
16607 {AArch64::STNT1H_ZZR_D_REAL, 781, 1 },
16608 {AArch64::STNT1H_ZZR_S_REAL, 782, 1 },
16609 {AArch64::STNT1W_ZRI, 783, 1 },
16610 {AArch64::STNT1W_ZZR_D_REAL, 784, 1 },
16611 {AArch64::STNT1W_ZZR_S_REAL, 785, 1 },
16612 {AArch64::STPDi, 786, 1 },
16613 {AArch64::STPQi, 787, 1 },
16614 {AArch64::STPSi, 788, 1 },
16615 {AArch64::STPWi, 789, 1 },
16616 {AArch64::STPXi, 790, 1 },
16617 {AArch64::STRBBroX, 791, 1 },
16618 {AArch64::STRBBui, 792, 1 },
16619 {AArch64::STRBroX, 793, 1 },
16620 {AArch64::STRBui, 794, 1 },
16621 {AArch64::STRDroX, 795, 1 },
16622 {AArch64::STRDui, 796, 1 },
16623 {AArch64::STRHHroX, 797, 1 },
16624 {AArch64::STRHHui, 798, 1 },
16625 {AArch64::STRHroX, 799, 1 },
16626 {AArch64::STRHui, 800, 1 },
16627 {AArch64::STRQroX, 801, 1 },
16628 {AArch64::STRQui, 802, 1 },
16629 {AArch64::STRSroX, 803, 1 },
16630 {AArch64::STRSui, 804, 1 },
16631 {AArch64::STRWroX, 805, 1 },
16632 {AArch64::STRWui, 806, 1 },
16633 {AArch64::STRXroX, 807, 1 },
16634 {AArch64::STRXui, 808, 1 },
16635 {AArch64::STR_PXI, 809, 1 },
16636 {AArch64::STR_ZXI, 810, 1 },
16637 {AArch64::STTRBi, 811, 1 },
16638 {AArch64::STTRHi, 812, 1 },
16639 {AArch64::STTRWi, 813, 1 },
16640 {AArch64::STTRXi, 814, 1 },
16641 {AArch64::STURBBi, 815, 1 },
16642 {AArch64::STURBi, 816, 1 },
16643 {AArch64::STURDi, 817, 1 },
16644 {AArch64::STURHHi, 818, 1 },
16645 {AArch64::STURHi, 819, 1 },
16646 {AArch64::STURQi, 820, 1 },
16647 {AArch64::STURSi, 821, 1 },
16648 {AArch64::STURWi, 822, 1 },
16649 {AArch64::STURXi, 823, 1 },
16650 {AArch64::STZ2GOffset, 824, 1 },
16651 {AArch64::STZGOffset, 825, 1 },
16652 {AArch64::SUBSWri, 826, 1 },
16653 {AArch64::SUBSWrs, 827, 5 },
16654 {AArch64::SUBSWrx, 832, 3 },
16655 {AArch64::SUBSXri, 835, 1 },
16656 {AArch64::SUBSXrs, 836, 5 },
16657 {AArch64::SUBSXrx, 841, 1 },
16658 {AArch64::SUBSXrx64, 842, 3 },
16659 {AArch64::SUBWrs, 845, 3 },
16660 {AArch64::SUBWrx, 848, 2 },
16661 {AArch64::SUBXrs, 850, 3 },
16662 {AArch64::SUBXrx64, 853, 2 },
16663 {AArch64::SYSxt, 855, 1 },
16664 {AArch64::UBFMWri, 856, 3 },
16665 {AArch64::UBFMXri, 859, 4 },
16666 {AArch64::UMADDLrrr, 863, 1 },
16667 {AArch64::UMOVvi32, 864, 1 },
16668 {AArch64::UMOVvi64, 865, 1 },
16669 {AArch64::UMSUBLrrr, 866, 1 },
16670 {AArch64::UQDECB_WPiI, 867, 2 },
16671 {AArch64::UQDECB_XPiI, 869, 2 },
16672 {AArch64::UQDECD_WPiI, 871, 2 },
16673 {AArch64::UQDECD_XPiI, 873, 2 },
16674 {AArch64::UQDECD_ZPiI, 875, 2 },
16675 {AArch64::UQDECH_WPiI, 877, 2 },
16676 {AArch64::UQDECH_XPiI, 879, 2 },
16677 {AArch64::UQDECH_ZPiI, 881, 2 },
16678 {AArch64::UQDECW_WPiI, 883, 2 },
16679 {AArch64::UQDECW_XPiI, 885, 2 },
16680 {AArch64::UQDECW_ZPiI, 887, 2 },
16681 {AArch64::UQINCB_WPiI, 889, 2 },
16682 {AArch64::UQINCB_XPiI, 891, 2 },
16683 {AArch64::UQINCD_WPiI, 893, 2 },
16684 {AArch64::UQINCD_XPiI, 895, 2 },
16685 {AArch64::UQINCD_ZPiI, 897, 2 },
16686 {AArch64::UQINCH_WPiI, 899, 2 },
16687 {AArch64::UQINCH_XPiI, 901, 2 },
16688 {AArch64::UQINCH_ZPiI, 903, 2 },
16689 {AArch64::UQINCW_WPiI, 905, 2 },
16690 {AArch64::UQINCW_XPiI, 907, 2 },
16691 {AArch64::UQINCW_ZPiI, 909, 2 },
16692 {AArch64::XPACLRI, 911, 1 },
16693 };
16694
16695 static const AliasPattern Patterns[] = {
16696 // AArch64::ADDSWri - 0
16697 {0, 0, 4, 2 },
16698 // AArch64::ADDSWrs - 1
16699 {13, 2, 4, 4 },
16700 {24, 6, 4, 3 },
16701 {39, 9, 4, 4 },
16702 // AArch64::ADDSWrx - 4
16703 {13, 13, 4, 4 },
16704 {55, 17, 4, 3 },
16705 {39, 20, 4, 4 },
16706 // AArch64::ADDSXri - 7
16707 {0, 24, 4, 2 },
16708 // AArch64::ADDSXrs - 8
16709 {13, 26, 4, 4 },
16710 {24, 30, 4, 3 },
16711 {39, 33, 4, 4 },
16712 // AArch64::ADDSXrx - 11
16713 {55, 37, 4, 3 },
16714 // AArch64::ADDSXrx64 - 12
16715 {13, 40, 4, 4 },
16716 {55, 44, 4, 3 },
16717 {39, 47, 4, 4 },
16718 // AArch64::ADDWri - 15
16719 {70, 51, 4, 4 },
16720 {70, 55, 4, 4 },
16721 // AArch64::ADDWrs - 17
16722 {81, 59, 4, 4 },
16723 // AArch64::ADDWrx - 18
16724 {81, 63, 4, 4 },
16725 {81, 67, 4, 4 },
16726 // AArch64::ADDXri - 20
16727 {70, 71, 4, 4 },
16728 {70, 75, 4, 4 },
16729 // AArch64::ADDXrs - 22
16730 {81, 79, 4, 4 },
16731 // AArch64::ADDXrx64 - 23
16732 {81, 83, 4, 4 },
16733 {81, 87, 4, 4 },
16734 // AArch64::ANDSWri - 25
16735 {96, 91, 3, 2 },
16736 // AArch64::ANDSWrs - 26
16737 {109, 93, 4, 4 },
16738 {120, 97, 4, 3 },
16739 {135, 100, 4, 4 },
16740 // AArch64::ANDSXri - 29
16741 {151, 104, 3, 2 },
16742 // AArch64::ANDSXrs - 30
16743 {109, 106, 4, 4 },
16744 {120, 110, 4, 3 },
16745 {135, 113, 4, 4 },
16746 // AArch64::ANDS_PPzPP - 33
16747 {164, 117, 4, 5 },
16748 // AArch64::ANDWrs - 34
16749 {188, 122, 4, 4 },
16750 // AArch64::ANDXrs - 35
16751 {188, 126, 4, 4 },
16752 // AArch64::AND_PPzPP - 36
16753 {203, 130, 4, 5 },
16754 // AArch64::AND_ZI - 37
16755 {226, 135, 3, 4 },
16756 {247, 139, 3, 4 },
16757 {268, 143, 3, 4 },
16758 // AArch64::AUTIA1716 - 40
16759 {289, 147, 0, 1 },
16760 // AArch64::AUTIASP - 41
16761 {299, 148, 0, 1 },
16762 // AArch64::AUTIAZ - 42
16763 {307, 149, 0, 1 },
16764 // AArch64::AUTIB1716 - 43
16765 {314, 150, 0, 1 },
16766 // AArch64::AUTIBSP - 44
16767 {324, 151, 0, 1 },
16768 // AArch64::AUTIBZ - 45
16769 {332, 152, 0, 1 },
16770 // AArch64::BICSWrs - 46
16771 {339, 153, 4, 4 },
16772 // AArch64::BICSXrs - 47
16773 {339, 157, 4, 4 },
16774 // AArch64::BICWrs - 48
16775 {355, 161, 4, 4 },
16776 // AArch64::BICXrs - 49
16777 {355, 165, 4, 4 },
16778 // AArch64::CLREX - 50
16779 {370, 169, 1, 1 },
16780 // AArch64::CNTB_XPiI - 51
16781 {376, 170, 3, 4 },
16782 {384, 174, 3, 4 },
16783 // AArch64::CNTD_XPiI - 53
16784 {398, 178, 3, 4 },
16785 {406, 182, 3, 4 },
16786 // AArch64::CNTH_XPiI - 55
16787 {420, 186, 3, 4 },
16788 {428, 190, 3, 4 },
16789 // AArch64::CNTW_XPiI - 57
16790 {442, 194, 3, 4 },
16791 {450, 198, 3, 4 },
16792 // AArch64::CPY_ZPmI_B - 59
16793 {464, 202, 5, 4 },
16794 // AArch64::CPY_ZPmI_D - 60
16795 {487, 206, 5, 4 },
16796 // AArch64::CPY_ZPmI_H - 61
16797 {510, 210, 5, 4 },
16798 // AArch64::CPY_ZPmI_S - 62
16799 {533, 214, 5, 4 },
16800 // AArch64::CPY_ZPmR_B - 63
16801 {556, 218, 4, 5 },
16802 // AArch64::CPY_ZPmR_D - 64
16803 {577, 223, 4, 5 },
16804 // AArch64::CPY_ZPmR_H - 65
16805 {598, 228, 4, 5 },
16806 // AArch64::CPY_ZPmR_S - 66
16807 {619, 233, 4, 5 },
16808 // AArch64::CPY_ZPmV_B - 67
16809 {556, 238, 4, 5 },
16810 // AArch64::CPY_ZPmV_D - 68
16811 {577, 243, 4, 5 },
16812 // AArch64::CPY_ZPmV_H - 69
16813 {598, 248, 4, 5 },
16814 // AArch64::CPY_ZPmV_S - 70
16815 {619, 253, 4, 5 },
16816 // AArch64::CPY_ZPzI_B - 71
16817 {640, 258, 4, 3 },
16818 // AArch64::CPY_ZPzI_D - 72
16819 {663, 261, 4, 3 },
16820 // AArch64::CPY_ZPzI_H - 73
16821 {686, 264, 4, 3 },
16822 // AArch64::CPY_ZPzI_S - 74
16823 {709, 267, 4, 3 },
16824 // AArch64::CSINCWr - 75
16825 {732, 270, 4, 4 },
16826 {746, 274, 4, 4 },
16827 // AArch64::CSINCXr - 77
16828 {732, 278, 4, 4 },
16829 {746, 282, 4, 4 },
16830 // AArch64::CSINVWr - 79
16831 {764, 286, 4, 4 },
16832 {779, 290, 4, 4 },
16833 // AArch64::CSINVXr - 81
16834 {764, 294, 4, 4 },
16835 {779, 298, 4, 4 },
16836 // AArch64::CSNEGWr - 83
16837 {797, 302, 4, 4 },
16838 // AArch64::CSNEGXr - 84
16839 {797, 306, 4, 4 },
16840 // AArch64::DCPS1 - 85
16841 {815, 310, 1, 1 },
16842 // AArch64::DCPS2 - 86
16843 {821, 311, 1, 1 },
16844 // AArch64::DCPS3 - 87
16845 {827, 312, 1, 1 },
16846 // AArch64::DECB_XPiI - 88
16847 {833, 313, 4, 5 },
16848 {841, 318, 4, 5 },
16849 // AArch64::DECD_XPiI - 90
16850 {855, 323, 4, 5 },
16851 {863, 328, 4, 5 },
16852 // AArch64::DECD_ZPiI - 92
16853 {877, 333, 4, 5 },
16854 {887, 338, 4, 5 },
16855 // AArch64::DECH_XPiI - 94
16856 {903, 343, 4, 5 },
16857 {911, 348, 4, 5 },
16858 // AArch64::DECH_ZPiI - 96
16859 {925, 353, 4, 5 },
16860 {935, 358, 4, 5 },
16861 // AArch64::DECW_XPiI - 98
16862 {951, 363, 4, 5 },
16863 {959, 368, 4, 5 },
16864 // AArch64::DECW_ZPiI - 100
16865 {973, 373, 4, 5 },
16866 {983, 378, 4, 5 },
16867 // AArch64::DSB - 102
16868 {999, 383, 1, 1 },
16869 {1004, 384, 1, 1 },
16870 // AArch64::DUPM_ZI - 104
16871 {1010, 385, 2, 3 },
16872 {1025, 388, 2, 3 },
16873 {1040, 391, 2, 3 },
16874 {1055, 394, 2, 3 },
16875 {1071, 397, 2, 3 },
16876 {1087, 400, 2, 3 },
16877 // AArch64::DUP_ZI_B - 110
16878 {1103, 403, 3, 2 },
16879 // AArch64::DUP_ZI_D - 111
16880 {1118, 405, 3, 2 },
16881 {1133, 407, 3, 4 },
16882 // AArch64::DUP_ZI_H - 113
16883 {1149, 411, 3, 2 },
16884 {1164, 413, 3, 4 },
16885 // AArch64::DUP_ZI_S - 115
16886 {1180, 417, 3, 2 },
16887 {1195, 419, 3, 4 },
16888 // AArch64::DUP_ZR_B - 117
16889 {1211, 423, 2, 3 },
16890 // AArch64::DUP_ZR_D - 118
16891 {1224, 426, 2, 3 },
16892 // AArch64::DUP_ZR_H - 119
16893 {1237, 429, 2, 3 },
16894 // AArch64::DUP_ZR_S - 120
16895 {1250, 432, 2, 3 },
16896 // AArch64::DUP_ZZI_B - 121
16897 {1263, 435, 3, 4 },
16898 {1278, 439, 3, 3 },
16899 // AArch64::DUP_ZZI_D - 123
16900 {1297, 442, 3, 4 },
16901 {1312, 446, 3, 3 },
16902 // AArch64::DUP_ZZI_H - 125
16903 {1331, 449, 3, 4 },
16904 {1346, 453, 3, 3 },
16905 // AArch64::DUP_ZZI_Q - 127
16906 {1365, 456, 3, 4 },
16907 {1380, 460, 3, 3 },
16908 // AArch64::DUP_ZZI_S - 129
16909 {1399, 463, 3, 4 },
16910 {1414, 467, 3, 3 },
16911 // AArch64::EONWrs - 131
16912 {1433, 470, 4, 4 },
16913 // AArch64::EONXrs - 132
16914 {1433, 474, 4, 4 },
16915 // AArch64::EORS_PPzPP - 133
16916 {1448, 478, 4, 5 },
16917 // AArch64::EORWrs - 134
16918 {1472, 483, 4, 4 },
16919 // AArch64::EORXrs - 135
16920 {1472, 487, 4, 4 },
16921 // AArch64::EOR_PPzPP - 136
16922 {1487, 491, 4, 5 },
16923 // AArch64::EOR_ZI - 137
16924 {1510, 496, 3, 4 },
16925 {1531, 500, 3, 4 },
16926 {1552, 504, 3, 4 },
16927 // AArch64::EXTRWrri - 140
16928 {1573, 508, 4, 3 },
16929 // AArch64::EXTRXrri - 141
16930 {1573, 511, 4, 3 },
16931 // AArch64::FCPY_ZPmI_D - 142
16932 {1588, 514, 4, 4 },
16933 // AArch64::FCPY_ZPmI_H - 143
16934 {1612, 518, 4, 4 },
16935 // AArch64::FCPY_ZPmI_S - 144
16936 {1636, 522, 4, 4 },
16937 // AArch64::FDUP_ZI_D - 145
16938 {1660, 526, 2, 2 },
16939 // AArch64::FDUP_ZI_H - 146
16940 {1676, 528, 2, 2 },
16941 // AArch64::FDUP_ZI_S - 147
16942 {1692, 530, 2, 2 },
16943 // AArch64::GLD1B_D_IMM_REAL - 148
16944 {1708, 532, 4, 5 },
16945 // AArch64::GLD1B_S_IMM_REAL - 149
16946 {1734, 537, 4, 5 },
16947 // AArch64::GLD1D_IMM_REAL - 150
16948 {1760, 542, 4, 5 },
16949 // AArch64::GLD1H_D_IMM_REAL - 151
16950 {1786, 547, 4, 5 },
16951 // AArch64::GLD1H_S_IMM_REAL - 152
16952 {1812, 552, 4, 5 },
16953 // AArch64::GLD1SB_D_IMM_REAL - 153
16954 {1838, 557, 4, 5 },
16955 // AArch64::GLD1SB_S_IMM_REAL - 154
16956 {1865, 562, 4, 5 },
16957 // AArch64::GLD1SH_D_IMM_REAL - 155
16958 {1892, 567, 4, 5 },
16959 // AArch64::GLD1SH_S_IMM_REAL - 156
16960 {1919, 572, 4, 5 },
16961 // AArch64::GLD1SW_D_IMM_REAL - 157
16962 {1946, 577, 4, 5 },
16963 // AArch64::GLD1W_D_IMM_REAL - 158
16964 {1973, 582, 4, 5 },
16965 // AArch64::GLD1W_IMM_REAL - 159
16966 {1999, 587, 4, 5 },
16967 // AArch64::GLDFF1B_D_IMM_REAL - 160
16968 {2025, 592, 4, 5 },
16969 // AArch64::GLDFF1B_S_IMM_REAL - 161
16970 {2053, 597, 4, 5 },
16971 // AArch64::GLDFF1D_IMM_REAL - 162
16972 {2081, 602, 4, 5 },
16973 // AArch64::GLDFF1H_D_IMM_REAL - 163
16974 {2109, 607, 4, 5 },
16975 // AArch64::GLDFF1H_S_IMM_REAL - 164
16976 {2137, 612, 4, 5 },
16977 // AArch64::GLDFF1SB_D_IMM_REAL - 165
16978 {2165, 617, 4, 5 },
16979 // AArch64::GLDFF1SB_S_IMM_REAL - 166
16980 {2194, 622, 4, 5 },
16981 // AArch64::GLDFF1SH_D_IMM_REAL - 167
16982 {2223, 627, 4, 5 },
16983 // AArch64::GLDFF1SH_S_IMM_REAL - 168
16984 {2252, 632, 4, 5 },
16985 // AArch64::GLDFF1SW_D_IMM_REAL - 169
16986 {2281, 637, 4, 5 },
16987 // AArch64::GLDFF1W_D_IMM_REAL - 170
16988 {2310, 642, 4, 5 },
16989 // AArch64::GLDFF1W_IMM_REAL - 171
16990 {2338, 647, 4, 5 },
16991 // AArch64::HINT - 172
16992 {2366, 652, 1, 1 },
16993 {2370, 653, 1, 1 },
16994 {2376, 654, 1, 1 },
16995 {2380, 655, 1, 1 },
16996 {2384, 656, 1, 1 },
16997 {2388, 657, 1, 1 },
16998 {2393, 658, 1, 1 },
16999 {2397, 659, 1, 2 },
17000 {2401, 661, 1, 1 },
17001 {2406, 662, 1, 2 },
17002 {2410, 664, 1, 2 },
17003 {2419, 666, 1, 2 },
17004 // AArch64::INCB_XPiI - 184
17005 {2428, 668, 4, 5 },
17006 {2436, 673, 4, 5 },
17007 // AArch64::INCD_XPiI - 186
17008 {2450, 678, 4, 5 },
17009 {2458, 683, 4, 5 },
17010 // AArch64::INCD_ZPiI - 188
17011 {2472, 688, 4, 5 },
17012 {2482, 693, 4, 5 },
17013 // AArch64::INCH_XPiI - 190
17014 {2498, 698, 4, 5 },
17015 {2506, 703, 4, 5 },
17016 // AArch64::INCH_ZPiI - 192
17017 {2520, 708, 4, 5 },
17018 {2530, 713, 4, 5 },
17019 // AArch64::INCW_XPiI - 194
17020 {2546, 718, 4, 5 },
17021 {2554, 723, 4, 5 },
17022 // AArch64::INCW_ZPiI - 196
17023 {2568, 728, 4, 5 },
17024 {2578, 733, 4, 5 },
17025 // AArch64::INSvi16gpr - 198
17026 {2594, 738, 4, 5 },
17027 // AArch64::INSvi16lane - 199
17028 {2613, 743, 5, 5 },
17029 // AArch64::INSvi32gpr - 200
17030 {2640, 748, 4, 5 },
17031 // AArch64::INSvi32lane - 201
17032 {2659, 753, 5, 5 },
17033 // AArch64::INSvi64gpr - 202
17034 {2686, 758, 4, 5 },
17035 // AArch64::INSvi64lane - 203
17036 {2705, 763, 5, 5 },
17037 // AArch64::INSvi8gpr - 204
17038 {2732, 768, 4, 5 },
17039 // AArch64::INSvi8lane - 205
17040 {2751, 773, 5, 5 },
17041 // AArch64::IRG - 206
17042 {2778, 778, 3, 4 },
17043 // AArch64::ISB - 207
17044 {2789, 782, 1, 1 },
17045 // AArch64::LD1B_D_IMM_REAL - 208
17046 {2793, 783, 4, 5 },
17047 // AArch64::LD1B_H_IMM_REAL - 209
17048 {2817, 788, 4, 5 },
17049 // AArch64::LD1B_IMM_REAL - 210
17050 {2841, 793, 4, 5 },
17051 // AArch64::LD1B_S_IMM_REAL - 211
17052 {2865, 798, 4, 5 },
17053 // AArch64::LD1D_IMM_REAL - 212
17054 {2889, 803, 4, 5 },
17055 // AArch64::LD1Fourv16b_POST - 213
17056 {2913, 808, 4, 5 },
17057 // AArch64::LD1Fourv1d_POST - 214
17058 {2933, 813, 4, 5 },
17059 // AArch64::LD1Fourv2d_POST - 215
17060 {2953, 818, 4, 5 },
17061 // AArch64::LD1Fourv2s_POST - 216
17062 {2973, 823, 4, 5 },
17063 // AArch64::LD1Fourv4h_POST - 217
17064 {2993, 828, 4, 5 },
17065 // AArch64::LD1Fourv4s_POST - 218
17066 {3013, 833, 4, 5 },
17067 // AArch64::LD1Fourv8b_POST - 219
17068 {3033, 838, 4, 5 },
17069 // AArch64::LD1Fourv8h_POST - 220
17070 {3053, 843, 4, 5 },
17071 // AArch64::LD1H_D_IMM_REAL - 221
17072 {3073, 848, 4, 5 },
17073 // AArch64::LD1H_IMM_REAL - 222
17074 {3097, 853, 4, 5 },
17075 // AArch64::LD1H_S_IMM_REAL - 223
17076 {3121, 858, 4, 5 },
17077 // AArch64::LD1Onev16b_POST - 224
17078 {3145, 863, 4, 5 },
17079 // AArch64::LD1Onev1d_POST - 225
17080 {3165, 868, 4, 5 },
17081 // AArch64::LD1Onev2d_POST - 226
17082 {3184, 873, 4, 5 },
17083 // AArch64::LD1Onev2s_POST - 227
17084 {3204, 878, 4, 5 },
17085 // AArch64::LD1Onev4h_POST - 228
17086 {3223, 883, 4, 5 },
17087 // AArch64::LD1Onev4s_POST - 229
17088 {3242, 888, 4, 5 },
17089 // AArch64::LD1Onev8b_POST - 230
17090 {3262, 893, 4, 5 },
17091 // AArch64::LD1Onev8h_POST - 231
17092 {3281, 898, 4, 5 },
17093 // AArch64::LD1RB_D_IMM - 232
17094 {3301, 903, 4, 5 },
17095 // AArch64::LD1RB_H_IMM - 233
17096 {3326, 908, 4, 5 },
17097 // AArch64::LD1RB_IMM - 234
17098 {3351, 913, 4, 5 },
17099 // AArch64::LD1RB_S_IMM - 235
17100 {3376, 918, 4, 5 },
17101 // AArch64::LD1RD_IMM - 236
17102 {3401, 923, 4, 5 },
17103 // AArch64::LD1RH_D_IMM - 237
17104 {3426, 928, 4, 5 },
17105 // AArch64::LD1RH_IMM - 238
17106 {3451, 933, 4, 5 },
17107 // AArch64::LD1RH_S_IMM - 239
17108 {3476, 938, 4, 5 },
17109 // AArch64::LD1RO_B_IMM - 240
17110 {3501, 943, 4, 6 },
17111 // AArch64::LD1RO_D_IMM - 241
17112 {3527, 949, 4, 6 },
17113 // AArch64::LD1RO_H_IMM - 242
17114 {3553, 955, 4, 6 },
17115 // AArch64::LD1RO_W_IMM - 243
17116 {3579, 961, 4, 6 },
17117 // AArch64::LD1RQ_B_IMM - 244
17118 {3605, 967, 4, 5 },
17119 // AArch64::LD1RQ_D_IMM - 245
17120 {3631, 972, 4, 5 },
17121 // AArch64::LD1RQ_H_IMM - 246
17122 {3657, 977, 4, 5 },
17123 // AArch64::LD1RQ_W_IMM - 247
17124 {3683, 982, 4, 5 },
17125 // AArch64::LD1RSB_D_IMM - 248
17126 {3709, 987, 4, 5 },
17127 // AArch64::LD1RSB_H_IMM - 249
17128 {3735, 992, 4, 5 },
17129 // AArch64::LD1RSB_S_IMM - 250
17130 {3761, 997, 4, 5 },
17131 // AArch64::LD1RSH_D_IMM - 251
17132 {3787, 1002, 4, 5 },
17133 // AArch64::LD1RSH_S_IMM - 252
17134 {3813, 1007, 4, 5 },
17135 // AArch64::LD1RSW_IMM - 253
17136 {3839, 1012, 4, 5 },
17137 // AArch64::LD1RW_D_IMM - 254
17138 {3865, 1017, 4, 5 },
17139 // AArch64::LD1RW_IMM - 255
17140 {3890, 1022, 4, 5 },
17141 // AArch64::LD1Rv16b_POST - 256
17142 {3915, 1027, 4, 5 },
17143 // AArch64::LD1Rv1d_POST - 257
17144 {3935, 1032, 4, 5 },
17145 // AArch64::LD1Rv2d_POST - 258
17146 {3955, 1037, 4, 5 },
17147 // AArch64::LD1Rv2s_POST - 259
17148 {3975, 1042, 4, 5 },
17149 // AArch64::LD1Rv4h_POST - 260
17150 {3995, 1047, 4, 5 },
17151 // AArch64::LD1Rv4s_POST - 261
17152 {4015, 1052, 4, 5 },
17153 // AArch64::LD1Rv8b_POST - 262
17154 {4035, 1057, 4, 5 },
17155 // AArch64::LD1Rv8h_POST - 263
17156 {4055, 1062, 4, 5 },
17157 // AArch64::LD1SB_D_IMM_REAL - 264
17158 {4075, 1067, 4, 5 },
17159 // AArch64::LD1SB_H_IMM_REAL - 265
17160 {4100, 1072, 4, 5 },
17161 // AArch64::LD1SB_S_IMM_REAL - 266
17162 {4125, 1077, 4, 5 },
17163 // AArch64::LD1SH_D_IMM_REAL - 267
17164 {4150, 1082, 4, 5 },
17165 // AArch64::LD1SH_S_IMM_REAL - 268
17166 {4175, 1087, 4, 5 },
17167 // AArch64::LD1SW_D_IMM_REAL - 269
17168 {4200, 1092, 4, 5 },
17169 // AArch64::LD1Threev16b_POST - 270
17170 {4225, 1097, 4, 5 },
17171 // AArch64::LD1Threev1d_POST - 271
17172 {4245, 1102, 4, 5 },
17173 // AArch64::LD1Threev2d_POST - 272
17174 {4265, 1107, 4, 5 },
17175 // AArch64::LD1Threev2s_POST - 273
17176 {4285, 1112, 4, 5 },
17177 // AArch64::LD1Threev4h_POST - 274
17178 {4305, 1117, 4, 5 },
17179 // AArch64::LD1Threev4s_POST - 275
17180 {4325, 1122, 4, 5 },
17181 // AArch64::LD1Threev8b_POST - 276
17182 {4345, 1127, 4, 5 },
17183 // AArch64::LD1Threev8h_POST - 277
17184 {4365, 1132, 4, 5 },
17185 // AArch64::LD1Twov16b_POST - 278
17186 {4385, 1137, 4, 5 },
17187 // AArch64::LD1Twov1d_POST - 279
17188 {4405, 1142, 4, 5 },
17189 // AArch64::LD1Twov2d_POST - 280
17190 {4425, 1147, 4, 5 },
17191 // AArch64::LD1Twov2s_POST - 281
17192 {4445, 1152, 4, 5 },
17193 // AArch64::LD1Twov4h_POST - 282
17194 {4465, 1157, 4, 5 },
17195 // AArch64::LD1Twov4s_POST - 283
17196 {4485, 1162, 4, 5 },
17197 // AArch64::LD1Twov8b_POST - 284
17198 {4505, 1167, 4, 5 },
17199 // AArch64::LD1Twov8h_POST - 285
17200 {4525, 1172, 4, 5 },
17201 // AArch64::LD1W_D_IMM_REAL - 286
17202 {4545, 1177, 4, 5 },
17203 // AArch64::LD1W_IMM_REAL - 287
17204 {4569, 1182, 4, 5 },
17205 // AArch64::LD1i16_POST - 288
17206 {4593, 1187, 6, 7 },
17207 // AArch64::LD1i32_POST - 289
17208 {4616, 1194, 6, 7 },
17209 // AArch64::LD1i64_POST - 290
17210 {4639, 1201, 6, 7 },
17211 // AArch64::LD1i8_POST - 291
17212 {4662, 1208, 6, 7 },
17213 // AArch64::LD2B_IMM - 292
17214 {4685, 1215, 4, 5 },
17215 // AArch64::LD2D_IMM - 293
17216 {4709, 1220, 4, 5 },
17217 // AArch64::LD2H_IMM - 294
17218 {4733, 1225, 4, 5 },
17219 // AArch64::LD2Rv16b_POST - 295
17220 {4757, 1230, 4, 5 },
17221 // AArch64::LD2Rv1d_POST - 296
17222 {4777, 1235, 4, 5 },
17223 // AArch64::LD2Rv2d_POST - 297
17224 {4798, 1240, 4, 5 },
17225 // AArch64::LD2Rv2s_POST - 298
17226 {4819, 1245, 4, 5 },
17227 // AArch64::LD2Rv4h_POST - 299
17228 {4839, 1250, 4, 5 },
17229 // AArch64::LD2Rv4s_POST - 300
17230 {4859, 1255, 4, 5 },
17231 // AArch64::LD2Rv8b_POST - 301
17232 {4879, 1260, 4, 5 },
17233 // AArch64::LD2Rv8h_POST - 302
17234 {4899, 1265, 4, 5 },
17235 // AArch64::LD2Twov16b_POST - 303
17236 {4919, 1270, 4, 5 },
17237 // AArch64::LD2Twov2d_POST - 304
17238 {4939, 1275, 4, 5 },
17239 // AArch64::LD2Twov2s_POST - 305
17240 {4959, 1280, 4, 5 },
17241 // AArch64::LD2Twov4h_POST - 306
17242 {4979, 1285, 4, 5 },
17243 // AArch64::LD2Twov4s_POST - 307
17244 {4999, 1290, 4, 5 },
17245 // AArch64::LD2Twov8b_POST - 308
17246 {5019, 1295, 4, 5 },
17247 // AArch64::LD2Twov8h_POST - 309
17248 {5039, 1300, 4, 5 },
17249 // AArch64::LD2W_IMM - 310
17250 {5059, 1305, 4, 5 },
17251 // AArch64::LD2i16_POST - 311
17252 {5083, 1310, 6, 7 },
17253 // AArch64::LD2i32_POST - 312
17254 {5106, 1317, 6, 7 },
17255 // AArch64::LD2i64_POST - 313
17256 {5129, 1324, 6, 7 },
17257 // AArch64::LD2i8_POST - 314
17258 {5153, 1331, 6, 7 },
17259 // AArch64::LD3B_IMM - 315
17260 {5176, 1338, 4, 5 },
17261 // AArch64::LD3D_IMM - 316
17262 {5200, 1343, 4, 5 },
17263 // AArch64::LD3H_IMM - 317
17264 {5224, 1348, 4, 5 },
17265 // AArch64::LD3Rv16b_POST - 318
17266 {5248, 1353, 4, 5 },
17267 // AArch64::LD3Rv1d_POST - 319
17268 {5268, 1358, 4, 5 },
17269 // AArch64::LD3Rv2d_POST - 320
17270 {5289, 1363, 4, 5 },
17271 // AArch64::LD3Rv2s_POST - 321
17272 {5310, 1368, 4, 5 },
17273 // AArch64::LD3Rv4h_POST - 322
17274 {5331, 1373, 4, 5 },
17275 // AArch64::LD3Rv4s_POST - 323
17276 {5351, 1378, 4, 5 },
17277 // AArch64::LD3Rv8b_POST - 324
17278 {5372, 1383, 4, 5 },
17279 // AArch64::LD3Rv8h_POST - 325
17280 {5392, 1388, 4, 5 },
17281 // AArch64::LD3Threev16b_POST - 326
17282 {5412, 1393, 4, 5 },
17283 // AArch64::LD3Threev2d_POST - 327
17284 {5432, 1398, 4, 5 },
17285 // AArch64::LD3Threev2s_POST - 328
17286 {5452, 1403, 4, 5 },
17287 // AArch64::LD3Threev4h_POST - 329
17288 {5472, 1408, 4, 5 },
17289 // AArch64::LD3Threev4s_POST - 330
17290 {5492, 1413, 4, 5 },
17291 // AArch64::LD3Threev8b_POST - 331
17292 {5512, 1418, 4, 5 },
17293 // AArch64::LD3Threev8h_POST - 332
17294 {5532, 1423, 4, 5 },
17295 // AArch64::LD3W_IMM - 333
17296 {5552, 1428, 4, 5 },
17297 // AArch64::LD3i16_POST - 334
17298 {5576, 1433, 6, 7 },
17299 // AArch64::LD3i32_POST - 335
17300 {5599, 1440, 6, 7 },
17301 // AArch64::LD3i64_POST - 336
17302 {5623, 1447, 6, 7 },
17303 // AArch64::LD3i8_POST - 337
17304 {5647, 1454, 6, 7 },
17305 // AArch64::LD4B_IMM - 338
17306 {5670, 1461, 4, 5 },
17307 // AArch64::LD4D_IMM - 339
17308 {5694, 1466, 4, 5 },
17309 // AArch64::LD4Fourv16b_POST - 340
17310 {5718, 1471, 4, 5 },
17311 // AArch64::LD4Fourv2d_POST - 341
17312 {5738, 1476, 4, 5 },
17313 // AArch64::LD4Fourv2s_POST - 342
17314 {5758, 1481, 4, 5 },
17315 // AArch64::LD4Fourv4h_POST - 343
17316 {5778, 1486, 4, 5 },
17317 // AArch64::LD4Fourv4s_POST - 344
17318 {5798, 1491, 4, 5 },
17319 // AArch64::LD4Fourv8b_POST - 345
17320 {5818, 1496, 4, 5 },
17321 // AArch64::LD4Fourv8h_POST - 346
17322 {5838, 1501, 4, 5 },
17323 // AArch64::LD4H_IMM - 347
17324 {5858, 1506, 4, 5 },
17325 // AArch64::LD4Rv16b_POST - 348
17326 {5882, 1511, 4, 5 },
17327 // AArch64::LD4Rv1d_POST - 349
17328 {5902, 1516, 4, 5 },
17329 // AArch64::LD4Rv2d_POST - 350
17330 {5923, 1521, 4, 5 },
17331 // AArch64::LD4Rv2s_POST - 351
17332 {5944, 1526, 4, 5 },
17333 // AArch64::LD4Rv4h_POST - 352
17334 {5965, 1531, 4, 5 },
17335 // AArch64::LD4Rv4s_POST - 353
17336 {5985, 1536, 4, 5 },
17337 // AArch64::LD4Rv8b_POST - 354
17338 {6006, 1541, 4, 5 },
17339 // AArch64::LD4Rv8h_POST - 355
17340 {6026, 1546, 4, 5 },
17341 // AArch64::LD4W_IMM - 356
17342 {6046, 1551, 4, 5 },
17343 // AArch64::LD4i16_POST - 357
17344 {6070, 1556, 6, 7 },
17345 // AArch64::LD4i32_POST - 358
17346 {6093, 1563, 6, 7 },
17347 // AArch64::LD4i64_POST - 359
17348 {6117, 1570, 6, 7 },
17349 // AArch64::LD4i8_POST - 360
17350 {6141, 1577, 6, 7 },
17351 // AArch64::LDADDB - 361
17352 {6164, 1584, 3, 4 },
17353 // AArch64::LDADDH - 362
17354 {6180, 1588, 3, 4 },
17355 // AArch64::LDADDLB - 363
17356 {6196, 1592, 3, 4 },
17357 // AArch64::LDADDLH - 364
17358 {6213, 1596, 3, 4 },
17359 // AArch64::LDADDLW - 365
17360 {6230, 1600, 3, 4 },
17361 // AArch64::LDADDLX - 366
17362 {6230, 1604, 3, 4 },
17363 // AArch64::LDADDW - 367
17364 {6246, 1608, 3, 4 },
17365 // AArch64::LDADDX - 368
17366 {6246, 1612, 3, 4 },
17367 // AArch64::LDAPURBi - 369
17368 {6261, 1616, 3, 4 },
17369 // AArch64::LDAPURHi - 370
17370 {6278, 1620, 3, 4 },
17371 // AArch64::LDAPURSBWi - 371
17372 {6295, 1624, 3, 4 },
17373 // AArch64::LDAPURSBXi - 372
17374 {6295, 1628, 3, 4 },
17375 // AArch64::LDAPURSHWi - 373
17376 {6313, 1632, 3, 4 },
17377 // AArch64::LDAPURSHXi - 374
17378 {6313, 1636, 3, 4 },
17379 // AArch64::LDAPURSWi - 375
17380 {6331, 1640, 3, 4 },
17381 // AArch64::LDAPURXi - 376
17382 {6349, 1644, 3, 4 },
17383 // AArch64::LDAPURi - 377
17384 {6349, 1648, 3, 4 },
17385 // AArch64::LDCLRB - 378
17386 {6365, 1652, 3, 4 },
17387 // AArch64::LDCLRH - 379
17388 {6381, 1656, 3, 4 },
17389 // AArch64::LDCLRLB - 380
17390 {6397, 1660, 3, 4 },
17391 // AArch64::LDCLRLH - 381
17392 {6414, 1664, 3, 4 },
17393 // AArch64::LDCLRLW - 382
17394 {6431, 1668, 3, 4 },
17395 // AArch64::LDCLRLX - 383
17396 {6431, 1672, 3, 4 },
17397 // AArch64::LDCLRW - 384
17398 {6447, 1676, 3, 4 },
17399 // AArch64::LDCLRX - 385
17400 {6447, 1680, 3, 4 },
17401 // AArch64::LDEORB - 386
17402 {6462, 1684, 3, 4 },
17403 // AArch64::LDEORH - 387
17404 {6478, 1688, 3, 4 },
17405 // AArch64::LDEORLB - 388
17406 {6494, 1692, 3, 4 },
17407 // AArch64::LDEORLH - 389
17408 {6511, 1696, 3, 4 },
17409 // AArch64::LDEORLW - 390
17410 {6528, 1700, 3, 4 },
17411 // AArch64::LDEORLX - 391
17412 {6528, 1704, 3, 4 },
17413 // AArch64::LDEORW - 392
17414 {6544, 1708, 3, 4 },
17415 // AArch64::LDEORX - 393
17416 {6544, 1712, 3, 4 },
17417 // AArch64::LDFF1B_D_REAL - 394
17418 {6559, 1716, 4, 5 },
17419 // AArch64::LDFF1B_H_REAL - 395
17420 {6585, 1721, 4, 5 },
17421 // AArch64::LDFF1B_REAL - 396
17422 {6611, 1726, 4, 5 },
17423 // AArch64::LDFF1B_S_REAL - 397
17424 {6637, 1731, 4, 5 },
17425 // AArch64::LDFF1D_REAL - 398
17426 {6663, 1736, 4, 5 },
17427 // AArch64::LDFF1H_D_REAL - 399
17428 {6689, 1741, 4, 5 },
17429 // AArch64::LDFF1H_REAL - 400
17430 {6715, 1746, 4, 5 },
17431 // AArch64::LDFF1H_S_REAL - 401
17432 {6741, 1751, 4, 5 },
17433 // AArch64::LDFF1SB_D_REAL - 402
17434 {6767, 1756, 4, 5 },
17435 // AArch64::LDFF1SB_H_REAL - 403
17436 {6794, 1761, 4, 5 },
17437 // AArch64::LDFF1SB_S_REAL - 404
17438 {6821, 1766, 4, 5 },
17439 // AArch64::LDFF1SH_D_REAL - 405
17440 {6848, 1771, 4, 5 },
17441 // AArch64::LDFF1SH_S_REAL - 406
17442 {6875, 1776, 4, 5 },
17443 // AArch64::LDFF1SW_D_REAL - 407
17444 {6902, 1781, 4, 5 },
17445 // AArch64::LDFF1W_D_REAL - 408
17446 {6929, 1786, 4, 5 },
17447 // AArch64::LDFF1W_REAL - 409
17448 {6955, 1791, 4, 5 },
17449 // AArch64::LDG - 410
17450 {6981, 1796, 4, 5 },
17451 // AArch64::LDNF1B_D_IMM_REAL - 411
17452 {6994, 1801, 4, 5 },
17453 // AArch64::LDNF1B_H_IMM_REAL - 412
17454 {7020, 1806, 4, 5 },
17455 // AArch64::LDNF1B_IMM_REAL - 413
17456 {7046, 1811, 4, 5 },
17457 // AArch64::LDNF1B_S_IMM_REAL - 414
17458 {7072, 1816, 4, 5 },
17459 // AArch64::LDNF1D_IMM_REAL - 415
17460 {7098, 1821, 4, 5 },
17461 // AArch64::LDNF1H_D_IMM_REAL - 416
17462 {7124, 1826, 4, 5 },
17463 // AArch64::LDNF1H_IMM_REAL - 417
17464 {7150, 1831, 4, 5 },
17465 // AArch64::LDNF1H_S_IMM_REAL - 418
17466 {7176, 1836, 4, 5 },
17467 // AArch64::LDNF1SB_D_IMM_REAL - 419
17468 {7202, 1841, 4, 5 },
17469 // AArch64::LDNF1SB_H_IMM_REAL - 420
17470 {7229, 1846, 4, 5 },
17471 // AArch64::LDNF1SB_S_IMM_REAL - 421
17472 {7256, 1851, 4, 5 },
17473 // AArch64::LDNF1SH_D_IMM_REAL - 422
17474 {7283, 1856, 4, 5 },
17475 // AArch64::LDNF1SH_S_IMM_REAL - 423
17476 {7310, 1861, 4, 5 },
17477 // AArch64::LDNF1SW_D_IMM_REAL - 424
17478 {7337, 1866, 4, 5 },
17479 // AArch64::LDNF1W_D_IMM_REAL - 425
17480 {7364, 1871, 4, 5 },
17481 // AArch64::LDNF1W_IMM_REAL - 426
17482 {7390, 1876, 4, 5 },
17483 // AArch64::LDNPDi - 427
17484 {7416, 1881, 4, 4 },
17485 // AArch64::LDNPQi - 428
17486 {7416, 1885, 4, 4 },
17487 // AArch64::LDNPSi - 429
17488 {7416, 1889, 4, 4 },
17489 // AArch64::LDNPWi - 430
17490 {7416, 1893, 4, 4 },
17491 // AArch64::LDNPXi - 431
17492 {7416, 1897, 4, 4 },
17493 // AArch64::LDNT1B_ZRI - 432
17494 {7434, 1901, 4, 5 },
17495 // AArch64::LDNT1B_ZZR_D_REAL - 433
17496 {7460, 1906, 4, 5 },
17497 // AArch64::LDNT1B_ZZR_S_REAL - 434
17498 {7488, 1911, 4, 5 },
17499 // AArch64::LDNT1D_ZRI - 435
17500 {7516, 1916, 4, 5 },
17501 // AArch64::LDNT1D_ZZR_D_REAL - 436
17502 {7542, 1921, 4, 5 },
17503 // AArch64::LDNT1H_ZRI - 437
17504 {7570, 1926, 4, 5 },
17505 // AArch64::LDNT1H_ZZR_D_REAL - 438
17506 {7596, 1931, 4, 5 },
17507 // AArch64::LDNT1H_ZZR_S_REAL - 439
17508 {7624, 1936, 4, 5 },
17509 // AArch64::LDNT1SB_ZZR_D_REAL - 440
17510 {7652, 1941, 4, 5 },
17511 // AArch64::LDNT1SB_ZZR_S_REAL - 441
17512 {7681, 1946, 4, 5 },
17513 // AArch64::LDNT1SH_ZZR_D_REAL - 442
17514 {7710, 1951, 4, 5 },
17515 // AArch64::LDNT1SH_ZZR_S_REAL - 443
17516 {7739, 1956, 4, 5 },
17517 // AArch64::LDNT1SW_ZZR_D_REAL - 444
17518 {7768, 1961, 4, 5 },
17519 // AArch64::LDNT1W_ZRI - 445
17520 {7797, 1966, 4, 5 },
17521 // AArch64::LDNT1W_ZZR_D_REAL - 446
17522 {7823, 1971, 4, 5 },
17523 // AArch64::LDNT1W_ZZR_S_REAL - 447
17524 {7851, 1976, 4, 5 },
17525 // AArch64::LDPDi - 448
17526 {7879, 1981, 4, 4 },
17527 // AArch64::LDPQi - 449
17528 {7879, 1985, 4, 4 },
17529 // AArch64::LDPSWi - 450
17530 {7896, 1989, 4, 4 },
17531 // AArch64::LDPSi - 451
17532 {7879, 1993, 4, 4 },
17533 // AArch64::LDPWi - 452
17534 {7879, 1997, 4, 4 },
17535 // AArch64::LDPXi - 453
17536 {7879, 2001, 4, 4 },
17537 // AArch64::LDRAAindexed - 454
17538 {7915, 2005, 3, 4 },
17539 // AArch64::LDRABindexed - 455
17540 {7930, 2009, 3, 4 },
17541 // AArch64::LDRBBroX - 456
17542 {7945, 2013, 5, 5 },
17543 // AArch64::LDRBBui - 457
17544 {7963, 2018, 3, 3 },
17545 // AArch64::LDRBroX - 458
17546 {7977, 2021, 5, 5 },
17547 // AArch64::LDRBui - 459
17548 {7994, 2026, 3, 3 },
17549 // AArch64::LDRDroX - 460
17550 {7977, 2029, 5, 5 },
17551 // AArch64::LDRDui - 461
17552 {7994, 2034, 3, 3 },
17553 // AArch64::LDRHHroX - 462
17554 {8007, 2037, 5, 5 },
17555 // AArch64::LDRHHui - 463
17556 {8025, 2042, 3, 3 },
17557 // AArch64::LDRHroX - 464
17558 {7977, 2045, 5, 5 },
17559 // AArch64::LDRHui - 465
17560 {7994, 2050, 3, 3 },
17561 // AArch64::LDRQroX - 466
17562 {7977, 2053, 5, 5 },
17563 // AArch64::LDRQui - 467
17564 {7994, 2058, 3, 3 },
17565 // AArch64::LDRSBWroX - 468
17566 {8039, 2061, 5, 5 },
17567 // AArch64::LDRSBWui - 469
17568 {8058, 2066, 3, 3 },
17569 // AArch64::LDRSBXroX - 470
17570 {8039, 2069, 5, 5 },
17571 // AArch64::LDRSBXui - 471
17572 {8058, 2074, 3, 3 },
17573 // AArch64::LDRSHWroX - 472
17574 {8073, 2077, 5, 5 },
17575 // AArch64::LDRSHWui - 473
17576 {8092, 2082, 3, 3 },
17577 // AArch64::LDRSHXroX - 474
17578 {8073, 2085, 5, 5 },
17579 // AArch64::LDRSHXui - 475
17580 {8092, 2090, 3, 3 },
17581 // AArch64::LDRSWroX - 476
17582 {8107, 2093, 5, 5 },
17583 // AArch64::LDRSWui - 477
17584 {8126, 2098, 3, 3 },
17585 // AArch64::LDRSroX - 478
17586 {7977, 2101, 5, 5 },
17587 // AArch64::LDRSui - 479
17588 {7994, 2106, 3, 3 },
17589 // AArch64::LDRWroX - 480
17590 {7977, 2109, 5, 5 },
17591 // AArch64::LDRWui - 481
17592 {7994, 2114, 3, 3 },
17593 // AArch64::LDRXroX - 482
17594 {7977, 2117, 5, 5 },
17595 // AArch64::LDRXui - 483
17596 {7994, 2122, 3, 3 },
17597 // AArch64::LDR_PXI - 484
17598 {8141, 2125, 3, 4 },
17599 // AArch64::LDR_ZXI - 485
17600 {8141, 2129, 3, 4 },
17601 // AArch64::LDSETB - 486
17602 {8156, 2133, 3, 4 },
17603 // AArch64::LDSETH - 487
17604 {8172, 2137, 3, 4 },
17605 // AArch64::LDSETLB - 488
17606 {8188, 2141, 3, 4 },
17607 // AArch64::LDSETLH - 489
17608 {8205, 2145, 3, 4 },
17609 // AArch64::LDSETLW - 490
17610 {8222, 2149, 3, 4 },
17611 // AArch64::LDSETLX - 491
17612 {8222, 2153, 3, 4 },
17613 // AArch64::LDSETW - 492
17614 {8238, 2157, 3, 4 },
17615 // AArch64::LDSETX - 493
17616 {8238, 2161, 3, 4 },
17617 // AArch64::LDSMAXB - 494
17618 {8253, 2165, 3, 4 },
17619 // AArch64::LDSMAXH - 495
17620 {8270, 2169, 3, 4 },
17621 // AArch64::LDSMAXLB - 496
17622 {8287, 2173, 3, 4 },
17623 // AArch64::LDSMAXLH - 497
17624 {8305, 2177, 3, 4 },
17625 // AArch64::LDSMAXLW - 498
17626 {8323, 2181, 3, 4 },
17627 // AArch64::LDSMAXLX - 499
17628 {8323, 2185, 3, 4 },
17629 // AArch64::LDSMAXW - 500
17630 {8340, 2189, 3, 4 },
17631 // AArch64::LDSMAXX - 501
17632 {8340, 2193, 3, 4 },
17633 // AArch64::LDSMINB - 502
17634 {8356, 2197, 3, 4 },
17635 // AArch64::LDSMINH - 503
17636 {8373, 2201, 3, 4 },
17637 // AArch64::LDSMINLB - 504
17638 {8390, 2205, 3, 4 },
17639 // AArch64::LDSMINLH - 505
17640 {8408, 2209, 3, 4 },
17641 // AArch64::LDSMINLW - 506
17642 {8426, 2213, 3, 4 },
17643 // AArch64::LDSMINLX - 507
17644 {8426, 2217, 3, 4 },
17645 // AArch64::LDSMINW - 508
17646 {8443, 2221, 3, 4 },
17647 // AArch64::LDSMINX - 509
17648 {8443, 2225, 3, 4 },
17649 // AArch64::LDTRBi - 510
17650 {8459, 2229, 3, 3 },
17651 // AArch64::LDTRHi - 511
17652 {8474, 2232, 3, 3 },
17653 // AArch64::LDTRSBWi - 512
17654 {8489, 2235, 3, 3 },
17655 // AArch64::LDTRSBXi - 513
17656 {8489, 2238, 3, 3 },
17657 // AArch64::LDTRSHWi - 514
17658 {8505, 2241, 3, 3 },
17659 // AArch64::LDTRSHXi - 515
17660 {8505, 2244, 3, 3 },
17661 // AArch64::LDTRSWi - 516
17662 {8521, 2247, 3, 3 },
17663 // AArch64::LDTRWi - 517
17664 {8537, 2250, 3, 3 },
17665 // AArch64::LDTRXi - 518
17666 {8537, 2253, 3, 3 },
17667 // AArch64::LDUMAXB - 519
17668 {8551, 2256, 3, 4 },
17669 // AArch64::LDUMAXH - 520
17670 {8568, 2260, 3, 4 },
17671 // AArch64::LDUMAXLB - 521
17672 {8585, 2264, 3, 4 },
17673 // AArch64::LDUMAXLH - 522
17674 {8603, 2268, 3, 4 },
17675 // AArch64::LDUMAXLW - 523
17676 {8621, 2272, 3, 4 },
17677 // AArch64::LDUMAXLX - 524
17678 {8621, 2276, 3, 4 },
17679 // AArch64::LDUMAXW - 525
17680 {8638, 2280, 3, 4 },
17681 // AArch64::LDUMAXX - 526
17682 {8638, 2284, 3, 4 },
17683 // AArch64::LDUMINB - 527
17684 {8654, 2288, 3, 4 },
17685 // AArch64::LDUMINH - 528
17686 {8671, 2292, 3, 4 },
17687 // AArch64::LDUMINLB - 529
17688 {8688, 2296, 3, 4 },
17689 // AArch64::LDUMINLH - 530
17690 {8706, 2300, 3, 4 },
17691 // AArch64::LDUMINLW - 531
17692 {8724, 2304, 3, 4 },
17693 // AArch64::LDUMINLX - 532
17694 {8724, 2308, 3, 4 },
17695 // AArch64::LDUMINW - 533
17696 {8741, 2312, 3, 4 },
17697 // AArch64::LDUMINX - 534
17698 {8741, 2316, 3, 4 },
17699 // AArch64::LDURBBi - 535
17700 {8757, 2320, 3, 3 },
17701 // AArch64::LDURBi - 536
17702 {8772, 2323, 3, 3 },
17703 // AArch64::LDURDi - 537
17704 {8772, 2326, 3, 3 },
17705 // AArch64::LDURHHi - 538
17706 {8786, 2329, 3, 3 },
17707 // AArch64::LDURHi - 539
17708 {8772, 2332, 3, 3 },
17709 // AArch64::LDURQi - 540
17710 {8772, 2335, 3, 3 },
17711 // AArch64::LDURSBWi - 541
17712 {8801, 2338, 3, 3 },
17713 // AArch64::LDURSBXi - 542
17714 {8801, 2341, 3, 3 },
17715 // AArch64::LDURSHWi - 543
17716 {8817, 2344, 3, 3 },
17717 // AArch64::LDURSHXi - 544
17718 {8817, 2347, 3, 3 },
17719 // AArch64::LDURSWi - 545
17720 {8833, 2350, 3, 3 },
17721 // AArch64::LDURSi - 546
17722 {8772, 2353, 3, 3 },
17723 // AArch64::LDURWi - 547
17724 {8772, 2356, 3, 3 },
17725 // AArch64::LDURXi - 548
17726 {8772, 2359, 3, 3 },
17727 // AArch64::MADDWrrr - 549
17728 {8849, 2362, 4, 4 },
17729 // AArch64::MADDXrrr - 550
17730 {8849, 2366, 4, 4 },
17731 // AArch64::MSUBWrrr - 551
17732 {8864, 2370, 4, 4 },
17733 // AArch64::MSUBXrrr - 552
17734 {8864, 2374, 4, 4 },
17735 // AArch64::NOTv16i8 - 553
17736 {8880, 2378, 2, 2 },
17737 // AArch64::NOTv8i8 - 554
17738 {8903, 2380, 2, 2 },
17739 // AArch64::ORNWrs - 555
17740 {8924, 2382, 4, 4 },
17741 {8935, 2386, 4, 3 },
17742 {8950, 2389, 4, 4 },
17743 // AArch64::ORNXrs - 558
17744 {8924, 2393, 4, 4 },
17745 {8935, 2397, 4, 3 },
17746 {8950, 2400, 4, 4 },
17747 // AArch64::ORRS_PPzPP - 561
17748 {8965, 2404, 4, 5 },
17749 // AArch64::ORRWrs - 562
17750 {8981, 2409, 4, 4 },
17751 {8992, 2413, 4, 4 },
17752 // AArch64::ORRXrs - 564
17753 {8981, 2417, 4, 4 },
17754 {8992, 2421, 4, 4 },
17755 // AArch64::ORR_PPzPP - 566
17756 {9007, 2425, 4, 5 },
17757 // AArch64::ORR_ZI - 567
17758 {9022, 2430, 3, 4 },
17759 {9043, 2434, 3, 4 },
17760 {9064, 2438, 3, 4 },
17761 // AArch64::ORR_ZZZ - 570
17762 {9085, 2442, 3, 4 },
17763 // AArch64::ORRv16i8 - 571
17764 {9100, 2446, 3, 3 },
17765 // AArch64::ORRv8i8 - 572
17766 {9123, 2449, 3, 3 },
17767 // AArch64::PACIA1716 - 573
17768 {9144, 2452, 0, 1 },
17769 // AArch64::PACIASP - 574
17770 {9154, 2453, 0, 1 },
17771 // AArch64::PACIAZ - 575
17772 {9162, 2454, 0, 1 },
17773 // AArch64::PACIB1716 - 576
17774 {9169, 2455, 0, 1 },
17775 // AArch64::PACIBSP - 577
17776 {9179, 2456, 0, 1 },
17777 // AArch64::PACIBZ - 578
17778 {9187, 2457, 0, 1 },
17779 // AArch64::PRFB_D_PZI - 579
17780 {9194, 2458, 4, 5 },
17781 // AArch64::PRFB_PRI - 580
17782 {9218, 2463, 4, 5 },
17783 // AArch64::PRFB_S_PZI - 581
17784 {9240, 2468, 4, 5 },
17785 // AArch64::PRFD_D_PZI - 582
17786 {9264, 2473, 4, 5 },
17787 // AArch64::PRFD_PRI - 583
17788 {9288, 2478, 4, 5 },
17789 // AArch64::PRFD_S_PZI - 584
17790 {9310, 2483, 4, 5 },
17791 // AArch64::PRFH_D_PZI - 585
17792 {9334, 2488, 4, 5 },
17793 // AArch64::PRFH_PRI - 586
17794 {9358, 2493, 4, 5 },
17795 // AArch64::PRFH_S_PZI - 587
17796 {9380, 2498, 4, 5 },
17797 // AArch64::PRFMroX - 588
17798 {9404, 2503, 5, 5 },
17799 // AArch64::PRFMui - 589
17800 {9424, 2508, 3, 3 },
17801 // AArch64::PRFUMi - 590
17802 {9440, 2511, 3, 3 },
17803 // AArch64::PRFW_D_PZI - 591
17804 {9457, 2514, 4, 5 },
17805 // AArch64::PRFW_PRI - 592
17806 {9481, 2519, 4, 5 },
17807 // AArch64::PRFW_S_PZI - 593
17808 {9503, 2524, 4, 5 },
17809 // AArch64::PTRUES_B - 594
17810 {9527, 2529, 2, 3 },
17811 // AArch64::PTRUES_D - 595
17812 {9539, 2532, 2, 3 },
17813 // AArch64::PTRUES_H - 596
17814 {9551, 2535, 2, 3 },
17815 // AArch64::PTRUES_S - 597
17816 {9563, 2538, 2, 3 },
17817 // AArch64::PTRUE_B - 598
17818 {9575, 2541, 2, 3 },
17819 // AArch64::PTRUE_D - 599
17820 {9586, 2544, 2, 3 },
17821 // AArch64::PTRUE_H - 600
17822 {9597, 2547, 2, 3 },
17823 // AArch64::PTRUE_S - 601
17824 {9608, 2550, 2, 3 },
17825 // AArch64::RET - 602
17826 {9619, 2553, 1, 1 },
17827 // AArch64::SBCSWr - 603
17828 {9623, 2554, 3, 3 },
17829 // AArch64::SBCSXr - 604
17830 {9623, 2557, 3, 3 },
17831 // AArch64::SBCWr - 605
17832 {9635, 2560, 3, 3 },
17833 // AArch64::SBCXr - 606
17834 {9635, 2563, 3, 3 },
17835 // AArch64::SBFMWri - 607
17836 {9646, 2566, 4, 4 },
17837 {9661, 2570, 4, 4 },
17838 {9673, 2574, 4, 4 },
17839 // AArch64::SBFMXri - 610
17840 {9646, 2578, 4, 4 },
17841 {9661, 2582, 4, 4 },
17842 {9673, 2586, 4, 4 },
17843 {9685, 2590, 4, 4 },
17844 // AArch64::SEL_PPPP - 614
17845 {9697, 2594, 4, 5 },
17846 // AArch64::SEL_ZPZZ_B - 615
17847 {9697, 2599, 4, 5 },
17848 // AArch64::SEL_ZPZZ_D - 616
17849 {9720, 2604, 4, 5 },
17850 // AArch64::SEL_ZPZZ_H - 617
17851 {9743, 2609, 4, 5 },
17852 // AArch64::SEL_ZPZZ_S - 618
17853 {9766, 2614, 4, 5 },
17854 // AArch64::SMADDLrrr - 619
17855 {9789, 2619, 4, 4 },
17856 // AArch64::SMSUBLrrr - 620
17857 {9806, 2623, 4, 4 },
17858 // AArch64::SQDECB_XPiI - 621
17859 {9824, 2627, 4, 5 },
17860 {9834, 2632, 4, 5 },
17861 // AArch64::SQDECB_XPiWdI - 623
17862 {9850, 2637, 4, 5 },
17863 {9866, 2642, 4, 5 },
17864 // AArch64::SQDECD_XPiI - 625
17865 {9888, 2647, 4, 5 },
17866 {9898, 2652, 4, 5 },
17867 // AArch64::SQDECD_XPiWdI - 627
17868 {9914, 2657, 4, 5 },
17869 {9930, 2662, 4, 5 },
17870 // AArch64::SQDECD_ZPiI - 629
17871 {9952, 2667, 4, 5 },
17872 {9964, 2672, 4, 5 },
17873 // AArch64::SQDECH_XPiI - 631
17874 {9982, 2677, 4, 5 },
17875 {9992, 2682, 4, 5 },
17876 // AArch64::SQDECH_XPiWdI - 633
17877 {10008, 2687, 4, 5 },
17878 {10024, 2692, 4, 5 },
17879 // AArch64::SQDECH_ZPiI - 635
17880 {10046, 2697, 4, 5 },
17881 {10058, 2702, 4, 5 },
17882 // AArch64::SQDECW_XPiI - 637
17883 {10076, 2707, 4, 5 },
17884 {10086, 2712, 4, 5 },
17885 // AArch64::SQDECW_XPiWdI - 639
17886 {10102, 2717, 4, 5 },
17887 {10118, 2722, 4, 5 },
17888 // AArch64::SQDECW_ZPiI - 641
17889 {10140, 2727, 4, 5 },
17890 {10152, 2732, 4, 5 },
17891 // AArch64::SQINCB_XPiI - 643
17892 {10170, 2737, 4, 5 },
17893 {10180, 2742, 4, 5 },
17894 // AArch64::SQINCB_XPiWdI - 645
17895 {10196, 2747, 4, 5 },
17896 {10212, 2752, 4, 5 },
17897 // AArch64::SQINCD_XPiI - 647
17898 {10234, 2757, 4, 5 },
17899 {10244, 2762, 4, 5 },
17900 // AArch64::SQINCD_XPiWdI - 649
17901 {10260, 2767, 4, 5 },
17902 {10276, 2772, 4, 5 },
17903 // AArch64::SQINCD_ZPiI - 651
17904 {10298, 2777, 4, 5 },
17905 {10310, 2782, 4, 5 },
17906 // AArch64::SQINCH_XPiI - 653
17907 {10328, 2787, 4, 5 },
17908 {10338, 2792, 4, 5 },
17909 // AArch64::SQINCH_XPiWdI - 655
17910 {10354, 2797, 4, 5 },
17911 {10370, 2802, 4, 5 },
17912 // AArch64::SQINCH_ZPiI - 657
17913 {10392, 2807, 4, 5 },
17914 {10404, 2812, 4, 5 },
17915 // AArch64::SQINCW_XPiI - 659
17916 {10422, 2817, 4, 5 },
17917 {10432, 2822, 4, 5 },
17918 // AArch64::SQINCW_XPiWdI - 661
17919 {10448, 2827, 4, 5 },
17920 {10464, 2832, 4, 5 },
17921 // AArch64::SQINCW_ZPiI - 663
17922 {10486, 2837, 4, 5 },
17923 {10498, 2842, 4, 5 },
17924 // AArch64::SST1B_D_IMM - 665
17925 {10516, 2847, 4, 5 },
17926 // AArch64::SST1B_S_IMM - 666
17927 {10540, 2852, 4, 5 },
17928 // AArch64::SST1D_IMM - 667
17929 {10564, 2857, 4, 5 },
17930 // AArch64::SST1H_D_IMM - 668
17931 {10588, 2862, 4, 5 },
17932 // AArch64::SST1H_S_IMM - 669
17933 {10612, 2867, 4, 5 },
17934 // AArch64::SST1W_D_IMM - 670
17935 {10636, 2872, 4, 5 },
17936 // AArch64::SST1W_IMM - 671
17937 {10660, 2877, 4, 5 },
17938 // AArch64::ST1B_D_IMM - 672
17939 {10684, 2882, 4, 5 },
17940 // AArch64::ST1B_H_IMM - 673
17941 {10706, 2887, 4, 5 },
17942 // AArch64::ST1B_IMM - 674
17943 {10728, 2892, 4, 5 },
17944 // AArch64::ST1B_S_IMM - 675
17945 {10750, 2897, 4, 5 },
17946 // AArch64::ST1D_IMM - 676
17947 {10772, 2902, 4, 5 },
17948 // AArch64::ST1Fourv16b_POST - 677
17949 {10794, 2907, 4, 5 },
17950 // AArch64::ST1Fourv1d_POST - 678
17951 {10814, 2912, 4, 5 },
17952 // AArch64::ST1Fourv2d_POST - 679
17953 {10834, 2917, 4, 5 },
17954 // AArch64::ST1Fourv2s_POST - 680
17955 {10854, 2922, 4, 5 },
17956 // AArch64::ST1Fourv4h_POST - 681
17957 {10874, 2927, 4, 5 },
17958 // AArch64::ST1Fourv4s_POST - 682
17959 {10894, 2932, 4, 5 },
17960 // AArch64::ST1Fourv8b_POST - 683
17961 {10914, 2937, 4, 5 },
17962 // AArch64::ST1Fourv8h_POST - 684
17963 {10934, 2942, 4, 5 },
17964 // AArch64::ST1H_D_IMM - 685
17965 {10954, 2947, 4, 5 },
17966 // AArch64::ST1H_IMM - 686
17967 {10976, 2952, 4, 5 },
17968 // AArch64::ST1H_S_IMM - 687
17969 {10998, 2957, 4, 5 },
17970 // AArch64::ST1Onev16b_POST - 688
17971 {11020, 2962, 4, 5 },
17972 // AArch64::ST1Onev1d_POST - 689
17973 {11040, 2967, 4, 5 },
17974 // AArch64::ST1Onev2d_POST - 690
17975 {11059, 2972, 4, 5 },
17976 // AArch64::ST1Onev2s_POST - 691
17977 {11079, 2977, 4, 5 },
17978 // AArch64::ST1Onev4h_POST - 692
17979 {11098, 2982, 4, 5 },
17980 // AArch64::ST1Onev4s_POST - 693
17981 {11117, 2987, 4, 5 },
17982 // AArch64::ST1Onev8b_POST - 694
17983 {11137, 2992, 4, 5 },
17984 // AArch64::ST1Onev8h_POST - 695
17985 {11156, 2997, 4, 5 },
17986 // AArch64::ST1Threev16b_POST - 696
17987 {11176, 3002, 4, 5 },
17988 // AArch64::ST1Threev1d_POST - 697
17989 {11196, 3007, 4, 5 },
17990 // AArch64::ST1Threev2d_POST - 698
17991 {11216, 3012, 4, 5 },
17992 // AArch64::ST1Threev2s_POST - 699
17993 {11236, 3017, 4, 5 },
17994 // AArch64::ST1Threev4h_POST - 700
17995 {11256, 3022, 4, 5 },
17996 // AArch64::ST1Threev4s_POST - 701
17997 {11276, 3027, 4, 5 },
17998 // AArch64::ST1Threev8b_POST - 702
17999 {11296, 3032, 4, 5 },
18000 // AArch64::ST1Threev8h_POST - 703
18001 {11316, 3037, 4, 5 },
18002 // AArch64::ST1Twov16b_POST - 704
18003 {11336, 3042, 4, 5 },
18004 // AArch64::ST1Twov1d_POST - 705
18005 {11356, 3047, 4, 5 },
18006 // AArch64::ST1Twov2d_POST - 706
18007 {11376, 3052, 4, 5 },
18008 // AArch64::ST1Twov2s_POST - 707
18009 {11396, 3057, 4, 5 },
18010 // AArch64::ST1Twov4h_POST - 708
18011 {11416, 3062, 4, 5 },
18012 // AArch64::ST1Twov4s_POST - 709
18013 {11436, 3067, 4, 5 },
18014 // AArch64::ST1Twov8b_POST - 710
18015 {11456, 3072, 4, 5 },
18016 // AArch64::ST1Twov8h_POST - 711
18017 {11476, 3077, 4, 5 },
18018 // AArch64::ST1W_D_IMM - 712
18019 {11496, 3082, 4, 5 },
18020 // AArch64::ST1W_IMM - 713
18021 {11518, 3087, 4, 5 },
18022 // AArch64::ST1i16_POST - 714
18023 {11540, 3092, 5, 6 },
18024 // AArch64::ST1i32_POST - 715
18025 {11563, 3098, 5, 6 },
18026 // AArch64::ST1i64_POST - 716
18027 {11586, 3104, 5, 6 },
18028 // AArch64::ST1i8_POST - 717
18029 {11609, 3110, 5, 6 },
18030 // AArch64::ST2B_IMM - 718
18031 {11632, 3116, 4, 5 },
18032 // AArch64::ST2D_IMM - 719
18033 {11654, 3121, 4, 5 },
18034 // AArch64::ST2GOffset - 720
18035 {11676, 3126, 3, 4 },
18036 // AArch64::ST2H_IMM - 721
18037 {11690, 3130, 4, 5 },
18038 // AArch64::ST2Twov16b_POST - 722
18039 {11712, 3135, 4, 5 },
18040 // AArch64::ST2Twov2d_POST - 723
18041 {11732, 3140, 4, 5 },
18042 // AArch64::ST2Twov2s_POST - 724
18043 {11752, 3145, 4, 5 },
18044 // AArch64::ST2Twov4h_POST - 725
18045 {11772, 3150, 4, 5 },
18046 // AArch64::ST2Twov4s_POST - 726
18047 {11792, 3155, 4, 5 },
18048 // AArch64::ST2Twov8b_POST - 727
18049 {11812, 3160, 4, 5 },
18050 // AArch64::ST2Twov8h_POST - 728
18051 {11832, 3165, 4, 5 },
18052 // AArch64::ST2W_IMM - 729
18053 {11852, 3170, 4, 5 },
18054 // AArch64::ST2i16_POST - 730
18055 {11874, 3175, 5, 6 },
18056 // AArch64::ST2i32_POST - 731
18057 {11897, 3181, 5, 6 },
18058 // AArch64::ST2i64_POST - 732
18059 {11920, 3187, 5, 6 },
18060 // AArch64::ST2i8_POST - 733
18061 {11944, 3193, 5, 6 },
18062 // AArch64::ST3B_IMM - 734
18063 {11967, 3199, 4, 5 },
18064 // AArch64::ST3D_IMM - 735
18065 {11989, 3204, 4, 5 },
18066 // AArch64::ST3H_IMM - 736
18067 {12011, 3209, 4, 5 },
18068 // AArch64::ST3Threev16b_POST - 737
18069 {12033, 3214, 4, 5 },
18070 // AArch64::ST3Threev2d_POST - 738
18071 {12053, 3219, 4, 5 },
18072 // AArch64::ST3Threev2s_POST - 739
18073 {12073, 3224, 4, 5 },
18074 // AArch64::ST3Threev4h_POST - 740
18075 {12093, 3229, 4, 5 },
18076 // AArch64::ST3Threev4s_POST - 741
18077 {12113, 3234, 4, 5 },
18078 // AArch64::ST3Threev8b_POST - 742
18079 {12133, 3239, 4, 5 },
18080 // AArch64::ST3Threev8h_POST - 743
18081 {12153, 3244, 4, 5 },
18082 // AArch64::ST3W_IMM - 744
18083 {12173, 3249, 4, 5 },
18084 // AArch64::ST3i16_POST - 745
18085 {12195, 3254, 5, 6 },
18086 // AArch64::ST3i32_POST - 746
18087 {12218, 3260, 5, 6 },
18088 // AArch64::ST3i64_POST - 747
18089 {12242, 3266, 5, 6 },
18090 // AArch64::ST3i8_POST - 748
18091 {12266, 3272, 5, 6 },
18092 // AArch64::ST4B_IMM - 749
18093 {12289, 3278, 4, 5 },
18094 // AArch64::ST4D_IMM - 750
18095 {12311, 3283, 4, 5 },
18096 // AArch64::ST4Fourv16b_POST - 751
18097 {12333, 3288, 4, 5 },
18098 // AArch64::ST4Fourv2d_POST - 752
18099 {12353, 3293, 4, 5 },
18100 // AArch64::ST4Fourv2s_POST - 753
18101 {12373, 3298, 4, 5 },
18102 // AArch64::ST4Fourv4h_POST - 754
18103 {12393, 3303, 4, 5 },
18104 // AArch64::ST4Fourv4s_POST - 755
18105 {12413, 3308, 4, 5 },
18106 // AArch64::ST4Fourv8b_POST - 756
18107 {12433, 3313, 4, 5 },
18108 // AArch64::ST4Fourv8h_POST - 757
18109 {12453, 3318, 4, 5 },
18110 // AArch64::ST4H_IMM - 758
18111 {12473, 3323, 4, 5 },
18112 // AArch64::ST4W_IMM - 759
18113 {12495, 3328, 4, 5 },
18114 // AArch64::ST4i16_POST - 760
18115 {12517, 3333, 5, 6 },
18116 // AArch64::ST4i32_POST - 761
18117 {12540, 3339, 5, 6 },
18118 // AArch64::ST4i64_POST - 762
18119 {12564, 3345, 5, 6 },
18120 // AArch64::ST4i8_POST - 763
18121 {12588, 3351, 5, 6 },
18122 // AArch64::STGOffset - 764
18123 {12611, 3357, 3, 4 },
18124 // AArch64::STGPi - 765
18125 {12624, 3361, 4, 5 },
18126 // AArch64::STLURBi - 766
18127 {12642, 3366, 3, 4 },
18128 // AArch64::STLURHi - 767
18129 {12658, 3370, 3, 4 },
18130 // AArch64::STLURWi - 768
18131 {12674, 3374, 3, 4 },
18132 // AArch64::STLURXi - 769
18133 {12674, 3378, 3, 4 },
18134 // AArch64::STNPDi - 770
18135 {12689, 3382, 4, 4 },
18136 // AArch64::STNPQi - 771
18137 {12689, 3386, 4, 4 },
18138 // AArch64::STNPSi - 772
18139 {12689, 3390, 4, 4 },
18140 // AArch64::STNPWi - 773
18141 {12689, 3394, 4, 4 },
18142 // AArch64::STNPXi - 774
18143 {12689, 3398, 4, 4 },
18144 // AArch64::STNT1B_ZRI - 775
18145 {12707, 3402, 4, 5 },
18146 // AArch64::STNT1B_ZZR_D_REAL - 776
18147 {12731, 3407, 4, 5 },
18148 // AArch64::STNT1B_ZZR_S_REAL - 777
18149 {12757, 3412, 4, 5 },
18150 // AArch64::STNT1D_ZRI - 778
18151 {12783, 3417, 4, 5 },
18152 // AArch64::STNT1D_ZZR_D_REAL - 779
18153 {12807, 3422, 4, 5 },
18154 // AArch64::STNT1H_ZRI - 780
18155 {12833, 3427, 4, 5 },
18156 // AArch64::STNT1H_ZZR_D_REAL - 781
18157 {12857, 3432, 4, 5 },
18158 // AArch64::STNT1H_ZZR_S_REAL - 782
18159 {12883, 3437, 4, 5 },
18160 // AArch64::STNT1W_ZRI - 783
18161 {12909, 3442, 4, 5 },
18162 // AArch64::STNT1W_ZZR_D_REAL - 784
18163 {12933, 3447, 4, 5 },
18164 // AArch64::STNT1W_ZZR_S_REAL - 785
18165 {12959, 3452, 4, 5 },
18166 // AArch64::STPDi - 786
18167 {12985, 3457, 4, 4 },
18168 // AArch64::STPQi - 787
18169 {12985, 3461, 4, 4 },
18170 // AArch64::STPSi - 788
18171 {12985, 3465, 4, 4 },
18172 // AArch64::STPWi - 789
18173 {12985, 3469, 4, 4 },
18174 // AArch64::STPXi - 790
18175 {12985, 3473, 4, 4 },
18176 // AArch64::STRBBroX - 791
18177 {13002, 3477, 5, 5 },
18178 // AArch64::STRBBui - 792
18179 {13020, 3482, 3, 3 },
18180 // AArch64::STRBroX - 793
18181 {13034, 3485, 5, 5 },
18182 // AArch64::STRBui - 794
18183 {13051, 3490, 3, 3 },
18184 // AArch64::STRDroX - 795
18185 {13034, 3493, 5, 5 },
18186 // AArch64::STRDui - 796
18187 {13051, 3498, 3, 3 },
18188 // AArch64::STRHHroX - 797
18189 {13064, 3501, 5, 5 },
18190 // AArch64::STRHHui - 798
18191 {13082, 3506, 3, 3 },
18192 // AArch64::STRHroX - 799
18193 {13034, 3509, 5, 5 },
18194 // AArch64::STRHui - 800
18195 {13051, 3514, 3, 3 },
18196 // AArch64::STRQroX - 801
18197 {13034, 3517, 5, 5 },
18198 // AArch64::STRQui - 802
18199 {13051, 3522, 3, 3 },
18200 // AArch64::STRSroX - 803
18201 {13034, 3525, 5, 5 },
18202 // AArch64::STRSui - 804
18203 {13051, 3530, 3, 3 },
18204 // AArch64::STRWroX - 805
18205 {13034, 3533, 5, 5 },
18206 // AArch64::STRWui - 806
18207 {13051, 3538, 3, 3 },
18208 // AArch64::STRXroX - 807
18209 {13034, 3541, 5, 5 },
18210 // AArch64::STRXui - 808
18211 {13051, 3546, 3, 3 },
18212 // AArch64::STR_PXI - 809
18213 {13096, 3549, 3, 4 },
18214 // AArch64::STR_ZXI - 810
18215 {13096, 3553, 3, 4 },
18216 // AArch64::STTRBi - 811
18217 {13111, 3557, 3, 3 },
18218 // AArch64::STTRHi - 812
18219 {13126, 3560, 3, 3 },
18220 // AArch64::STTRWi - 813
18221 {13141, 3563, 3, 3 },
18222 // AArch64::STTRXi - 814
18223 {13141, 3566, 3, 3 },
18224 // AArch64::STURBBi - 815
18225 {13155, 3569, 3, 3 },
18226 // AArch64::STURBi - 816
18227 {13170, 3572, 3, 3 },
18228 // AArch64::STURDi - 817
18229 {13170, 3575, 3, 3 },
18230 // AArch64::STURHHi - 818
18231 {13184, 3578, 3, 3 },
18232 // AArch64::STURHi - 819
18233 {13170, 3581, 3, 3 },
18234 // AArch64::STURQi - 820
18235 {13170, 3584, 3, 3 },
18236 // AArch64::STURSi - 821
18237 {13170, 3587, 3, 3 },
18238 // AArch64::STURWi - 822
18239 {13170, 3590, 3, 3 },
18240 // AArch64::STURXi - 823
18241 {13170, 3593, 3, 3 },
18242 // AArch64::STZ2GOffset - 824
18243 {13199, 3596, 3, 4 },
18244 // AArch64::STZGOffset - 825
18245 {13214, 3600, 3, 4 },
18246 // AArch64::SUBSWri - 826
18247 {13228, 3604, 4, 2 },
18248 // AArch64::SUBSWrs - 827
18249 {13241, 3606, 4, 4 },
18250 {13252, 3610, 4, 3 },
18251 {13267, 3613, 4, 4 },
18252 {13279, 3617, 4, 3 },
18253 {13295, 3620, 4, 4 },
18254 // AArch64::SUBSWrx - 832
18255 {13241, 3624, 4, 4 },
18256 {13311, 3628, 4, 3 },
18257 {13295, 3631, 4, 4 },
18258 // AArch64::SUBSXri - 835
18259 {13228, 3635, 4, 2 },
18260 // AArch64::SUBSXrs - 836
18261 {13241, 3637, 4, 4 },
18262 {13252, 3641, 4, 3 },
18263 {13267, 3644, 4, 4 },
18264 {13279, 3648, 4, 3 },
18265 {13295, 3651, 4, 4 },
18266 // AArch64::SUBSXrx - 841
18267 {13311, 3655, 4, 3 },
18268 // AArch64::SUBSXrx64 - 842
18269 {13241, 3658, 4, 4 },
18270 {13311, 3662, 4, 3 },
18271 {13295, 3665, 4, 4 },
18272 // AArch64::SUBWrs - 845
18273 {13326, 3669, 4, 4 },
18274 {13337, 3673, 4, 3 },
18275 {13352, 3676, 4, 4 },
18276 // AArch64::SUBWrx - 848
18277 {13352, 3680, 4, 4 },
18278 {13352, 3684, 4, 4 },
18279 // AArch64::SUBXrs - 850
18280 {13326, 3688, 4, 4 },
18281 {13337, 3692, 4, 3 },
18282 {13352, 3695, 4, 4 },
18283 // AArch64::SUBXrx64 - 853
18284 {13352, 3699, 4, 4 },
18285 {13352, 3703, 4, 4 },
18286 // AArch64::SYSxt - 855
18287 {13367, 3707, 5, 5 },
18288 // AArch64::UBFMWri - 856
18289 {13390, 3712, 4, 4 },
18290 {13405, 3716, 4, 4 },
18291 {13417, 3720, 4, 4 },
18292 // AArch64::UBFMXri - 859
18293 {13390, 3724, 4, 4 },
18294 {13405, 3728, 4, 4 },
18295 {13417, 3732, 4, 4 },
18296 {13429, 3736, 4, 4 },
18297 // AArch64::UMADDLrrr - 863
18298 {13441, 3740, 4, 4 },
18299 // AArch64::UMOVvi32 - 864
18300 {13458, 3744, 3, 3 },
18301 // AArch64::UMOVvi64 - 865
18302 {13477, 3747, 3, 3 },
18303 // AArch64::UMSUBLrrr - 866
18304 {13496, 3750, 4, 4 },
18305 // AArch64::UQDECB_WPiI - 867
18306 {13514, 3754, 4, 5 },
18307 {13524, 3759, 4, 5 },
18308 // AArch64::UQDECB_XPiI - 869
18309 {13514, 3764, 4, 5 },
18310 {13524, 3769, 4, 5 },
18311 // AArch64::UQDECD_WPiI - 871
18312 {13540, 3774, 4, 5 },
18313 {13550, 3779, 4, 5 },
18314 // AArch64::UQDECD_XPiI - 873
18315 {13540, 3784, 4, 5 },
18316 {13550, 3789, 4, 5 },
18317 // AArch64::UQDECD_ZPiI - 875
18318 {13566, 3794, 4, 5 },
18319 {13578, 3799, 4, 5 },
18320 // AArch64::UQDECH_WPiI - 877
18321 {13596, 3804, 4, 5 },
18322 {13606, 3809, 4, 5 },
18323 // AArch64::UQDECH_XPiI - 879
18324 {13596, 3814, 4, 5 },
18325 {13606, 3819, 4, 5 },
18326 // AArch64::UQDECH_ZPiI - 881
18327 {13622, 3824, 4, 5 },
18328 {13634, 3829, 4, 5 },
18329 // AArch64::UQDECW_WPiI - 883
18330 {13652, 3834, 4, 5 },
18331 {13662, 3839, 4, 5 },
18332 // AArch64::UQDECW_XPiI - 885
18333 {13652, 3844, 4, 5 },
18334 {13662, 3849, 4, 5 },
18335 // AArch64::UQDECW_ZPiI - 887
18336 {13678, 3854, 4, 5 },
18337 {13690, 3859, 4, 5 },
18338 // AArch64::UQINCB_WPiI - 889
18339 {13708, 3864, 4, 5 },
18340 {13718, 3869, 4, 5 },
18341 // AArch64::UQINCB_XPiI - 891
18342 {13708, 3874, 4, 5 },
18343 {13718, 3879, 4, 5 },
18344 // AArch64::UQINCD_WPiI - 893
18345 {13734, 3884, 4, 5 },
18346 {13744, 3889, 4, 5 },
18347 // AArch64::UQINCD_XPiI - 895
18348 {13734, 3894, 4, 5 },
18349 {13744, 3899, 4, 5 },
18350 // AArch64::UQINCD_ZPiI - 897
18351 {13760, 3904, 4, 5 },
18352 {13772, 3909, 4, 5 },
18353 // AArch64::UQINCH_WPiI - 899
18354 {13790, 3914, 4, 5 },
18355 {13800, 3919, 4, 5 },
18356 // AArch64::UQINCH_XPiI - 901
18357 {13790, 3924, 4, 5 },
18358 {13800, 3929, 4, 5 },
18359 // AArch64::UQINCH_ZPiI - 903
18360 {13816, 3934, 4, 5 },
18361 {13828, 3939, 4, 5 },
18362 // AArch64::UQINCW_WPiI - 905
18363 {13846, 3944, 4, 5 },
18364 {13856, 3949, 4, 5 },
18365 // AArch64::UQINCW_XPiI - 907
18366 {13846, 3954, 4, 5 },
18367 {13856, 3959, 4, 5 },
18368 // AArch64::UQINCW_ZPiI - 909
18369 {13872, 3964, 4, 5 },
18370 {13884, 3969, 4, 5 },
18371 // AArch64::XPACLRI - 911
18372 {13902, 3974, 0, 1 },
18373 };
18374
18375 static const AliasPatternCond Conds[] = {
18376 // (ADDSWri WZR, GPR32sp:$src, addsub_shifted_imm32:$imm) - 0
18377 {AliasPatternCond::K_Reg, AArch64::WZR},
18378 {AliasPatternCond::K_RegClass, AArch64::GPR32spRegClassID},
18379 // (ADDSWrs WZR, GPR32:$src1, GPR32:$src2, 0) - 2
18380 {AliasPatternCond::K_Reg, AArch64::WZR},
18381 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
18382 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
18383 {AliasPatternCond::K_Imm, uint32_t(0)},
18384 // (ADDSWrs WZR, GPR32:$src1, GPR32:$src2, arith_shift32:$sh) - 6
18385 {AliasPatternCond::K_Reg, AArch64::WZR},
18386 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
18387 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
18388 // (ADDSWrs GPR32:$dst, GPR32:$src1, GPR32:$src2, 0) - 9
18389 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
18390 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
18391 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
18392 {AliasPatternCond::K_Imm, uint32_t(0)},
18393 // (ADDSWrx WZR, GPR32sponly:$src1, GPR32:$src2, 16) - 13
18394 {AliasPatternCond::K_Reg, AArch64::WZR},
18395 {AliasPatternCond::K_RegClass, AArch64::GPR32sponlyRegClassID},
18396 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
18397 {AliasPatternCond::K_Imm, uint32_t(16)},
18398 // (ADDSWrx WZR, GPR32sp:$src1, GPR32:$src2, arith_extend:$sh) - 17
18399 {AliasPatternCond::K_Reg, AArch64::WZR},
18400 {AliasPatternCond::K_RegClass, AArch64::GPR32spRegClassID},
18401 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
18402 // (ADDSWrx GPR32:$dst, GPR32sponly:$src1, GPR32:$src2, 16) - 20
18403 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
18404 {AliasPatternCond::K_RegClass, AArch64::GPR32sponlyRegClassID},
18405 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
18406 {AliasPatternCond::K_Imm, uint32_t(16)},
18407 // (ADDSXri XZR, GPR64sp:$src, addsub_shifted_imm64:$imm) - 24
18408 {AliasPatternCond::K_Reg, AArch64::XZR},
18409 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
18410 // (ADDSXrs XZR, GPR64:$src1, GPR64:$src2, 0) - 26
18411 {AliasPatternCond::K_Reg, AArch64::XZR},
18412 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
18413 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
18414 {AliasPatternCond::K_Imm, uint32_t(0)},
18415 // (ADDSXrs XZR, GPR64:$src1, GPR64:$src2, arith_shift64:$sh) - 30
18416 {AliasPatternCond::K_Reg, AArch64::XZR},
18417 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
18418 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
18419 // (ADDSXrs GPR64:$dst, GPR64:$src1, GPR64:$src2, 0) - 33
18420 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
18421 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
18422 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
18423 {AliasPatternCond::K_Imm, uint32_t(0)},
18424 // (ADDSXrx XZR, GPR64sp:$src1, GPR32:$src2, arith_extend:$sh) - 37
18425 {AliasPatternCond::K_Reg, AArch64::XZR},
18426 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
18427 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
18428 // (ADDSXrx64 XZR, GPR64sponly:$src1, GPR64:$src2, 24) - 40
18429 {AliasPatternCond::K_Reg, AArch64::XZR},
18430 {AliasPatternCond::K_RegClass, AArch64::GPR64sponlyRegClassID},
18431 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
18432 {AliasPatternCond::K_Imm, uint32_t(24)},
18433 // (ADDSXrx64 XZR, GPR64sp:$src1, GPR64:$src2, arith_extendlsl64:$sh) - 44
18434 {AliasPatternCond::K_Reg, AArch64::XZR},
18435 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
18436 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
18437 // (ADDSXrx64 GPR64:$dst, GPR64sponly:$src1, GPR64:$src2, 24) - 47
18438 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
18439 {AliasPatternCond::K_RegClass, AArch64::GPR64sponlyRegClassID},
18440 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
18441 {AliasPatternCond::K_Imm, uint32_t(24)},
18442 // (ADDWri GPR32sponly:$dst, GPR32sp:$src, 0, 0) - 51
18443 {AliasPatternCond::K_RegClass, AArch64::GPR32sponlyRegClassID},
18444 {AliasPatternCond::K_RegClass, AArch64::GPR32spRegClassID},
18445 {AliasPatternCond::K_Imm, uint32_t(0)},
18446 {AliasPatternCond::K_Imm, uint32_t(0)},
18447 // (ADDWri GPR32sp:$dst, GPR32sponly:$src, 0, 0) - 55
18448 {AliasPatternCond::K_RegClass, AArch64::GPR32spRegClassID},
18449 {AliasPatternCond::K_RegClass, AArch64::GPR32sponlyRegClassID},
18450 {AliasPatternCond::K_Imm, uint32_t(0)},
18451 {AliasPatternCond::K_Imm, uint32_t(0)},
18452 // (ADDWrs GPR32:$dst, GPR32:$src1, GPR32:$src2, 0) - 59
18453 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
18454 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
18455 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
18456 {AliasPatternCond::K_Imm, uint32_t(0)},
18457 // (ADDWrx GPR32sponly:$dst, GPR32sp:$src1, GPR32:$src2, 16) - 63
18458 {AliasPatternCond::K_RegClass, AArch64::GPR32sponlyRegClassID},
18459 {AliasPatternCond::K_RegClass, AArch64::GPR32spRegClassID},
18460 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
18461 {AliasPatternCond::K_Imm, uint32_t(16)},
18462 // (ADDWrx GPR32sp:$dst, GPR32sponly:$src1, GPR32:$src2, 16) - 67
18463 {AliasPatternCond::K_RegClass, AArch64::GPR32spRegClassID},
18464 {AliasPatternCond::K_RegClass, AArch64::GPR32sponlyRegClassID},
18465 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
18466 {AliasPatternCond::K_Imm, uint32_t(16)},
18467 // (ADDXri GPR64sponly:$dst, GPR64sp:$src, 0, 0) - 71
18468 {AliasPatternCond::K_RegClass, AArch64::GPR64sponlyRegClassID},
18469 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
18470 {AliasPatternCond::K_Imm, uint32_t(0)},
18471 {AliasPatternCond::K_Imm, uint32_t(0)},
18472 // (ADDXri GPR64sp:$dst, GPR64sponly:$src, 0, 0) - 75
18473 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
18474 {AliasPatternCond::K_RegClass, AArch64::GPR64sponlyRegClassID},
18475 {AliasPatternCond::K_Imm, uint32_t(0)},
18476 {AliasPatternCond::K_Imm, uint32_t(0)},
18477 // (ADDXrs GPR64:$dst, GPR64:$src1, GPR64:$src2, 0) - 79
18478 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
18479 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
18480 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
18481 {AliasPatternCond::K_Imm, uint32_t(0)},
18482 // (ADDXrx64 GPR64sponly:$dst, GPR64sp:$src1, GPR64:$src2, 24) - 83
18483 {AliasPatternCond::K_RegClass, AArch64::GPR64sponlyRegClassID},
18484 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
18485 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
18486 {AliasPatternCond::K_Imm, uint32_t(24)},
18487 // (ADDXrx64 GPR64sp:$dst, GPR64sponly:$src1, GPR64:$src2, 24) - 87
18488 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
18489 {AliasPatternCond::K_RegClass, AArch64::GPR64sponlyRegClassID},
18490 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
18491 {AliasPatternCond::K_Imm, uint32_t(24)},
18492 // (ANDSWri WZR, GPR32:$src1, logical_imm32:$src2) - 91
18493 {AliasPatternCond::K_Reg, AArch64::WZR},
18494 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
18495 // (ANDSWrs WZR, GPR32:$src1, GPR32:$src2, 0) - 93
18496 {AliasPatternCond::K_Reg, AArch64::WZR},
18497 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
18498 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
18499 {AliasPatternCond::K_Imm, uint32_t(0)},
18500 // (ANDSWrs WZR, GPR32:$src1, GPR32:$src2, logical_shift32:$sh) - 97
18501 {AliasPatternCond::K_Reg, AArch64::WZR},
18502 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
18503 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
18504 // (ANDSWrs GPR32:$dst, GPR32:$src1, GPR32:$src2, 0) - 100
18505 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
18506 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
18507 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
18508 {AliasPatternCond::K_Imm, uint32_t(0)},
18509 // (ANDSXri XZR, GPR64:$src1, logical_imm64:$src2) - 104
18510 {AliasPatternCond::K_Reg, AArch64::XZR},
18511 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
18512 // (ANDSXrs XZR, GPR64:$src1, GPR64:$src2, 0) - 106
18513 {AliasPatternCond::K_Reg, AArch64::XZR},
18514 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
18515 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
18516 {AliasPatternCond::K_Imm, uint32_t(0)},
18517 // (ANDSXrs XZR, GPR64:$src1, GPR64:$src2, logical_shift64:$sh) - 110
18518 {AliasPatternCond::K_Reg, AArch64::XZR},
18519 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
18520 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
18521 // (ANDSXrs GPR64:$dst, GPR64:$src1, GPR64:$src2, 0) - 113
18522 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
18523 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
18524 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
18525 {AliasPatternCond::K_Imm, uint32_t(0)},
18526 // (ANDS_PPzPP PPR8:$Pd, PPRAny:$Pg, PPR8:$Pn, PPR8:$Pn) - 117
18527 {AliasPatternCond::K_RegClass, AArch64::PPRRegClassID},
18528 {AliasPatternCond::K_RegClass, AArch64::PPRRegClassID},
18529 {AliasPatternCond::K_RegClass, AArch64::PPRRegClassID},
18530 {AliasPatternCond::K_TiedReg, 2},
18531 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
18532 // (ANDWrs GPR32:$dst, GPR32:$src1, GPR32:$src2, 0) - 122
18533 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
18534 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
18535 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
18536 {AliasPatternCond::K_Imm, uint32_t(0)},
18537 // (ANDXrs GPR64:$dst, GPR64:$src1, GPR64:$src2, 0) - 126
18538 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
18539 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
18540 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
18541 {AliasPatternCond::K_Imm, uint32_t(0)},
18542 // (AND_PPzPP PPR8:$Pd, PPRAny:$Pg, PPR8:$Pn, PPR8:$Pn) - 130
18543 {AliasPatternCond::K_RegClass, AArch64::PPRRegClassID},
18544 {AliasPatternCond::K_RegClass, AArch64::PPRRegClassID},
18545 {AliasPatternCond::K_RegClass, AArch64::PPRRegClassID},
18546 {AliasPatternCond::K_TiedReg, 2},
18547 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
18548 // (AND_ZI ZPR8:$Zdn, sve_logical_imm8:$imm) - 135
18549 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
18550 {AliasPatternCond::K_Ignore, 0},
18551 {AliasPatternCond::K_Custom, 1},
18552 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
18553 // (AND_ZI ZPR16:$Zdn, sve_logical_imm16:$imm) - 139
18554 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
18555 {AliasPatternCond::K_Ignore, 0},
18556 {AliasPatternCond::K_Custom, 2},
18557 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
18558 // (AND_ZI ZPR32:$Zdn, sve_logical_imm32:$imm) - 143
18559 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
18560 {AliasPatternCond::K_Ignore, 0},
18561 {AliasPatternCond::K_Custom, 3},
18562 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
18563 // (AUTIA1716) - 147
18564 {AliasPatternCond::K_Feature, AArch64::FeaturePAuth},
18565 // (AUTIASP) - 148
18566 {AliasPatternCond::K_Feature, AArch64::FeaturePAuth},
18567 // (AUTIAZ) - 149
18568 {AliasPatternCond::K_Feature, AArch64::FeaturePAuth},
18569 // (AUTIB1716) - 150
18570 {AliasPatternCond::K_Feature, AArch64::FeaturePAuth},
18571 // (AUTIBSP) - 151
18572 {AliasPatternCond::K_Feature, AArch64::FeaturePAuth},
18573 // (AUTIBZ) - 152
18574 {AliasPatternCond::K_Feature, AArch64::FeaturePAuth},
18575 // (BICSWrs GPR32:$dst, GPR32:$src1, GPR32:$src2, 0) - 153
18576 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
18577 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
18578 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
18579 {AliasPatternCond::K_Imm, uint32_t(0)},
18580 // (BICSXrs GPR64:$dst, GPR64:$src1, GPR64:$src2, 0) - 157
18581 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
18582 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
18583 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
18584 {AliasPatternCond::K_Imm, uint32_t(0)},
18585 // (BICWrs GPR32:$dst, GPR32:$src1, GPR32:$src2, 0) - 161
18586 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
18587 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
18588 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
18589 {AliasPatternCond::K_Imm, uint32_t(0)},
18590 // (BICXrs GPR64:$dst, GPR64:$src1, GPR64:$src2, 0) - 165
18591 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
18592 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
18593 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
18594 {AliasPatternCond::K_Imm, uint32_t(0)},
18595 // (CLREX 15) - 169
18596 {AliasPatternCond::K_Imm, uint32_t(15)},
18597 // (CNTB_XPiI GPR64:$Rd, { 1, 1, 1, 1, 1 }, 1) - 170
18598 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
18599 {AliasPatternCond::K_Imm, uint32_t(31)},
18600 {AliasPatternCond::K_Imm, uint32_t(1)},
18601 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
18602 // (CNTB_XPiI GPR64:$Rd, sve_pred_enum:$pattern, 1) - 174
18603 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
18604 {AliasPatternCond::K_Ignore, 0},
18605 {AliasPatternCond::K_Imm, uint32_t(1)},
18606 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
18607 // (CNTD_XPiI GPR64:$Rd, { 1, 1, 1, 1, 1 }, 1) - 178
18608 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
18609 {AliasPatternCond::K_Imm, uint32_t(31)},
18610 {AliasPatternCond::K_Imm, uint32_t(1)},
18611 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
18612 // (CNTD_XPiI GPR64:$Rd, sve_pred_enum:$pattern, 1) - 182
18613 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
18614 {AliasPatternCond::K_Ignore, 0},
18615 {AliasPatternCond::K_Imm, uint32_t(1)},
18616 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
18617 // (CNTH_XPiI GPR64:$Rd, { 1, 1, 1, 1, 1 }, 1) - 186
18618 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
18619 {AliasPatternCond::K_Imm, uint32_t(31)},
18620 {AliasPatternCond::K_Imm, uint32_t(1)},
18621 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
18622 // (CNTH_XPiI GPR64:$Rd, sve_pred_enum:$pattern, 1) - 190
18623 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
18624 {AliasPatternCond::K_Ignore, 0},
18625 {AliasPatternCond::K_Imm, uint32_t(1)},
18626 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
18627 // (CNTW_XPiI GPR64:$Rd, { 1, 1, 1, 1, 1 }, 1) - 194
18628 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
18629 {AliasPatternCond::K_Imm, uint32_t(31)},
18630 {AliasPatternCond::K_Imm, uint32_t(1)},
18631 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
18632 // (CNTW_XPiI GPR64:$Rd, sve_pred_enum:$pattern, 1) - 198
18633 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
18634 {AliasPatternCond::K_Ignore, 0},
18635 {AliasPatternCond::K_Imm, uint32_t(1)},
18636 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
18637 // (CPY_ZPmI_B ZPR8:$Zd, PPRAny:$Pg, cpy_imm8_opt_lsl_i8:$imm) - 202
18638 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
18639 {AliasPatternCond::K_Ignore, 0},
18640 {AliasPatternCond::K_RegClass, AArch64::PPRRegClassID},
18641 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
18642 // (CPY_ZPmI_D ZPR64:$Zd, PPRAny:$Pg, cpy_imm8_opt_lsl_i64:$imm) - 206
18643 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
18644 {AliasPatternCond::K_Ignore, 0},
18645 {AliasPatternCond::K_RegClass, AArch64::PPRRegClassID},
18646 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
18647 // (CPY_ZPmI_H ZPR16:$Zd, PPRAny:$Pg, cpy_imm8_opt_lsl_i16:$imm) - 210
18648 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
18649 {AliasPatternCond::K_Ignore, 0},
18650 {AliasPatternCond::K_RegClass, AArch64::PPRRegClassID},
18651 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
18652 // (CPY_ZPmI_S ZPR32:$Zd, PPRAny:$Pg, cpy_imm8_opt_lsl_i32:$imm) - 214
18653 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
18654 {AliasPatternCond::K_Ignore, 0},
18655 {AliasPatternCond::K_RegClass, AArch64::PPRRegClassID},
18656 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
18657 // (CPY_ZPmR_B ZPR8:$Zd, PPR3bAny:$Pg, GPR32sp:$Rn) - 218
18658 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
18659 {AliasPatternCond::K_Ignore, 0},
18660 {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID},
18661 {AliasPatternCond::K_RegClass, AArch64::GPR32spRegClassID},
18662 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
18663 // (CPY_ZPmR_D ZPR64:$Zd, PPR3bAny:$Pg, GPR64sp:$Rn) - 223
18664 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
18665 {AliasPatternCond::K_Ignore, 0},
18666 {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID},
18667 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
18668 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
18669 // (CPY_ZPmR_H ZPR16:$Zd, PPR3bAny:$Pg, GPR32sp:$Rn) - 228
18670 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
18671 {AliasPatternCond::K_Ignore, 0},
18672 {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID},
18673 {AliasPatternCond::K_RegClass, AArch64::GPR32spRegClassID},
18674 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
18675 // (CPY_ZPmR_S ZPR32:$Zd, PPR3bAny:$Pg, GPR32sp:$Rn) - 233
18676 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
18677 {AliasPatternCond::K_Ignore, 0},
18678 {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID},
18679 {AliasPatternCond::K_RegClass, AArch64::GPR32spRegClassID},
18680 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
18681 // (CPY_ZPmV_B ZPR8:$Zd, PPR3bAny:$Pg, FPR8:$Vn) - 238
18682 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
18683 {AliasPatternCond::K_Ignore, 0},
18684 {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID},
18685 {AliasPatternCond::K_RegClass, AArch64::FPR8RegClassID},
18686 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
18687 // (CPY_ZPmV_D ZPR64:$Zd, PPR3bAny:$Pg, FPR64:$Vn) - 243
18688 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
18689 {AliasPatternCond::K_Ignore, 0},
18690 {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID},
18691 {AliasPatternCond::K_RegClass, AArch64::FPR64RegClassID},
18692 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
18693 // (CPY_ZPmV_H ZPR16:$Zd, PPR3bAny:$Pg, FPR16:$Vn) - 248
18694 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
18695 {AliasPatternCond::K_Ignore, 0},
18696 {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID},
18697 {AliasPatternCond::K_RegClass, AArch64::FPR16RegClassID},
18698 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
18699 // (CPY_ZPmV_S ZPR32:$Zd, PPR3bAny:$Pg, FPR32:$Vn) - 253
18700 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
18701 {AliasPatternCond::K_Ignore, 0},
18702 {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID},
18703 {AliasPatternCond::K_RegClass, AArch64::FPR32RegClassID},
18704 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
18705 // (CPY_ZPzI_B ZPR8:$Zd, PPRAny:$Pg, cpy_imm8_opt_lsl_i8:$imm) - 258
18706 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
18707 {AliasPatternCond::K_RegClass, AArch64::PPRRegClassID},
18708 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
18709 // (CPY_ZPzI_D ZPR64:$Zd, PPRAny:$Pg, cpy_imm8_opt_lsl_i64:$imm) - 261
18710 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
18711 {AliasPatternCond::K_RegClass, AArch64::PPRRegClassID},
18712 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
18713 // (CPY_ZPzI_H ZPR16:$Zd, PPRAny:$Pg, cpy_imm8_opt_lsl_i16:$imm) - 264
18714 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
18715 {AliasPatternCond::K_RegClass, AArch64::PPRRegClassID},
18716 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
18717 // (CPY_ZPzI_S ZPR32:$Zd, PPRAny:$Pg, cpy_imm8_opt_lsl_i32:$imm) - 267
18718 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
18719 {AliasPatternCond::K_RegClass, AArch64::PPRRegClassID},
18720 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
18721 // (CSINCWr GPR32:$dst, WZR, WZR, inv_ccode:$cc) - 270
18722 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
18723 {AliasPatternCond::K_Reg, AArch64::WZR},
18724 {AliasPatternCond::K_Reg, AArch64::WZR},
18725 {AliasPatternCond::K_Custom, 4},
18726 // (CSINCWr GPR32:$dst, GPR32:$src, GPR32:$src, inv_ccode:$cc) - 274
18727 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
18728 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
18729 {AliasPatternCond::K_TiedReg, 1},
18730 {AliasPatternCond::K_Custom, 4},
18731 // (CSINCXr GPR64:$dst, XZR, XZR, inv_ccode:$cc) - 278
18732 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
18733 {AliasPatternCond::K_Reg, AArch64::XZR},
18734 {AliasPatternCond::K_Reg, AArch64::XZR},
18735 {AliasPatternCond::K_Custom, 4},
18736 // (CSINCXr GPR64:$dst, GPR64:$src, GPR64:$src, inv_ccode:$cc) - 282
18737 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
18738 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
18739 {AliasPatternCond::K_TiedReg, 1},
18740 {AliasPatternCond::K_Custom, 4},
18741 // (CSINVWr GPR32:$dst, WZR, WZR, inv_ccode:$cc) - 286
18742 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
18743 {AliasPatternCond::K_Reg, AArch64::WZR},
18744 {AliasPatternCond::K_Reg, AArch64::WZR},
18745 {AliasPatternCond::K_Custom, 4},
18746 // (CSINVWr GPR32:$dst, GPR32:$src, GPR32:$src, inv_ccode:$cc) - 290
18747 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
18748 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
18749 {AliasPatternCond::K_TiedReg, 1},
18750 {AliasPatternCond::K_Custom, 4},
18751 // (CSINVXr GPR64:$dst, XZR, XZR, inv_ccode:$cc) - 294
18752 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
18753 {AliasPatternCond::K_Reg, AArch64::XZR},
18754 {AliasPatternCond::K_Reg, AArch64::XZR},
18755 {AliasPatternCond::K_Custom, 4},
18756 // (CSINVXr GPR64:$dst, GPR64:$src, GPR64:$src, inv_ccode:$cc) - 298
18757 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
18758 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
18759 {AliasPatternCond::K_TiedReg, 1},
18760 {AliasPatternCond::K_Custom, 4},
18761 // (CSNEGWr GPR32:$dst, GPR32:$src, GPR32:$src, inv_ccode:$cc) - 302
18762 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
18763 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
18764 {AliasPatternCond::K_TiedReg, 1},
18765 {AliasPatternCond::K_Custom, 4},
18766 // (CSNEGXr GPR64:$dst, GPR64:$src, GPR64:$src, inv_ccode:$cc) - 306
18767 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
18768 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
18769 {AliasPatternCond::K_TiedReg, 1},
18770 {AliasPatternCond::K_Custom, 4},
18771 // (DCPS1 0) - 310
18772 {AliasPatternCond::K_Imm, uint32_t(0)},
18773 // (DCPS2 0) - 311
18774 {AliasPatternCond::K_Imm, uint32_t(0)},
18775 // (DCPS3 0) - 312
18776 {AliasPatternCond::K_Imm, uint32_t(0)},
18777 // (DECB_XPiI GPR64:$Rdn, { 1, 1, 1, 1, 1 }, 1) - 313
18778 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
18779 {AliasPatternCond::K_Ignore, 0},
18780 {AliasPatternCond::K_Imm, uint32_t(31)},
18781 {AliasPatternCond::K_Imm, uint32_t(1)},
18782 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
18783 // (DECB_XPiI GPR64:$Rdn, sve_pred_enum:$pattern, 1) - 318
18784 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
18785 {AliasPatternCond::K_Ignore, 0},
18786 {AliasPatternCond::K_Ignore, 0},
18787 {AliasPatternCond::K_Imm, uint32_t(1)},
18788 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
18789 // (DECD_XPiI GPR64:$Rdn, { 1, 1, 1, 1, 1 }, 1) - 323
18790 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
18791 {AliasPatternCond::K_Ignore, 0},
18792 {AliasPatternCond::K_Imm, uint32_t(31)},
18793 {AliasPatternCond::K_Imm, uint32_t(1)},
18794 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
18795 // (DECD_XPiI GPR64:$Rdn, sve_pred_enum:$pattern, 1) - 328
18796 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
18797 {AliasPatternCond::K_Ignore, 0},
18798 {AliasPatternCond::K_Ignore, 0},
18799 {AliasPatternCond::K_Imm, uint32_t(1)},
18800 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
18801 // (DECD_ZPiI ZPR64:$Zdn, { 1, 1, 1, 1, 1 }, 1) - 333
18802 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
18803 {AliasPatternCond::K_Ignore, 0},
18804 {AliasPatternCond::K_Imm, uint32_t(31)},
18805 {AliasPatternCond::K_Imm, uint32_t(1)},
18806 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
18807 // (DECD_ZPiI ZPR64:$Zdn, sve_pred_enum:$pattern, 1) - 338
18808 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
18809 {AliasPatternCond::K_Ignore, 0},
18810 {AliasPatternCond::K_Ignore, 0},
18811 {AliasPatternCond::K_Imm, uint32_t(1)},
18812 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
18813 // (DECH_XPiI GPR64:$Rdn, { 1, 1, 1, 1, 1 }, 1) - 343
18814 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
18815 {AliasPatternCond::K_Ignore, 0},
18816 {AliasPatternCond::K_Imm, uint32_t(31)},
18817 {AliasPatternCond::K_Imm, uint32_t(1)},
18818 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
18819 // (DECH_XPiI GPR64:$Rdn, sve_pred_enum:$pattern, 1) - 348
18820 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
18821 {AliasPatternCond::K_Ignore, 0},
18822 {AliasPatternCond::K_Ignore, 0},
18823 {AliasPatternCond::K_Imm, uint32_t(1)},
18824 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
18825 // (DECH_ZPiI ZPR16:$Zdn, { 1, 1, 1, 1, 1 }, 1) - 353
18826 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
18827 {AliasPatternCond::K_Ignore, 0},
18828 {AliasPatternCond::K_Imm, uint32_t(31)},
18829 {AliasPatternCond::K_Imm, uint32_t(1)},
18830 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
18831 // (DECH_ZPiI ZPR16:$Zdn, sve_pred_enum:$pattern, 1) - 358
18832 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
18833 {AliasPatternCond::K_Ignore, 0},
18834 {AliasPatternCond::K_Ignore, 0},
18835 {AliasPatternCond::K_Imm, uint32_t(1)},
18836 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
18837 // (DECW_XPiI GPR64:$Rdn, { 1, 1, 1, 1, 1 }, 1) - 363
18838 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
18839 {AliasPatternCond::K_Ignore, 0},
18840 {AliasPatternCond::K_Imm, uint32_t(31)},
18841 {AliasPatternCond::K_Imm, uint32_t(1)},
18842 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
18843 // (DECW_XPiI GPR64:$Rdn, sve_pred_enum:$pattern, 1) - 368
18844 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
18845 {AliasPatternCond::K_Ignore, 0},
18846 {AliasPatternCond::K_Ignore, 0},
18847 {AliasPatternCond::K_Imm, uint32_t(1)},
18848 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
18849 // (DECW_ZPiI ZPR32:$Zdn, { 1, 1, 1, 1, 1 }, 1) - 373
18850 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
18851 {AliasPatternCond::K_Ignore, 0},
18852 {AliasPatternCond::K_Imm, uint32_t(31)},
18853 {AliasPatternCond::K_Imm, uint32_t(1)},
18854 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
18855 // (DECW_ZPiI ZPR32:$Zdn, sve_pred_enum:$pattern, 1) - 378
18856 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
18857 {AliasPatternCond::K_Ignore, 0},
18858 {AliasPatternCond::K_Ignore, 0},
18859 {AliasPatternCond::K_Imm, uint32_t(1)},
18860 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
18861 // (DSB 0) - 383
18862 {AliasPatternCond::K_Imm, uint32_t(0)},
18863 // (DSB 4) - 384
18864 {AliasPatternCond::K_Imm, uint32_t(4)},
18865 // (DUPM_ZI ZPR16:$Zd, sve_preferred_logical_imm16:$imm) - 385
18866 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
18867 {AliasPatternCond::K_Custom, 5},
18868 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
18869 // (DUPM_ZI ZPR32:$Zd, sve_preferred_logical_imm32:$imm) - 388
18870 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
18871 {AliasPatternCond::K_Custom, 6},
18872 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
18873 // (DUPM_ZI ZPR64:$Zd, sve_preferred_logical_imm64:$imm) - 391
18874 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
18875 {AliasPatternCond::K_Custom, 7},
18876 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
18877 // (DUPM_ZI ZPR8:$Zd, sve_logical_imm8:$imm) - 394
18878 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
18879 {AliasPatternCond::K_Custom, 1},
18880 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
18881 // (DUPM_ZI ZPR16:$Zd, sve_logical_imm16:$imm) - 397
18882 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
18883 {AliasPatternCond::K_Custom, 2},
18884 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
18885 // (DUPM_ZI ZPR32:$Zd, sve_logical_imm32:$imm) - 400
18886 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
18887 {AliasPatternCond::K_Custom, 3},
18888 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
18889 // (DUP_ZI_B ZPR8:$Zd, cpy_imm8_opt_lsl_i8:$imm) - 403
18890 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
18891 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
18892 // (DUP_ZI_D ZPR64:$Zd, cpy_imm8_opt_lsl_i64:$imm) - 405
18893 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
18894 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
18895 // (DUP_ZI_D ZPR64:$Zd, 0, 0) - 407
18896 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
18897 {AliasPatternCond::K_Imm, uint32_t(0)},
18898 {AliasPatternCond::K_Imm, uint32_t(0)},
18899 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
18900 // (DUP_ZI_H ZPR16:$Zd, cpy_imm8_opt_lsl_i16:$imm) - 411
18901 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
18902 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
18903 // (DUP_ZI_H ZPR16:$Zd, 0, 0) - 413
18904 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
18905 {AliasPatternCond::K_Imm, uint32_t(0)},
18906 {AliasPatternCond::K_Imm, uint32_t(0)},
18907 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
18908 // (DUP_ZI_S ZPR32:$Zd, cpy_imm8_opt_lsl_i32:$imm) - 417
18909 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
18910 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
18911 // (DUP_ZI_S ZPR32:$Zd, 0, 0) - 419
18912 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
18913 {AliasPatternCond::K_Imm, uint32_t(0)},
18914 {AliasPatternCond::K_Imm, uint32_t(0)},
18915 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
18916 // (DUP_ZR_B ZPR8:$Zd, GPR32sp:$Rn) - 423
18917 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
18918 {AliasPatternCond::K_RegClass, AArch64::GPR32spRegClassID},
18919 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
18920 // (DUP_ZR_D ZPR64:$Zd, GPR64sp:$Rn) - 426
18921 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
18922 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
18923 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
18924 // (DUP_ZR_H ZPR16:$Zd, GPR32sp:$Rn) - 429
18925 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
18926 {AliasPatternCond::K_RegClass, AArch64::GPR32spRegClassID},
18927 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
18928 // (DUP_ZR_S ZPR32:$Zd, GPR32sp:$Rn) - 432
18929 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
18930 {AliasPatternCond::K_RegClass, AArch64::GPR32spRegClassID},
18931 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
18932 // (DUP_ZZI_B ZPR8:$Zd, FPR8asZPR:$Bn, 0) - 435
18933 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
18934 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
18935 {AliasPatternCond::K_Imm, uint32_t(0)},
18936 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
18937 // (DUP_ZZI_B ZPR8:$Zd, ZPR8:$Zn, sve_elm_idx_extdup_b:$idx) - 439
18938 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
18939 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
18940 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
18941 // (DUP_ZZI_D ZPR64:$Zd, FPR64asZPR:$Dn, 0) - 442
18942 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
18943 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
18944 {AliasPatternCond::K_Imm, uint32_t(0)},
18945 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
18946 // (DUP_ZZI_D ZPR64:$Zd, ZPR64:$Zn, sve_elm_idx_extdup_d:$idx) - 446
18947 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
18948 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
18949 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
18950 // (DUP_ZZI_H ZPR16:$Zd, FPR16asZPR:$Hn, 0) - 449
18951 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
18952 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
18953 {AliasPatternCond::K_Imm, uint32_t(0)},
18954 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
18955 // (DUP_ZZI_H ZPR16:$Zd, ZPR16:$Zn, sve_elm_idx_extdup_h:$idx) - 453
18956 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
18957 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
18958 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
18959 // (DUP_ZZI_Q ZPR128:$Zd, FPR128asZPR:$Qn, 0) - 456
18960 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
18961 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
18962 {AliasPatternCond::K_Imm, uint32_t(0)},
18963 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
18964 // (DUP_ZZI_Q ZPR128:$Zd, ZPR128:$Zn, sve_elm_idx_extdup_q:$idx) - 460
18965 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
18966 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
18967 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
18968 // (DUP_ZZI_S ZPR32:$Zd, FPR32asZPR:$Sn, 0) - 463
18969 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
18970 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
18971 {AliasPatternCond::K_Imm, uint32_t(0)},
18972 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
18973 // (DUP_ZZI_S ZPR32:$Zd, ZPR32:$Zn, sve_elm_idx_extdup_s:$idx) - 467
18974 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
18975 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
18976 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
18977 // (EONWrs GPR32:$dst, GPR32:$src1, GPR32:$src2, 0) - 470
18978 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
18979 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
18980 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
18981 {AliasPatternCond::K_Imm, uint32_t(0)},
18982 // (EONXrs GPR64:$dst, GPR64:$src1, GPR64:$src2, 0) - 474
18983 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
18984 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
18985 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
18986 {AliasPatternCond::K_Imm, uint32_t(0)},
18987 // (EORS_PPzPP PPR8:$Pd, PPRAny:$Pg, PPR8:$Pn, PPRAny:$Pg) - 478
18988 {AliasPatternCond::K_RegClass, AArch64::PPRRegClassID},
18989 {AliasPatternCond::K_RegClass, AArch64::PPRRegClassID},
18990 {AliasPatternCond::K_RegClass, AArch64::PPRRegClassID},
18991 {AliasPatternCond::K_TiedReg, 1},
18992 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
18993 // (EORWrs GPR32:$dst, GPR32:$src1, GPR32:$src2, 0) - 483
18994 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
18995 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
18996 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
18997 {AliasPatternCond::K_Imm, uint32_t(0)},
18998 // (EORXrs GPR64:$dst, GPR64:$src1, GPR64:$src2, 0) - 487
18999 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
19000 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
19001 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
19002 {AliasPatternCond::K_Imm, uint32_t(0)},
19003 // (EOR_PPzPP PPR8:$Pd, PPRAny:$Pg, PPR8:$Pn, PPRAny:$Pg) - 491
19004 {AliasPatternCond::K_RegClass, AArch64::PPRRegClassID},
19005 {AliasPatternCond::K_RegClass, AArch64::PPRRegClassID},
19006 {AliasPatternCond::K_RegClass, AArch64::PPRRegClassID},
19007 {AliasPatternCond::K_TiedReg, 1},
19008 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
19009 // (EOR_ZI ZPR8:$Zdn, sve_logical_imm8:$imm) - 496
19010 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
19011 {AliasPatternCond::K_Ignore, 0},
19012 {AliasPatternCond::K_Custom, 1},
19013 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
19014 // (EOR_ZI ZPR16:$Zdn, sve_logical_imm16:$imm) - 500
19015 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
19016 {AliasPatternCond::K_Ignore, 0},
19017 {AliasPatternCond::K_Custom, 2},
19018 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
19019 // (EOR_ZI ZPR32:$Zdn, sve_logical_imm32:$imm) - 504
19020 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
19021 {AliasPatternCond::K_Ignore, 0},
19022 {AliasPatternCond::K_Custom, 3},
19023 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
19024 // (EXTRWrri GPR32:$dst, GPR32:$src, GPR32:$src, imm0_31:$shift) - 508
19025 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
19026 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
19027 {AliasPatternCond::K_TiedReg, 1},
19028 // (EXTRXrri GPR64:$dst, GPR64:$src, GPR64:$src, imm0_63:$shift) - 511
19029 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
19030 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
19031 {AliasPatternCond::K_TiedReg, 1},
19032 // (FCPY_ZPmI_D ZPR64:$Zd, PPRAny:$Pg, fpimm64:$imm8) - 514
19033 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
19034 {AliasPatternCond::K_Ignore, 0},
19035 {AliasPatternCond::K_RegClass, AArch64::PPRRegClassID},
19036 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
19037 // (FCPY_ZPmI_H ZPR16:$Zd, PPRAny:$Pg, fpimm16:$imm8) - 518
19038 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
19039 {AliasPatternCond::K_Ignore, 0},
19040 {AliasPatternCond::K_RegClass, AArch64::PPRRegClassID},
19041 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
19042 // (FCPY_ZPmI_S ZPR32:$Zd, PPRAny:$Pg, fpimm32:$imm8) - 522
19043 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
19044 {AliasPatternCond::K_Ignore, 0},
19045 {AliasPatternCond::K_RegClass, AArch64::PPRRegClassID},
19046 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
19047 // (FDUP_ZI_D ZPR64:$Zd, fpimm64:$imm8) - 526
19048 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
19049 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
19050 // (FDUP_ZI_H ZPR16:$Zd, fpimm16:$imm8) - 528
19051 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
19052 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
19053 // (FDUP_ZI_S ZPR32:$Zd, fpimm32:$imm8) - 530
19054 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
19055 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
19056 // (GLD1B_D_IMM_REAL Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, 0) - 532
19057 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
19058 {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID},
19059 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
19060 {AliasPatternCond::K_Imm, uint32_t(0)},
19061 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
19062 // (GLD1B_S_IMM_REAL Z_s:$Zt, PPR3bAny:$Pg, ZPR32:$Zn, 0) - 537
19063 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
19064 {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID},
19065 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
19066 {AliasPatternCond::K_Imm, uint32_t(0)},
19067 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
19068 // (GLD1D_IMM_REAL Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, 0) - 542
19069 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
19070 {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID},
19071 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
19072 {AliasPatternCond::K_Imm, uint32_t(0)},
19073 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
19074 // (GLD1H_D_IMM_REAL Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, 0) - 547
19075 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
19076 {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID},
19077 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
19078 {AliasPatternCond::K_Imm, uint32_t(0)},
19079 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
19080 // (GLD1H_S_IMM_REAL Z_s:$Zt, PPR3bAny:$Pg, ZPR32:$Zn, 0) - 552
19081 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
19082 {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID},
19083 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
19084 {AliasPatternCond::K_Imm, uint32_t(0)},
19085 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
19086 // (GLD1SB_D_IMM_REAL Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, 0) - 557
19087 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
19088 {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID},
19089 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
19090 {AliasPatternCond::K_Imm, uint32_t(0)},
19091 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
19092 // (GLD1SB_S_IMM_REAL Z_s:$Zt, PPR3bAny:$Pg, ZPR32:$Zn, 0) - 562
19093 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
19094 {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID},
19095 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
19096 {AliasPatternCond::K_Imm, uint32_t(0)},
19097 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
19098 // (GLD1SH_D_IMM_REAL Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, 0) - 567
19099 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
19100 {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID},
19101 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
19102 {AliasPatternCond::K_Imm, uint32_t(0)},
19103 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
19104 // (GLD1SH_S_IMM_REAL Z_s:$Zt, PPR3bAny:$Pg, ZPR32:$Zn, 0) - 572
19105 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
19106 {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID},
19107 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
19108 {AliasPatternCond::K_Imm, uint32_t(0)},
19109 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
19110 // (GLD1SW_D_IMM_REAL Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, 0) - 577
19111 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
19112 {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID},
19113 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
19114 {AliasPatternCond::K_Imm, uint32_t(0)},
19115 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
19116 // (GLD1W_D_IMM_REAL Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, 0) - 582
19117 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
19118 {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID},
19119 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
19120 {AliasPatternCond::K_Imm, uint32_t(0)},
19121 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
19122 // (GLD1W_IMM_REAL Z_s:$Zt, PPR3bAny:$Pg, ZPR32:$Zn, 0) - 587
19123 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
19124 {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID},
19125 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
19126 {AliasPatternCond::K_Imm, uint32_t(0)},
19127 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
19128 // (GLDFF1B_D_IMM_REAL Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, 0) - 592
19129 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
19130 {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID},
19131 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
19132 {AliasPatternCond::K_Imm, uint32_t(0)},
19133 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
19134 // (GLDFF1B_S_IMM_REAL Z_s:$Zt, PPR3bAny:$Pg, ZPR32:$Zn, 0) - 597
19135 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
19136 {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID},
19137 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
19138 {AliasPatternCond::K_Imm, uint32_t(0)},
19139 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
19140 // (GLDFF1D_IMM_REAL Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, 0) - 602
19141 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
19142 {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID},
19143 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
19144 {AliasPatternCond::K_Imm, uint32_t(0)},
19145 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
19146 // (GLDFF1H_D_IMM_REAL Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, 0) - 607
19147 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
19148 {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID},
19149 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
19150 {AliasPatternCond::K_Imm, uint32_t(0)},
19151 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
19152 // (GLDFF1H_S_IMM_REAL Z_s:$Zt, PPR3bAny:$Pg, ZPR32:$Zn, 0) - 612
19153 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
19154 {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID},
19155 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
19156 {AliasPatternCond::K_Imm, uint32_t(0)},
19157 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
19158 // (GLDFF1SB_D_IMM_REAL Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, 0) - 617
19159 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
19160 {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID},
19161 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
19162 {AliasPatternCond::K_Imm, uint32_t(0)},
19163 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
19164 // (GLDFF1SB_S_IMM_REAL Z_s:$Zt, PPR3bAny:$Pg, ZPR32:$Zn, 0) - 622
19165 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
19166 {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID},
19167 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
19168 {AliasPatternCond::K_Imm, uint32_t(0)},
19169 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
19170 // (GLDFF1SH_D_IMM_REAL Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, 0) - 627
19171 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
19172 {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID},
19173 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
19174 {AliasPatternCond::K_Imm, uint32_t(0)},
19175 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
19176 // (GLDFF1SH_S_IMM_REAL Z_s:$Zt, PPR3bAny:$Pg, ZPR32:$Zn, 0) - 632
19177 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
19178 {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID},
19179 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
19180 {AliasPatternCond::K_Imm, uint32_t(0)},
19181 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
19182 // (GLDFF1SW_D_IMM_REAL Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, 0) - 637
19183 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
19184 {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID},
19185 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
19186 {AliasPatternCond::K_Imm, uint32_t(0)},
19187 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
19188 // (GLDFF1W_D_IMM_REAL Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, 0) - 642
19189 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
19190 {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID},
19191 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
19192 {AliasPatternCond::K_Imm, uint32_t(0)},
19193 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
19194 // (GLDFF1W_IMM_REAL Z_s:$Zt, PPR3bAny:$Pg, ZPR32:$Zn, 0) - 647
19195 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
19196 {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID},
19197 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
19198 {AliasPatternCond::K_Imm, uint32_t(0)},
19199 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
19200 // (HINT { 0, 0, 0 }) - 652
19201 {AliasPatternCond::K_Imm, uint32_t(0)},
19202 // (HINT { 0, 0, 1 }) - 653
19203 {AliasPatternCond::K_Imm, uint32_t(1)},
19204 // (HINT { 0, 1, 0 }) - 654
19205 {AliasPatternCond::K_Imm, uint32_t(2)},
19206 // (HINT { 0, 1, 1 }) - 655
19207 {AliasPatternCond::K_Imm, uint32_t(3)},
19208 // (HINT { 1, 0, 0 }) - 656
19209 {AliasPatternCond::K_Imm, uint32_t(4)},
19210 // (HINT { 1, 0, 1 }) - 657
19211 {AliasPatternCond::K_Imm, uint32_t(5)},
19212 // (HINT { 1, 1, 0 }) - 658
19213 {AliasPatternCond::K_Imm, uint32_t(6)},
19214 // (HINT { 1, 0, 0, 0, 0 }) - 659
19215 {AliasPatternCond::K_Imm, uint32_t(16)},
19216 {AliasPatternCond::K_Feature, AArch64::FeatureRAS},
19217 // (HINT 20) - 661
19218 {AliasPatternCond::K_Imm, uint32_t(20)},
19219 // (HINT 32) - 662
19220 {AliasPatternCond::K_Imm, uint32_t(32)},
19221 {AliasPatternCond::K_Feature, AArch64::FeatureBranchTargetId},
19222 // (HINT btihint_op:$op) - 664
19223 {AliasPatternCond::K_Custom, 8},
19224 {AliasPatternCond::K_Feature, AArch64::FeatureBranchTargetId},
19225 // (HINT psbhint_op:$op) - 666
19226 {AliasPatternCond::K_Custom, 9},
19227 {AliasPatternCond::K_Feature, AArch64::FeatureSPE},
19228 // (INCB_XPiI GPR64:$Rdn, { 1, 1, 1, 1, 1 }, 1) - 668
19229 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
19230 {AliasPatternCond::K_Ignore, 0},
19231 {AliasPatternCond::K_Imm, uint32_t(31)},
19232 {AliasPatternCond::K_Imm, uint32_t(1)},
19233 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
19234 // (INCB_XPiI GPR64:$Rdn, sve_pred_enum:$pattern, 1) - 673
19235 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
19236 {AliasPatternCond::K_Ignore, 0},
19237 {AliasPatternCond::K_Ignore, 0},
19238 {AliasPatternCond::K_Imm, uint32_t(1)},
19239 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
19240 // (INCD_XPiI GPR64:$Rdn, { 1, 1, 1, 1, 1 }, 1) - 678
19241 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
19242 {AliasPatternCond::K_Ignore, 0},
19243 {AliasPatternCond::K_Imm, uint32_t(31)},
19244 {AliasPatternCond::K_Imm, uint32_t(1)},
19245 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
19246 // (INCD_XPiI GPR64:$Rdn, sve_pred_enum:$pattern, 1) - 683
19247 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
19248 {AliasPatternCond::K_Ignore, 0},
19249 {AliasPatternCond::K_Ignore, 0},
19250 {AliasPatternCond::K_Imm, uint32_t(1)},
19251 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
19252 // (INCD_ZPiI ZPR64:$Zdn, { 1, 1, 1, 1, 1 }, 1) - 688
19253 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
19254 {AliasPatternCond::K_Ignore, 0},
19255 {AliasPatternCond::K_Imm, uint32_t(31)},
19256 {AliasPatternCond::K_Imm, uint32_t(1)},
19257 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
19258 // (INCD_ZPiI ZPR64:$Zdn, sve_pred_enum:$pattern, 1) - 693
19259 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
19260 {AliasPatternCond::K_Ignore, 0},
19261 {AliasPatternCond::K_Ignore, 0},
19262 {AliasPatternCond::K_Imm, uint32_t(1)},
19263 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
19264 // (INCH_XPiI GPR64:$Rdn, { 1, 1, 1, 1, 1 }, 1) - 698
19265 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
19266 {AliasPatternCond::K_Ignore, 0},
19267 {AliasPatternCond::K_Imm, uint32_t(31)},
19268 {AliasPatternCond::K_Imm, uint32_t(1)},
19269 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
19270 // (INCH_XPiI GPR64:$Rdn, sve_pred_enum:$pattern, 1) - 703
19271 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
19272 {AliasPatternCond::K_Ignore, 0},
19273 {AliasPatternCond::K_Ignore, 0},
19274 {AliasPatternCond::K_Imm, uint32_t(1)},
19275 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
19276 // (INCH_ZPiI ZPR16:$Zdn, { 1, 1, 1, 1, 1 }, 1) - 708
19277 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
19278 {AliasPatternCond::K_Ignore, 0},
19279 {AliasPatternCond::K_Imm, uint32_t(31)},
19280 {AliasPatternCond::K_Imm, uint32_t(1)},
19281 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
19282 // (INCH_ZPiI ZPR16:$Zdn, sve_pred_enum:$pattern, 1) - 713
19283 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
19284 {AliasPatternCond::K_Ignore, 0},
19285 {AliasPatternCond::K_Ignore, 0},
19286 {AliasPatternCond::K_Imm, uint32_t(1)},
19287 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
19288 // (INCW_XPiI GPR64:$Rdn, { 1, 1, 1, 1, 1 }, 1) - 718
19289 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
19290 {AliasPatternCond::K_Ignore, 0},
19291 {AliasPatternCond::K_Imm, uint32_t(31)},
19292 {AliasPatternCond::K_Imm, uint32_t(1)},
19293 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
19294 // (INCW_XPiI GPR64:$Rdn, sve_pred_enum:$pattern, 1) - 723
19295 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
19296 {AliasPatternCond::K_Ignore, 0},
19297 {AliasPatternCond::K_Ignore, 0},
19298 {AliasPatternCond::K_Imm, uint32_t(1)},
19299 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
19300 // (INCW_ZPiI ZPR32:$Zdn, { 1, 1, 1, 1, 1 }, 1) - 728
19301 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
19302 {AliasPatternCond::K_Ignore, 0},
19303 {AliasPatternCond::K_Imm, uint32_t(31)},
19304 {AliasPatternCond::K_Imm, uint32_t(1)},
19305 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
19306 // (INCW_ZPiI ZPR32:$Zdn, sve_pred_enum:$pattern, 1) - 733
19307 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
19308 {AliasPatternCond::K_Ignore, 0},
19309 {AliasPatternCond::K_Ignore, 0},
19310 {AliasPatternCond::K_Imm, uint32_t(1)},
19311 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
19312 // (INSvi16gpr V128:$dst, VectorIndexH:$idx, GPR32:$src) - 738
19313 {AliasPatternCond::K_RegClass, AArch64::FPR128RegClassID},
19314 {AliasPatternCond::K_Ignore, 0},
19315 {AliasPatternCond::K_Ignore, 0},
19316 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
19317 {AliasPatternCond::K_Feature, AArch64::FeatureNEON},
19318 // (INSvi16lane V128:$dst, VectorIndexH:$idx, V128:$src, VectorIndexH:$idx2) - 743
19319 {AliasPatternCond::K_RegClass, AArch64::FPR128RegClassID},
19320 {AliasPatternCond::K_Ignore, 0},
19321 {AliasPatternCond::K_Ignore, 0},
19322 {AliasPatternCond::K_RegClass, AArch64::FPR128RegClassID},
19323 {AliasPatternCond::K_Feature, AArch64::FeatureNEON},
19324 // (INSvi32gpr V128:$dst, VectorIndexS:$idx, GPR32:$src) - 748
19325 {AliasPatternCond::K_RegClass, AArch64::FPR128RegClassID},
19326 {AliasPatternCond::K_Ignore, 0},
19327 {AliasPatternCond::K_Ignore, 0},
19328 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
19329 {AliasPatternCond::K_Feature, AArch64::FeatureNEON},
19330 // (INSvi32lane V128:$dst, VectorIndexS:$idx, V128:$src, VectorIndexS:$idx2) - 753
19331 {AliasPatternCond::K_RegClass, AArch64::FPR128RegClassID},
19332 {AliasPatternCond::K_Ignore, 0},
19333 {AliasPatternCond::K_Ignore, 0},
19334 {AliasPatternCond::K_RegClass, AArch64::FPR128RegClassID},
19335 {AliasPatternCond::K_Feature, AArch64::FeatureNEON},
19336 // (INSvi64gpr V128:$dst, VectorIndexD:$idx, GPR64:$src) - 758
19337 {AliasPatternCond::K_RegClass, AArch64::FPR128RegClassID},
19338 {AliasPatternCond::K_Ignore, 0},
19339 {AliasPatternCond::K_Ignore, 0},
19340 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
19341 {AliasPatternCond::K_Feature, AArch64::FeatureNEON},
19342 // (INSvi64lane V128:$dst, VectorIndexD:$idx, V128:$src, VectorIndexD:$idx2) - 763
19343 {AliasPatternCond::K_RegClass, AArch64::FPR128RegClassID},
19344 {AliasPatternCond::K_Ignore, 0},
19345 {AliasPatternCond::K_Ignore, 0},
19346 {AliasPatternCond::K_RegClass, AArch64::FPR128RegClassID},
19347 {AliasPatternCond::K_Feature, AArch64::FeatureNEON},
19348 // (INSvi8gpr V128:$dst, VectorIndexB:$idx, GPR32:$src) - 768
19349 {AliasPatternCond::K_RegClass, AArch64::FPR128RegClassID},
19350 {AliasPatternCond::K_Ignore, 0},
19351 {AliasPatternCond::K_Ignore, 0},
19352 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
19353 {AliasPatternCond::K_Feature, AArch64::FeatureNEON},
19354 // (INSvi8lane V128:$dst, VectorIndexB:$idx, V128:$src, VectorIndexB:$idx2) - 773
19355 {AliasPatternCond::K_RegClass, AArch64::FPR128RegClassID},
19356 {AliasPatternCond::K_Ignore, 0},
19357 {AliasPatternCond::K_Ignore, 0},
19358 {AliasPatternCond::K_RegClass, AArch64::FPR128RegClassID},
19359 {AliasPatternCond::K_Feature, AArch64::FeatureNEON},
19360 // (IRG GPR64sp:$dst, GPR64sp:$src, XZR) - 778
19361 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
19362 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
19363 {AliasPatternCond::K_Reg, AArch64::XZR},
19364 {AliasPatternCond::K_Feature, AArch64::FeatureMTE},
19365 // (ISB 15) - 782
19366 {AliasPatternCond::K_Imm, uint32_t(15)},
19367 // (LD1B_D_IMM_REAL Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 783
19368 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
19369 {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID},
19370 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
19371 {AliasPatternCond::K_Imm, uint32_t(0)},
19372 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
19373 // (LD1B_H_IMM_REAL Z_h:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 788
19374 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
19375 {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID},
19376 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
19377 {AliasPatternCond::K_Imm, uint32_t(0)},
19378 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
19379 // (LD1B_IMM_REAL Z_b:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 793
19380 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
19381 {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID},
19382 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
19383 {AliasPatternCond::K_Imm, uint32_t(0)},
19384 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
19385 // (LD1B_S_IMM_REAL Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 798
19386 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
19387 {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID},
19388 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
19389 {AliasPatternCond::K_Imm, uint32_t(0)},
19390 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
19391 // (LD1D_IMM_REAL Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 803
19392 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
19393 {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID},
19394 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
19395 {AliasPatternCond::K_Imm, uint32_t(0)},
19396 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
19397 // (LD1Fourv16b_POST GPR64sp:$Rn, VecListFour16b:$Vt, XZR) - 808
19398 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
19399 {AliasPatternCond::K_RegClass, AArch64::QQQQRegClassID},
19400 {AliasPatternCond::K_Ignore, 0},
19401 {AliasPatternCond::K_Reg, AArch64::XZR},
19402 {AliasPatternCond::K_Feature, AArch64::FeatureNEON},
19403 // (LD1Fourv1d_POST GPR64sp:$Rn, VecListFour1d:$Vt, XZR) - 813
19404 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
19405 {AliasPatternCond::K_RegClass, AArch64::DDDDRegClassID},
19406 {AliasPatternCond::K_Ignore, 0},
19407 {AliasPatternCond::K_Reg, AArch64::XZR},
19408 {AliasPatternCond::K_Feature, AArch64::FeatureNEON},
19409 // (LD1Fourv2d_POST GPR64sp:$Rn, VecListFour2d:$Vt, XZR) - 818
19410 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
19411 {AliasPatternCond::K_RegClass, AArch64::QQQQRegClassID},
19412 {AliasPatternCond::K_Ignore, 0},
19413 {AliasPatternCond::K_Reg, AArch64::XZR},
19414 {AliasPatternCond::K_Feature, AArch64::FeatureNEON},
19415 // (LD1Fourv2s_POST GPR64sp:$Rn, VecListFour2s:$Vt, XZR) - 823
19416 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
19417 {AliasPatternCond::K_RegClass, AArch64::DDDDRegClassID},
19418 {AliasPatternCond::K_Ignore, 0},
19419 {AliasPatternCond::K_Reg, AArch64::XZR},
19420 {AliasPatternCond::K_Feature, AArch64::FeatureNEON},
19421 // (LD1Fourv4h_POST GPR64sp:$Rn, VecListFour4h:$Vt, XZR) - 828
19422 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
19423 {AliasPatternCond::K_RegClass, AArch64::DDDDRegClassID},
19424 {AliasPatternCond::K_Ignore, 0},
19425 {AliasPatternCond::K_Reg, AArch64::XZR},
19426 {AliasPatternCond::K_Feature, AArch64::FeatureNEON},
19427 // (LD1Fourv4s_POST GPR64sp:$Rn, VecListFour4s:$Vt, XZR) - 833
19428 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
19429 {AliasPatternCond::K_RegClass, AArch64::QQQQRegClassID},
19430 {AliasPatternCond::K_Ignore, 0},
19431 {AliasPatternCond::K_Reg, AArch64::XZR},
19432 {AliasPatternCond::K_Feature, AArch64::FeatureNEON},
19433 // (LD1Fourv8b_POST GPR64sp:$Rn, VecListFour8b:$Vt, XZR) - 838
19434 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
19435 {AliasPatternCond::K_RegClass, AArch64::DDDDRegClassID},
19436 {AliasPatternCond::K_Ignore, 0},
19437 {AliasPatternCond::K_Reg, AArch64::XZR},
19438 {AliasPatternCond::K_Feature, AArch64::FeatureNEON},
19439 // (LD1Fourv8h_POST GPR64sp:$Rn, VecListFour8h:$Vt, XZR) - 843
19440 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
19441 {AliasPatternCond::K_RegClass, AArch64::QQQQRegClassID},
19442 {AliasPatternCond::K_Ignore, 0},
19443 {AliasPatternCond::K_Reg, AArch64::XZR},
19444 {AliasPatternCond::K_Feature, AArch64::FeatureNEON},
19445 // (LD1H_D_IMM_REAL Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 848
19446 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
19447 {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID},
19448 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
19449 {AliasPatternCond::K_Imm, uint32_t(0)},
19450 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
19451 // (LD1H_IMM_REAL Z_h:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 853
19452 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
19453 {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID},
19454 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
19455 {AliasPatternCond::K_Imm, uint32_t(0)},
19456 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
19457 // (LD1H_S_IMM_REAL Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 858
19458 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
19459 {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID},
19460 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
19461 {AliasPatternCond::K_Imm, uint32_t(0)},
19462 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
19463 // (LD1Onev16b_POST GPR64sp:$Rn, VecListOne16b:$Vt, XZR) - 863
19464 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
19465 {AliasPatternCond::K_RegClass, AArch64::FPR128RegClassID},
19466 {AliasPatternCond::K_Ignore, 0},
19467 {AliasPatternCond::K_Reg, AArch64::XZR},
19468 {AliasPatternCond::K_Feature, AArch64::FeatureNEON},
19469 // (LD1Onev1d_POST GPR64sp:$Rn, VecListOne1d:$Vt, XZR) - 868
19470 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
19471 {AliasPatternCond::K_RegClass, AArch64::FPR64RegClassID},
19472 {AliasPatternCond::K_Ignore, 0},
19473 {AliasPatternCond::K_Reg, AArch64::XZR},
19474 {AliasPatternCond::K_Feature, AArch64::FeatureNEON},
19475 // (LD1Onev2d_POST GPR64sp:$Rn, VecListOne2d:$Vt, XZR) - 873
19476 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
19477 {AliasPatternCond::K_RegClass, AArch64::FPR128RegClassID},
19478 {AliasPatternCond::K_Ignore, 0},
19479 {AliasPatternCond::K_Reg, AArch64::XZR},
19480 {AliasPatternCond::K_Feature, AArch64::FeatureNEON},
19481 // (LD1Onev2s_POST GPR64sp:$Rn, VecListOne2s:$Vt, XZR) - 878
19482 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
19483 {AliasPatternCond::K_RegClass, AArch64::FPR64RegClassID},
19484 {AliasPatternCond::K_Ignore, 0},
19485 {AliasPatternCond::K_Reg, AArch64::XZR},
19486 {AliasPatternCond::K_Feature, AArch64::FeatureNEON},
19487 // (LD1Onev4h_POST GPR64sp:$Rn, VecListOne4h:$Vt, XZR) - 883
19488 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
19489 {AliasPatternCond::K_RegClass, AArch64::FPR64RegClassID},
19490 {AliasPatternCond::K_Ignore, 0},
19491 {AliasPatternCond::K_Reg, AArch64::XZR},
19492 {AliasPatternCond::K_Feature, AArch64::FeatureNEON},
19493 // (LD1Onev4s_POST GPR64sp:$Rn, VecListOne4s:$Vt, XZR) - 888
19494 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
19495 {AliasPatternCond::K_RegClass, AArch64::FPR128RegClassID},
19496 {AliasPatternCond::K_Ignore, 0},
19497 {AliasPatternCond::K_Reg, AArch64::XZR},
19498 {AliasPatternCond::K_Feature, AArch64::FeatureNEON},
19499 // (LD1Onev8b_POST GPR64sp:$Rn, VecListOne8b:$Vt, XZR) - 893
19500 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
19501 {AliasPatternCond::K_RegClass, AArch64::FPR64RegClassID},
19502 {AliasPatternCond::K_Ignore, 0},
19503 {AliasPatternCond::K_Reg, AArch64::XZR},
19504 {AliasPatternCond::K_Feature, AArch64::FeatureNEON},
19505 // (LD1Onev8h_POST GPR64sp:$Rn, VecListOne8h:$Vt, XZR) - 898
19506 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
19507 {AliasPatternCond::K_RegClass, AArch64::FPR128RegClassID},
19508 {AliasPatternCond::K_Ignore, 0},
19509 {AliasPatternCond::K_Reg, AArch64::XZR},
19510 {AliasPatternCond::K_Feature, AArch64::FeatureNEON},
19511 // (LD1RB_D_IMM Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 903
19512 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
19513 {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID},
19514 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
19515 {AliasPatternCond::K_Imm, uint32_t(0)},
19516 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
19517 // (LD1RB_H_IMM Z_h:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 908
19518 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
19519 {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID},
19520 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
19521 {AliasPatternCond::K_Imm, uint32_t(0)},
19522 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
19523 // (LD1RB_IMM Z_b:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 913
19524 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
19525 {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID},
19526 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
19527 {AliasPatternCond::K_Imm, uint32_t(0)},
19528 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
19529 // (LD1RB_S_IMM Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 918
19530 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
19531 {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID},
19532 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
19533 {AliasPatternCond::K_Imm, uint32_t(0)},
19534 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
19535 // (LD1RD_IMM Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 923
19536 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
19537 {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID},
19538 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
19539 {AliasPatternCond::K_Imm, uint32_t(0)},
19540 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
19541 // (LD1RH_D_IMM Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 928
19542 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
19543 {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID},
19544 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
19545 {AliasPatternCond::K_Imm, uint32_t(0)},
19546 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
19547 // (LD1RH_IMM Z_h:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 933
19548 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
19549 {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID},
19550 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
19551 {AliasPatternCond::K_Imm, uint32_t(0)},
19552 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
19553 // (LD1RH_S_IMM Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 938
19554 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
19555 {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID},
19556 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
19557 {AliasPatternCond::K_Imm, uint32_t(0)},
19558 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
19559 // (LD1RO_B_IMM Z_b:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 943
19560 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
19561 {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID},
19562 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
19563 {AliasPatternCond::K_Imm, uint32_t(0)},
19564 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
19565 {AliasPatternCond::K_Feature, AArch64::FeatureMatMulFP64},
19566 // (LD1RO_D_IMM Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 949
19567 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
19568 {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID},
19569 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
19570 {AliasPatternCond::K_Imm, uint32_t(0)},
19571 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
19572 {AliasPatternCond::K_Feature, AArch64::FeatureMatMulFP64},
19573 // (LD1RO_H_IMM Z_h:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 955
19574 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
19575 {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID},
19576 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
19577 {AliasPatternCond::K_Imm, uint32_t(0)},
19578 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
19579 {AliasPatternCond::K_Feature, AArch64::FeatureMatMulFP64},
19580 // (LD1RO_W_IMM Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 961
19581 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
19582 {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID},
19583 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
19584 {AliasPatternCond::K_Imm, uint32_t(0)},
19585 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
19586 {AliasPatternCond::K_Feature, AArch64::FeatureMatMulFP64},
19587 // (LD1RQ_B_IMM Z_b:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 967
19588 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
19589 {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID},
19590 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
19591 {AliasPatternCond::K_Imm, uint32_t(0)},
19592 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
19593 // (LD1RQ_D_IMM Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 972
19594 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
19595 {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID},
19596 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
19597 {AliasPatternCond::K_Imm, uint32_t(0)},
19598 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
19599 // (LD1RQ_H_IMM Z_h:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 977
19600 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
19601 {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID},
19602 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
19603 {AliasPatternCond::K_Imm, uint32_t(0)},
19604 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
19605 // (LD1RQ_W_IMM Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 982
19606 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
19607 {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID},
19608 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
19609 {AliasPatternCond::K_Imm, uint32_t(0)},
19610 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
19611 // (LD1RSB_D_IMM Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 987
19612 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
19613 {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID},
19614 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
19615 {AliasPatternCond::K_Imm, uint32_t(0)},
19616 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
19617 // (LD1RSB_H_IMM Z_h:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 992
19618 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
19619 {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID},
19620 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
19621 {AliasPatternCond::K_Imm, uint32_t(0)},
19622 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
19623 // (LD1RSB_S_IMM Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 997
19624 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
19625 {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID},
19626 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
19627 {AliasPatternCond::K_Imm, uint32_t(0)},
19628 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
19629 // (LD1RSH_D_IMM Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1002
19630 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
19631 {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID},
19632 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
19633 {AliasPatternCond::K_Imm, uint32_t(0)},
19634 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
19635 // (LD1RSH_S_IMM Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1007
19636 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
19637 {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID},
19638 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
19639 {AliasPatternCond::K_Imm, uint32_t(0)},
19640 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
19641 // (LD1RSW_IMM Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1012
19642 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
19643 {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID},
19644 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
19645 {AliasPatternCond::K_Imm, uint32_t(0)},
19646 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
19647 // (LD1RW_D_IMM Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1017
19648 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
19649 {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID},
19650 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
19651 {AliasPatternCond::K_Imm, uint32_t(0)},
19652 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
19653 // (LD1RW_IMM Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1022
19654 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
19655 {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID},
19656 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
19657 {AliasPatternCond::K_Imm, uint32_t(0)},
19658 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
19659 // (LD1Rv16b_POST GPR64sp:$Rn, VecListOne16b:$Vt, XZR) - 1027
19660 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
19661 {AliasPatternCond::K_RegClass, AArch64::FPR128RegClassID},
19662 {AliasPatternCond::K_Ignore, 0},
19663 {AliasPatternCond::K_Reg, AArch64::XZR},
19664 {AliasPatternCond::K_Feature, AArch64::FeatureNEON},
19665 // (LD1Rv1d_POST GPR64sp:$Rn, VecListOne1d:$Vt, XZR) - 1032
19666 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
19667 {AliasPatternCond::K_RegClass, AArch64::FPR64RegClassID},
19668 {AliasPatternCond::K_Ignore, 0},
19669 {AliasPatternCond::K_Reg, AArch64::XZR},
19670 {AliasPatternCond::K_Feature, AArch64::FeatureNEON},
19671 // (LD1Rv2d_POST GPR64sp:$Rn, VecListOne2d:$Vt, XZR) - 1037
19672 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
19673 {AliasPatternCond::K_RegClass, AArch64::FPR128RegClassID},
19674 {AliasPatternCond::K_Ignore, 0},
19675 {AliasPatternCond::K_Reg, AArch64::XZR},
19676 {AliasPatternCond::K_Feature, AArch64::FeatureNEON},
19677 // (LD1Rv2s_POST GPR64sp:$Rn, VecListOne2s:$Vt, XZR) - 1042
19678 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
19679 {AliasPatternCond::K_RegClass, AArch64::FPR64RegClassID},
19680 {AliasPatternCond::K_Ignore, 0},
19681 {AliasPatternCond::K_Reg, AArch64::XZR},
19682 {AliasPatternCond::K_Feature, AArch64::FeatureNEON},
19683 // (LD1Rv4h_POST GPR64sp:$Rn, VecListOne4h:$Vt, XZR) - 1047
19684 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
19685 {AliasPatternCond::K_RegClass, AArch64::FPR64RegClassID},
19686 {AliasPatternCond::K_Ignore, 0},
19687 {AliasPatternCond::K_Reg, AArch64::XZR},
19688 {AliasPatternCond::K_Feature, AArch64::FeatureNEON},
19689 // (LD1Rv4s_POST GPR64sp:$Rn, VecListOne4s:$Vt, XZR) - 1052
19690 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
19691 {AliasPatternCond::K_RegClass, AArch64::FPR128RegClassID},
19692 {AliasPatternCond::K_Ignore, 0},
19693 {AliasPatternCond::K_Reg, AArch64::XZR},
19694 {AliasPatternCond::K_Feature, AArch64::FeatureNEON},
19695 // (LD1Rv8b_POST GPR64sp:$Rn, VecListOne8b:$Vt, XZR) - 1057
19696 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
19697 {AliasPatternCond::K_RegClass, AArch64::FPR64RegClassID},
19698 {AliasPatternCond::K_Ignore, 0},
19699 {AliasPatternCond::K_Reg, AArch64::XZR},
19700 {AliasPatternCond::K_Feature, AArch64::FeatureNEON},
19701 // (LD1Rv8h_POST GPR64sp:$Rn, VecListOne8h:$Vt, XZR) - 1062
19702 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
19703 {AliasPatternCond::K_RegClass, AArch64::FPR128RegClassID},
19704 {AliasPatternCond::K_Ignore, 0},
19705 {AliasPatternCond::K_Reg, AArch64::XZR},
19706 {AliasPatternCond::K_Feature, AArch64::FeatureNEON},
19707 // (LD1SB_D_IMM_REAL Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1067
19708 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
19709 {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID},
19710 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
19711 {AliasPatternCond::K_Imm, uint32_t(0)},
19712 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
19713 // (LD1SB_H_IMM_REAL Z_h:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1072
19714 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
19715 {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID},
19716 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
19717 {AliasPatternCond::K_Imm, uint32_t(0)},
19718 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
19719 // (LD1SB_S_IMM_REAL Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1077
19720 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
19721 {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID},
19722 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
19723 {AliasPatternCond::K_Imm, uint32_t(0)},
19724 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
19725 // (LD1SH_D_IMM_REAL Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1082
19726 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
19727 {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID},
19728 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
19729 {AliasPatternCond::K_Imm, uint32_t(0)},
19730 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
19731 // (LD1SH_S_IMM_REAL Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1087
19732 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
19733 {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID},
19734 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
19735 {AliasPatternCond::K_Imm, uint32_t(0)},
19736 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
19737 // (LD1SW_D_IMM_REAL Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1092
19738 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
19739 {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID},
19740 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
19741 {AliasPatternCond::K_Imm, uint32_t(0)},
19742 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
19743 // (LD1Threev16b_POST GPR64sp:$Rn, VecListThree16b:$Vt, XZR) - 1097
19744 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
19745 {AliasPatternCond::K_RegClass, AArch64::QQQRegClassID},
19746 {AliasPatternCond::K_Ignore, 0},
19747 {AliasPatternCond::K_Reg, AArch64::XZR},
19748 {AliasPatternCond::K_Feature, AArch64::FeatureNEON},
19749 // (LD1Threev1d_POST GPR64sp:$Rn, VecListThree1d:$Vt, XZR) - 1102
19750 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
19751 {AliasPatternCond::K_RegClass, AArch64::DDDRegClassID},
19752 {AliasPatternCond::K_Ignore, 0},
19753 {AliasPatternCond::K_Reg, AArch64::XZR},
19754 {AliasPatternCond::K_Feature, AArch64::FeatureNEON},
19755 // (LD1Threev2d_POST GPR64sp:$Rn, VecListThree2d:$Vt, XZR) - 1107
19756 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
19757 {AliasPatternCond::K_RegClass, AArch64::QQQRegClassID},
19758 {AliasPatternCond::K_Ignore, 0},
19759 {AliasPatternCond::K_Reg, AArch64::XZR},
19760 {AliasPatternCond::K_Feature, AArch64::FeatureNEON},
19761 // (LD1Threev2s_POST GPR64sp:$Rn, VecListThree2s:$Vt, XZR) - 1112
19762 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
19763 {AliasPatternCond::K_RegClass, AArch64::DDDRegClassID},
19764 {AliasPatternCond::K_Ignore, 0},
19765 {AliasPatternCond::K_Reg, AArch64::XZR},
19766 {AliasPatternCond::K_Feature, AArch64::FeatureNEON},
19767 // (LD1Threev4h_POST GPR64sp:$Rn, VecListThree4h:$Vt, XZR) - 1117
19768 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
19769 {AliasPatternCond::K_RegClass, AArch64::DDDRegClassID},
19770 {AliasPatternCond::K_Ignore, 0},
19771 {AliasPatternCond::K_Reg, AArch64::XZR},
19772 {AliasPatternCond::K_Feature, AArch64::FeatureNEON},
19773 // (LD1Threev4s_POST GPR64sp:$Rn, VecListThree4s:$Vt, XZR) - 1122
19774 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
19775 {AliasPatternCond::K_RegClass, AArch64::QQQRegClassID},
19776 {AliasPatternCond::K_Ignore, 0},
19777 {AliasPatternCond::K_Reg, AArch64::XZR},
19778 {AliasPatternCond::K_Feature, AArch64::FeatureNEON},
19779 // (LD1Threev8b_POST GPR64sp:$Rn, VecListThree8b:$Vt, XZR) - 1127
19780 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
19781 {AliasPatternCond::K_RegClass, AArch64::DDDRegClassID},
19782 {AliasPatternCond::K_Ignore, 0},
19783 {AliasPatternCond::K_Reg, AArch64::XZR},
19784 {AliasPatternCond::K_Feature, AArch64::FeatureNEON},
19785 // (LD1Threev8h_POST GPR64sp:$Rn, VecListThree8h:$Vt, XZR) - 1132
19786 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
19787 {AliasPatternCond::K_RegClass, AArch64::QQQRegClassID},
19788 {AliasPatternCond::K_Ignore, 0},
19789 {AliasPatternCond::K_Reg, AArch64::XZR},
19790 {AliasPatternCond::K_Feature, AArch64::FeatureNEON},
19791 // (LD1Twov16b_POST GPR64sp:$Rn, VecListTwo16b:$Vt, XZR) - 1137
19792 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
19793 {AliasPatternCond::K_RegClass, AArch64::QQRegClassID},
19794 {AliasPatternCond::K_Ignore, 0},
19795 {AliasPatternCond::K_Reg, AArch64::XZR},
19796 {AliasPatternCond::K_Feature, AArch64::FeatureNEON},
19797 // (LD1Twov1d_POST GPR64sp:$Rn, VecListTwo1d:$Vt, XZR) - 1142
19798 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
19799 {AliasPatternCond::K_RegClass, AArch64::DDRegClassID},
19800 {AliasPatternCond::K_Ignore, 0},
19801 {AliasPatternCond::K_Reg, AArch64::XZR},
19802 {AliasPatternCond::K_Feature, AArch64::FeatureNEON},
19803 // (LD1Twov2d_POST GPR64sp:$Rn, VecListTwo2d:$Vt, XZR) - 1147
19804 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
19805 {AliasPatternCond::K_RegClass, AArch64::QQRegClassID},
19806 {AliasPatternCond::K_Ignore, 0},
19807 {AliasPatternCond::K_Reg, AArch64::XZR},
19808 {AliasPatternCond::K_Feature, AArch64::FeatureNEON},
19809 // (LD1Twov2s_POST GPR64sp:$Rn, VecListTwo2s:$Vt, XZR) - 1152
19810 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
19811 {AliasPatternCond::K_RegClass, AArch64::DDRegClassID},
19812 {AliasPatternCond::K_Ignore, 0},
19813 {AliasPatternCond::K_Reg, AArch64::XZR},
19814 {AliasPatternCond::K_Feature, AArch64::FeatureNEON},
19815 // (LD1Twov4h_POST GPR64sp:$Rn, VecListTwo4h:$Vt, XZR) - 1157
19816 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
19817 {AliasPatternCond::K_RegClass, AArch64::DDRegClassID},
19818 {AliasPatternCond::K_Ignore, 0},
19819 {AliasPatternCond::K_Reg, AArch64::XZR},
19820 {AliasPatternCond::K_Feature, AArch64::FeatureNEON},
19821 // (LD1Twov4s_POST GPR64sp:$Rn, VecListTwo4s:$Vt, XZR) - 1162
19822 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
19823 {AliasPatternCond::K_RegClass, AArch64::QQRegClassID},
19824 {AliasPatternCond::K_Ignore, 0},
19825 {AliasPatternCond::K_Reg, AArch64::XZR},
19826 {AliasPatternCond::K_Feature, AArch64::FeatureNEON},
19827 // (LD1Twov8b_POST GPR64sp:$Rn, VecListTwo8b:$Vt, XZR) - 1167
19828 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
19829 {AliasPatternCond::K_RegClass, AArch64::DDRegClassID},
19830 {AliasPatternCond::K_Ignore, 0},
19831 {AliasPatternCond::K_Reg, AArch64::XZR},
19832 {AliasPatternCond::K_Feature, AArch64::FeatureNEON},
19833 // (LD1Twov8h_POST GPR64sp:$Rn, VecListTwo8h:$Vt, XZR) - 1172
19834 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
19835 {AliasPatternCond::K_RegClass, AArch64::QQRegClassID},
19836 {AliasPatternCond::K_Ignore, 0},
19837 {AliasPatternCond::K_Reg, AArch64::XZR},
19838 {AliasPatternCond::K_Feature, AArch64::FeatureNEON},
19839 // (LD1W_D_IMM_REAL Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1177
19840 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
19841 {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID},
19842 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
19843 {AliasPatternCond::K_Imm, uint32_t(0)},
19844 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
19845 // (LD1W_IMM_REAL Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1182
19846 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
19847 {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID},
19848 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
19849 {AliasPatternCond::K_Imm, uint32_t(0)},
19850 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
19851 // (LD1i16_POST GPR64sp:$Rn, VecListOneh:$Vt, VectorIndexH:$idx, XZR) - 1187
19852 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
19853 {AliasPatternCond::K_RegClass, AArch64::FPR128RegClassID},
19854 {AliasPatternCond::K_Ignore, 0},
19855 {AliasPatternCond::K_Ignore, 0},
19856 {AliasPatternCond::K_Ignore, 0},
19857 {AliasPatternCond::K_Reg, AArch64::XZR},
19858 {AliasPatternCond::K_Feature, AArch64::FeatureNEON},
19859 // (LD1i32_POST GPR64sp:$Rn, VecListOnes:$Vt, VectorIndexS:$idx, XZR) - 1194
19860 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
19861 {AliasPatternCond::K_RegClass, AArch64::FPR128RegClassID},
19862 {AliasPatternCond::K_Ignore, 0},
19863 {AliasPatternCond::K_Ignore, 0},
19864 {AliasPatternCond::K_Ignore, 0},
19865 {AliasPatternCond::K_Reg, AArch64::XZR},
19866 {AliasPatternCond::K_Feature, AArch64::FeatureNEON},
19867 // (LD1i64_POST GPR64sp:$Rn, VecListOned:$Vt, VectorIndexD:$idx, XZR) - 1201
19868 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
19869 {AliasPatternCond::K_RegClass, AArch64::FPR128RegClassID},
19870 {AliasPatternCond::K_Ignore, 0},
19871 {AliasPatternCond::K_Ignore, 0},
19872 {AliasPatternCond::K_Ignore, 0},
19873 {AliasPatternCond::K_Reg, AArch64::XZR},
19874 {AliasPatternCond::K_Feature, AArch64::FeatureNEON},
19875 // (LD1i8_POST GPR64sp:$Rn, VecListOneb:$Vt, VectorIndexB:$idx, XZR) - 1208
19876 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
19877 {AliasPatternCond::K_RegClass, AArch64::FPR128RegClassID},
19878 {AliasPatternCond::K_Ignore, 0},
19879 {AliasPatternCond::K_Ignore, 0},
19880 {AliasPatternCond::K_Ignore, 0},
19881 {AliasPatternCond::K_Reg, AArch64::XZR},
19882 {AliasPatternCond::K_Feature, AArch64::FeatureNEON},
19883 // (LD2B_IMM ZZ_b:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1215
19884 {AliasPatternCond::K_RegClass, AArch64::ZPR2RegClassID},
19885 {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID},
19886 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
19887 {AliasPatternCond::K_Imm, uint32_t(0)},
19888 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
19889 // (LD2D_IMM ZZ_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1220
19890 {AliasPatternCond::K_RegClass, AArch64::ZPR2RegClassID},
19891 {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID},
19892 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
19893 {AliasPatternCond::K_Imm, uint32_t(0)},
19894 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
19895 // (LD2H_IMM ZZ_h:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1225
19896 {AliasPatternCond::K_RegClass, AArch64::ZPR2RegClassID},
19897 {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID},
19898 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
19899 {AliasPatternCond::K_Imm, uint32_t(0)},
19900 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
19901 // (LD2Rv16b_POST GPR64sp:$Rn, VecListTwo16b:$Vt, XZR) - 1230
19902 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
19903 {AliasPatternCond::K_RegClass, AArch64::QQRegClassID},
19904 {AliasPatternCond::K_Ignore, 0},
19905 {AliasPatternCond::K_Reg, AArch64::XZR},
19906 {AliasPatternCond::K_Feature, AArch64::FeatureNEON},
19907 // (LD2Rv1d_POST GPR64sp:$Rn, VecListTwo1d:$Vt, XZR) - 1235
19908 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
19909 {AliasPatternCond::K_RegClass, AArch64::DDRegClassID},
19910 {AliasPatternCond::K_Ignore, 0},
19911 {AliasPatternCond::K_Reg, AArch64::XZR},
19912 {AliasPatternCond::K_Feature, AArch64::FeatureNEON},
19913 // (LD2Rv2d_POST GPR64sp:$Rn, VecListTwo2d:$Vt, XZR) - 1240
19914 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
19915 {AliasPatternCond::K_RegClass, AArch64::QQRegClassID},
19916 {AliasPatternCond::K_Ignore, 0},
19917 {AliasPatternCond::K_Reg, AArch64::XZR},
19918 {AliasPatternCond::K_Feature, AArch64::FeatureNEON},
19919 // (LD2Rv2s_POST GPR64sp:$Rn, VecListTwo2s:$Vt, XZR) - 1245
19920 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
19921 {AliasPatternCond::K_RegClass, AArch64::DDRegClassID},
19922 {AliasPatternCond::K_Ignore, 0},
19923 {AliasPatternCond::K_Reg, AArch64::XZR},
19924 {AliasPatternCond::K_Feature, AArch64::FeatureNEON},
19925 // (LD2Rv4h_POST GPR64sp:$Rn, VecListTwo4h:$Vt, XZR) - 1250
19926 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
19927 {AliasPatternCond::K_RegClass, AArch64::DDRegClassID},
19928 {AliasPatternCond::K_Ignore, 0},
19929 {AliasPatternCond::K_Reg, AArch64::XZR},
19930 {AliasPatternCond::K_Feature, AArch64::FeatureNEON},
19931 // (LD2Rv4s_POST GPR64sp:$Rn, VecListTwo4s:$Vt, XZR) - 1255
19932 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
19933 {AliasPatternCond::K_RegClass, AArch64::QQRegClassID},
19934 {AliasPatternCond::K_Ignore, 0},
19935 {AliasPatternCond::K_Reg, AArch64::XZR},
19936 {AliasPatternCond::K_Feature, AArch64::FeatureNEON},
19937 // (LD2Rv8b_POST GPR64sp:$Rn, VecListTwo8b:$Vt, XZR) - 1260
19938 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
19939 {AliasPatternCond::K_RegClass, AArch64::DDRegClassID},
19940 {AliasPatternCond::K_Ignore, 0},
19941 {AliasPatternCond::K_Reg, AArch64::XZR},
19942 {AliasPatternCond::K_Feature, AArch64::FeatureNEON},
19943 // (LD2Rv8h_POST GPR64sp:$Rn, VecListTwo8h:$Vt, XZR) - 1265
19944 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
19945 {AliasPatternCond::K_RegClass, AArch64::QQRegClassID},
19946 {AliasPatternCond::K_Ignore, 0},
19947 {AliasPatternCond::K_Reg, AArch64::XZR},
19948 {AliasPatternCond::K_Feature, AArch64::FeatureNEON},
19949 // (LD2Twov16b_POST GPR64sp:$Rn, VecListTwo16b:$Vt, XZR) - 1270
19950 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
19951 {AliasPatternCond::K_RegClass, AArch64::QQRegClassID},
19952 {AliasPatternCond::K_Ignore, 0},
19953 {AliasPatternCond::K_Reg, AArch64::XZR},
19954 {AliasPatternCond::K_Feature, AArch64::FeatureNEON},
19955 // (LD2Twov2d_POST GPR64sp:$Rn, VecListTwo2d:$Vt, XZR) - 1275
19956 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
19957 {AliasPatternCond::K_RegClass, AArch64::QQRegClassID},
19958 {AliasPatternCond::K_Ignore, 0},
19959 {AliasPatternCond::K_Reg, AArch64::XZR},
19960 {AliasPatternCond::K_Feature, AArch64::FeatureNEON},
19961 // (LD2Twov2s_POST GPR64sp:$Rn, VecListTwo2s:$Vt, XZR) - 1280
19962 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
19963 {AliasPatternCond::K_RegClass, AArch64::DDRegClassID},
19964 {AliasPatternCond::K_Ignore, 0},
19965 {AliasPatternCond::K_Reg, AArch64::XZR},
19966 {AliasPatternCond::K_Feature, AArch64::FeatureNEON},
19967 // (LD2Twov4h_POST GPR64sp:$Rn, VecListTwo4h:$Vt, XZR) - 1285
19968 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
19969 {AliasPatternCond::K_RegClass, AArch64::DDRegClassID},
19970 {AliasPatternCond::K_Ignore, 0},
19971 {AliasPatternCond::K_Reg, AArch64::XZR},
19972 {AliasPatternCond::K_Feature, AArch64::FeatureNEON},
19973 // (LD2Twov4s_POST GPR64sp:$Rn, VecListTwo4s:$Vt, XZR) - 1290
19974 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
19975 {AliasPatternCond::K_RegClass, AArch64::QQRegClassID},
19976 {AliasPatternCond::K_Ignore, 0},
19977 {AliasPatternCond::K_Reg, AArch64::XZR},
19978 {AliasPatternCond::K_Feature, AArch64::FeatureNEON},
19979 // (LD2Twov8b_POST GPR64sp:$Rn, VecListTwo8b:$Vt, XZR) - 1295
19980 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
19981 {AliasPatternCond::K_RegClass, AArch64::DDRegClassID},
19982 {AliasPatternCond::K_Ignore, 0},
19983 {AliasPatternCond::K_Reg, AArch64::XZR},
19984 {AliasPatternCond::K_Feature, AArch64::FeatureNEON},
19985 // (LD2Twov8h_POST GPR64sp:$Rn, VecListTwo8h:$Vt, XZR) - 1300
19986 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
19987 {AliasPatternCond::K_RegClass, AArch64::QQRegClassID},
19988 {AliasPatternCond::K_Ignore, 0},
19989 {AliasPatternCond::K_Reg, AArch64::XZR},
19990 {AliasPatternCond::K_Feature, AArch64::FeatureNEON},
19991 // (LD2W_IMM ZZ_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1305
19992 {AliasPatternCond::K_RegClass, AArch64::ZPR2RegClassID},
19993 {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID},
19994 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
19995 {AliasPatternCond::K_Imm, uint32_t(0)},
19996 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
19997 // (LD2i16_POST GPR64sp:$Rn, VecListTwoh:$Vt, VectorIndexH:$idx, XZR) - 1310
19998 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
19999 {AliasPatternCond::K_RegClass, AArch64::QQRegClassID},
20000 {AliasPatternCond::K_Ignore, 0},
20001 {AliasPatternCond::K_Ignore, 0},
20002 {AliasPatternCond::K_Ignore, 0},
20003 {AliasPatternCond::K_Reg, AArch64::XZR},
20004 {AliasPatternCond::K_Feature, AArch64::FeatureNEON},
20005 // (LD2i32_POST GPR64sp:$Rn, VecListTwos:$Vt, VectorIndexS:$idx, XZR) - 1317
20006 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
20007 {AliasPatternCond::K_RegClass, AArch64::QQRegClassID},
20008 {AliasPatternCond::K_Ignore, 0},
20009 {AliasPatternCond::K_Ignore, 0},
20010 {AliasPatternCond::K_Ignore, 0},
20011 {AliasPatternCond::K_Reg, AArch64::XZR},
20012 {AliasPatternCond::K_Feature, AArch64::FeatureNEON},
20013 // (LD2i64_POST GPR64sp:$Rn, VecListTwod:$Vt, VectorIndexD:$idx, XZR) - 1324
20014 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
20015 {AliasPatternCond::K_RegClass, AArch64::QQRegClassID},
20016 {AliasPatternCond::K_Ignore, 0},
20017 {AliasPatternCond::K_Ignore, 0},
20018 {AliasPatternCond::K_Ignore, 0},
20019 {AliasPatternCond::K_Reg, AArch64::XZR},
20020 {AliasPatternCond::K_Feature, AArch64::FeatureNEON},
20021 // (LD2i8_POST GPR64sp:$Rn, VecListTwob:$Vt, VectorIndexB:$idx, XZR) - 1331
20022 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
20023 {AliasPatternCond::K_RegClass, AArch64::QQRegClassID},
20024 {AliasPatternCond::K_Ignore, 0},
20025 {AliasPatternCond::K_Ignore, 0},
20026 {AliasPatternCond::K_Ignore, 0},
20027 {AliasPatternCond::K_Reg, AArch64::XZR},
20028 {AliasPatternCond::K_Feature, AArch64::FeatureNEON},
20029 // (LD3B_IMM ZZZ_b:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1338
20030 {AliasPatternCond::K_RegClass, AArch64::ZPR3RegClassID},
20031 {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID},
20032 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
20033 {AliasPatternCond::K_Imm, uint32_t(0)},
20034 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
20035 // (LD3D_IMM ZZZ_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1343
20036 {AliasPatternCond::K_RegClass, AArch64::ZPR3RegClassID},
20037 {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID},
20038 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
20039 {AliasPatternCond::K_Imm, uint32_t(0)},
20040 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
20041 // (LD3H_IMM ZZZ_h:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1348
20042 {AliasPatternCond::K_RegClass, AArch64::ZPR3RegClassID},
20043 {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID},
20044 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
20045 {AliasPatternCond::K_Imm, uint32_t(0)},
20046 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
20047 // (LD3Rv16b_POST GPR64sp:$Rn, VecListThree16b:$Vt, XZR) - 1353
20048 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
20049 {AliasPatternCond::K_RegClass, AArch64::QQQRegClassID},
20050 {AliasPatternCond::K_Ignore, 0},
20051 {AliasPatternCond::K_Reg, AArch64::XZR},
20052 {AliasPatternCond::K_Feature, AArch64::FeatureNEON},
20053 // (LD3Rv1d_POST GPR64sp:$Rn, VecListThree1d:$Vt, XZR) - 1358
20054 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
20055 {AliasPatternCond::K_RegClass, AArch64::DDDRegClassID},
20056 {AliasPatternCond::K_Ignore, 0},
20057 {AliasPatternCond::K_Reg, AArch64::XZR},
20058 {AliasPatternCond::K_Feature, AArch64::FeatureNEON},
20059 // (LD3Rv2d_POST GPR64sp:$Rn, VecListThree2d:$Vt, XZR) - 1363
20060 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
20061 {AliasPatternCond::K_RegClass, AArch64::QQQRegClassID},
20062 {AliasPatternCond::K_Ignore, 0},
20063 {AliasPatternCond::K_Reg, AArch64::XZR},
20064 {AliasPatternCond::K_Feature, AArch64::FeatureNEON},
20065 // (LD3Rv2s_POST GPR64sp:$Rn, VecListThree2s:$Vt, XZR) - 1368
20066 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
20067 {AliasPatternCond::K_RegClass, AArch64::DDDRegClassID},
20068 {AliasPatternCond::K_Ignore, 0},
20069 {AliasPatternCond::K_Reg, AArch64::XZR},
20070 {AliasPatternCond::K_Feature, AArch64::FeatureNEON},
20071 // (LD3Rv4h_POST GPR64sp:$Rn, VecListThree4h:$Vt, XZR) - 1373
20072 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
20073 {AliasPatternCond::K_RegClass, AArch64::DDDRegClassID},
20074 {AliasPatternCond::K_Ignore, 0},
20075 {AliasPatternCond::K_Reg, AArch64::XZR},
20076 {AliasPatternCond::K_Feature, AArch64::FeatureNEON},
20077 // (LD3Rv4s_POST GPR64sp:$Rn, VecListThree4s:$Vt, XZR) - 1378
20078 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
20079 {AliasPatternCond::K_RegClass, AArch64::QQQRegClassID},
20080 {AliasPatternCond::K_Ignore, 0},
20081 {AliasPatternCond::K_Reg, AArch64::XZR},
20082 {AliasPatternCond::K_Feature, AArch64::FeatureNEON},
20083 // (LD3Rv8b_POST GPR64sp:$Rn, VecListThree8b:$Vt, XZR) - 1383
20084 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
20085 {AliasPatternCond::K_RegClass, AArch64::DDDRegClassID},
20086 {AliasPatternCond::K_Ignore, 0},
20087 {AliasPatternCond::K_Reg, AArch64::XZR},
20088 {AliasPatternCond::K_Feature, AArch64::FeatureNEON},
20089 // (LD3Rv8h_POST GPR64sp:$Rn, VecListThree8h:$Vt, XZR) - 1388
20090 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
20091 {AliasPatternCond::K_RegClass, AArch64::QQQRegClassID},
20092 {AliasPatternCond::K_Ignore, 0},
20093 {AliasPatternCond::K_Reg, AArch64::XZR},
20094 {AliasPatternCond::K_Feature, AArch64::FeatureNEON},
20095 // (LD3Threev16b_POST GPR64sp:$Rn, VecListThree16b:$Vt, XZR) - 1393
20096 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
20097 {AliasPatternCond::K_RegClass, AArch64::QQQRegClassID},
20098 {AliasPatternCond::K_Ignore, 0},
20099 {AliasPatternCond::K_Reg, AArch64::XZR},
20100 {AliasPatternCond::K_Feature, AArch64::FeatureNEON},
20101 // (LD3Threev2d_POST GPR64sp:$Rn, VecListThree2d:$Vt, XZR) - 1398
20102 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
20103 {AliasPatternCond::K_RegClass, AArch64::QQQRegClassID},
20104 {AliasPatternCond::K_Ignore, 0},
20105 {AliasPatternCond::K_Reg, AArch64::XZR},
20106 {AliasPatternCond::K_Feature, AArch64::FeatureNEON},
20107 // (LD3Threev2s_POST GPR64sp:$Rn, VecListThree2s:$Vt, XZR) - 1403
20108 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
20109 {AliasPatternCond::K_RegClass, AArch64::DDDRegClassID},
20110 {AliasPatternCond::K_Ignore, 0},
20111 {AliasPatternCond::K_Reg, AArch64::XZR},
20112 {AliasPatternCond::K_Feature, AArch64::FeatureNEON},
20113 // (LD3Threev4h_POST GPR64sp:$Rn, VecListThree4h:$Vt, XZR) - 1408
20114 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
20115 {AliasPatternCond::K_RegClass, AArch64::DDDRegClassID},
20116 {AliasPatternCond::K_Ignore, 0},
20117 {AliasPatternCond::K_Reg, AArch64::XZR},
20118 {AliasPatternCond::K_Feature, AArch64::FeatureNEON},
20119 // (LD3Threev4s_POST GPR64sp:$Rn, VecListThree4s:$Vt, XZR) - 1413
20120 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
20121 {AliasPatternCond::K_RegClass, AArch64::QQQRegClassID},
20122 {AliasPatternCond::K_Ignore, 0},
20123 {AliasPatternCond::K_Reg, AArch64::XZR},
20124 {AliasPatternCond::K_Feature, AArch64::FeatureNEON},
20125 // (LD3Threev8b_POST GPR64sp:$Rn, VecListThree8b:$Vt, XZR) - 1418
20126 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
20127 {AliasPatternCond::K_RegClass, AArch64::DDDRegClassID},
20128 {AliasPatternCond::K_Ignore, 0},
20129 {AliasPatternCond::K_Reg, AArch64::XZR},
20130 {AliasPatternCond::K_Feature, AArch64::FeatureNEON},
20131 // (LD3Threev8h_POST GPR64sp:$Rn, VecListThree8h:$Vt, XZR) - 1423
20132 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
20133 {AliasPatternCond::K_RegClass, AArch64::QQQRegClassID},
20134 {AliasPatternCond::K_Ignore, 0},
20135 {AliasPatternCond::K_Reg, AArch64::XZR},
20136 {AliasPatternCond::K_Feature, AArch64::FeatureNEON},
20137 // (LD3W_IMM ZZZ_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1428
20138 {AliasPatternCond::K_RegClass, AArch64::ZPR3RegClassID},
20139 {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID},
20140 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
20141 {AliasPatternCond::K_Imm, uint32_t(0)},
20142 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
20143 // (LD3i16_POST GPR64sp:$Rn, VecListThreeh:$Vt, VectorIndexH:$idx, XZR) - 1433
20144 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
20145 {AliasPatternCond::K_RegClass, AArch64::QQQRegClassID},
20146 {AliasPatternCond::K_Ignore, 0},
20147 {AliasPatternCond::K_Ignore, 0},
20148 {AliasPatternCond::K_Ignore, 0},
20149 {AliasPatternCond::K_Reg, AArch64::XZR},
20150 {AliasPatternCond::K_Feature, AArch64::FeatureNEON},
20151 // (LD3i32_POST GPR64sp:$Rn, VecListThrees:$Vt, VectorIndexS:$idx, XZR) - 1440
20152 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
20153 {AliasPatternCond::K_RegClass, AArch64::QQQRegClassID},
20154 {AliasPatternCond::K_Ignore, 0},
20155 {AliasPatternCond::K_Ignore, 0},
20156 {AliasPatternCond::K_Ignore, 0},
20157 {AliasPatternCond::K_Reg, AArch64::XZR},
20158 {AliasPatternCond::K_Feature, AArch64::FeatureNEON},
20159 // (LD3i64_POST GPR64sp:$Rn, VecListThreed:$Vt, VectorIndexD:$idx, XZR) - 1447
20160 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
20161 {AliasPatternCond::K_RegClass, AArch64::QQQRegClassID},
20162 {AliasPatternCond::K_Ignore, 0},
20163 {AliasPatternCond::K_Ignore, 0},
20164 {AliasPatternCond::K_Ignore, 0},
20165 {AliasPatternCond::K_Reg, AArch64::XZR},
20166 {AliasPatternCond::K_Feature, AArch64::FeatureNEON},
20167 // (LD3i8_POST GPR64sp:$Rn, VecListThreeb:$Vt, VectorIndexB:$idx, XZR) - 1454
20168 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
20169 {AliasPatternCond::K_RegClass, AArch64::QQQRegClassID},
20170 {AliasPatternCond::K_Ignore, 0},
20171 {AliasPatternCond::K_Ignore, 0},
20172 {AliasPatternCond::K_Ignore, 0},
20173 {AliasPatternCond::K_Reg, AArch64::XZR},
20174 {AliasPatternCond::K_Feature, AArch64::FeatureNEON},
20175 // (LD4B_IMM ZZZZ_b:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1461
20176 {AliasPatternCond::K_RegClass, AArch64::ZPR4RegClassID},
20177 {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID},
20178 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
20179 {AliasPatternCond::K_Imm, uint32_t(0)},
20180 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
20181 // (LD4D_IMM ZZZZ_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1466
20182 {AliasPatternCond::K_RegClass, AArch64::ZPR4RegClassID},
20183 {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID},
20184 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
20185 {AliasPatternCond::K_Imm, uint32_t(0)},
20186 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
20187 // (LD4Fourv16b_POST GPR64sp:$Rn, VecListFour16b:$Vt, XZR) - 1471
20188 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
20189 {AliasPatternCond::K_RegClass, AArch64::QQQQRegClassID},
20190 {AliasPatternCond::K_Ignore, 0},
20191 {AliasPatternCond::K_Reg, AArch64::XZR},
20192 {AliasPatternCond::K_Feature, AArch64::FeatureNEON},
20193 // (LD4Fourv2d_POST GPR64sp:$Rn, VecListFour2d:$Vt, XZR) - 1476
20194 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
20195 {AliasPatternCond::K_RegClass, AArch64::QQQQRegClassID},
20196 {AliasPatternCond::K_Ignore, 0},
20197 {AliasPatternCond::K_Reg, AArch64::XZR},
20198 {AliasPatternCond::K_Feature, AArch64::FeatureNEON},
20199 // (LD4Fourv2s_POST GPR64sp:$Rn, VecListFour2s:$Vt, XZR) - 1481
20200 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
20201 {AliasPatternCond::K_RegClass, AArch64::DDDDRegClassID},
20202 {AliasPatternCond::K_Ignore, 0},
20203 {AliasPatternCond::K_Reg, AArch64::XZR},
20204 {AliasPatternCond::K_Feature, AArch64::FeatureNEON},
20205 // (LD4Fourv4h_POST GPR64sp:$Rn, VecListFour4h:$Vt, XZR) - 1486
20206 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
20207 {AliasPatternCond::K_RegClass, AArch64::DDDDRegClassID},
20208 {AliasPatternCond::K_Ignore, 0},
20209 {AliasPatternCond::K_Reg, AArch64::XZR},
20210 {AliasPatternCond::K_Feature, AArch64::FeatureNEON},
20211 // (LD4Fourv4s_POST GPR64sp:$Rn, VecListFour4s:$Vt, XZR) - 1491
20212 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
20213 {AliasPatternCond::K_RegClass, AArch64::QQQQRegClassID},
20214 {AliasPatternCond::K_Ignore, 0},
20215 {AliasPatternCond::K_Reg, AArch64::XZR},
20216 {AliasPatternCond::K_Feature, AArch64::FeatureNEON},
20217 // (LD4Fourv8b_POST GPR64sp:$Rn, VecListFour8b:$Vt, XZR) - 1496
20218 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
20219 {AliasPatternCond::K_RegClass, AArch64::DDDDRegClassID},
20220 {AliasPatternCond::K_Ignore, 0},
20221 {AliasPatternCond::K_Reg, AArch64::XZR},
20222 {AliasPatternCond::K_Feature, AArch64::FeatureNEON},
20223 // (LD4Fourv8h_POST GPR64sp:$Rn, VecListFour8h:$Vt, XZR) - 1501
20224 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
20225 {AliasPatternCond::K_RegClass, AArch64::QQQQRegClassID},
20226 {AliasPatternCond::K_Ignore, 0},
20227 {AliasPatternCond::K_Reg, AArch64::XZR},
20228 {AliasPatternCond::K_Feature, AArch64::FeatureNEON},
20229 // (LD4H_IMM ZZZZ_h:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1506
20230 {AliasPatternCond::K_RegClass, AArch64::ZPR4RegClassID},
20231 {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID},
20232 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
20233 {AliasPatternCond::K_Imm, uint32_t(0)},
20234 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
20235 // (LD4Rv16b_POST GPR64sp:$Rn, VecListFour16b:$Vt, XZR) - 1511
20236 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
20237 {AliasPatternCond::K_RegClass, AArch64::QQQQRegClassID},
20238 {AliasPatternCond::K_Ignore, 0},
20239 {AliasPatternCond::K_Reg, AArch64::XZR},
20240 {AliasPatternCond::K_Feature, AArch64::FeatureNEON},
20241 // (LD4Rv1d_POST GPR64sp:$Rn, VecListFour1d:$Vt, XZR) - 1516
20242 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
20243 {AliasPatternCond::K_RegClass, AArch64::DDDDRegClassID},
20244 {AliasPatternCond::K_Ignore, 0},
20245 {AliasPatternCond::K_Reg, AArch64::XZR},
20246 {AliasPatternCond::K_Feature, AArch64::FeatureNEON},
20247 // (LD4Rv2d_POST GPR64sp:$Rn, VecListFour2d:$Vt, XZR) - 1521
20248 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
20249 {AliasPatternCond::K_RegClass, AArch64::QQQQRegClassID},
20250 {AliasPatternCond::K_Ignore, 0},
20251 {AliasPatternCond::K_Reg, AArch64::XZR},
20252 {AliasPatternCond::K_Feature, AArch64::FeatureNEON},
20253 // (LD4Rv2s_POST GPR64sp:$Rn, VecListFour2s:$Vt, XZR) - 1526
20254 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
20255 {AliasPatternCond::K_RegClass, AArch64::DDDDRegClassID},
20256 {AliasPatternCond::K_Ignore, 0},
20257 {AliasPatternCond::K_Reg, AArch64::XZR},
20258 {AliasPatternCond::K_Feature, AArch64::FeatureNEON},
20259 // (LD4Rv4h_POST GPR64sp:$Rn, VecListFour4h:$Vt, XZR) - 1531
20260 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
20261 {AliasPatternCond::K_RegClass, AArch64::DDDDRegClassID},
20262 {AliasPatternCond::K_Ignore, 0},
20263 {AliasPatternCond::K_Reg, AArch64::XZR},
20264 {AliasPatternCond::K_Feature, AArch64::FeatureNEON},
20265 // (LD4Rv4s_POST GPR64sp:$Rn, VecListFour4s:$Vt, XZR) - 1536
20266 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
20267 {AliasPatternCond::K_RegClass, AArch64::QQQQRegClassID},
20268 {AliasPatternCond::K_Ignore, 0},
20269 {AliasPatternCond::K_Reg, AArch64::XZR},
20270 {AliasPatternCond::K_Feature, AArch64::FeatureNEON},
20271 // (LD4Rv8b_POST GPR64sp:$Rn, VecListFour8b:$Vt, XZR) - 1541
20272 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
20273 {AliasPatternCond::K_RegClass, AArch64::DDDDRegClassID},
20274 {AliasPatternCond::K_Ignore, 0},
20275 {AliasPatternCond::K_Reg, AArch64::XZR},
20276 {AliasPatternCond::K_Feature, AArch64::FeatureNEON},
20277 // (LD4Rv8h_POST GPR64sp:$Rn, VecListFour8h:$Vt, XZR) - 1546
20278 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
20279 {AliasPatternCond::K_RegClass, AArch64::QQQQRegClassID},
20280 {AliasPatternCond::K_Ignore, 0},
20281 {AliasPatternCond::K_Reg, AArch64::XZR},
20282 {AliasPatternCond::K_Feature, AArch64::FeatureNEON},
20283 // (LD4W_IMM ZZZZ_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1551
20284 {AliasPatternCond::K_RegClass, AArch64::ZPR4RegClassID},
20285 {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID},
20286 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
20287 {AliasPatternCond::K_Imm, uint32_t(0)},
20288 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
20289 // (LD4i16_POST GPR64sp:$Rn, VecListFourh:$Vt, VectorIndexH:$idx, XZR) - 1556
20290 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
20291 {AliasPatternCond::K_RegClass, AArch64::QQQQRegClassID},
20292 {AliasPatternCond::K_Ignore, 0},
20293 {AliasPatternCond::K_Ignore, 0},
20294 {AliasPatternCond::K_Ignore, 0},
20295 {AliasPatternCond::K_Reg, AArch64::XZR},
20296 {AliasPatternCond::K_Feature, AArch64::FeatureNEON},
20297 // (LD4i32_POST GPR64sp:$Rn, VecListFours:$Vt, VectorIndexS:$idx, XZR) - 1563
20298 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
20299 {AliasPatternCond::K_RegClass, AArch64::QQQQRegClassID},
20300 {AliasPatternCond::K_Ignore, 0},
20301 {AliasPatternCond::K_Ignore, 0},
20302 {AliasPatternCond::K_Ignore, 0},
20303 {AliasPatternCond::K_Reg, AArch64::XZR},
20304 {AliasPatternCond::K_Feature, AArch64::FeatureNEON},
20305 // (LD4i64_POST GPR64sp:$Rn, VecListFourd:$Vt, VectorIndexD:$idx, XZR) - 1570
20306 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
20307 {AliasPatternCond::K_RegClass, AArch64::QQQQRegClassID},
20308 {AliasPatternCond::K_Ignore, 0},
20309 {AliasPatternCond::K_Ignore, 0},
20310 {AliasPatternCond::K_Ignore, 0},
20311 {AliasPatternCond::K_Reg, AArch64::XZR},
20312 {AliasPatternCond::K_Feature, AArch64::FeatureNEON},
20313 // (LD4i8_POST GPR64sp:$Rn, VecListFourb:$Vt, VectorIndexB:$idx, XZR) - 1577
20314 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
20315 {AliasPatternCond::K_RegClass, AArch64::QQQQRegClassID},
20316 {AliasPatternCond::K_Ignore, 0},
20317 {AliasPatternCond::K_Ignore, 0},
20318 {AliasPatternCond::K_Ignore, 0},
20319 {AliasPatternCond::K_Reg, AArch64::XZR},
20320 {AliasPatternCond::K_Feature, AArch64::FeatureNEON},
20321 // (LDADDB WZR, GPR32:$Rs, GPR64sp:$Rn) - 1584
20322 {AliasPatternCond::K_Reg, AArch64::WZR},
20323 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
20324 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
20325 {AliasPatternCond::K_Feature, AArch64::FeatureLSE},
20326 // (LDADDH WZR, GPR32:$Rs, GPR64sp:$Rn) - 1588
20327 {AliasPatternCond::K_Reg, AArch64::WZR},
20328 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
20329 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
20330 {AliasPatternCond::K_Feature, AArch64::FeatureLSE},
20331 // (LDADDLB WZR, GPR32:$Rs, GPR64sp:$Rn) - 1592
20332 {AliasPatternCond::K_Reg, AArch64::WZR},
20333 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
20334 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
20335 {AliasPatternCond::K_Feature, AArch64::FeatureLSE},
20336 // (LDADDLH WZR, GPR32:$Rs, GPR64sp:$Rn) - 1596
20337 {AliasPatternCond::K_Reg, AArch64::WZR},
20338 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
20339 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
20340 {AliasPatternCond::K_Feature, AArch64::FeatureLSE},
20341 // (LDADDLW WZR, GPR32:$Rs, GPR64sp:$Rn) - 1600
20342 {AliasPatternCond::K_Reg, AArch64::WZR},
20343 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
20344 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
20345 {AliasPatternCond::K_Feature, AArch64::FeatureLSE},
20346 // (LDADDLX XZR, GPR64:$Rs, GPR64sp:$Rn) - 1604
20347 {AliasPatternCond::K_Reg, AArch64::XZR},
20348 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
20349 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
20350 {AliasPatternCond::K_Feature, AArch64::FeatureLSE},
20351 // (LDADDW WZR, GPR32:$Rs, GPR64sp:$Rn) - 1608
20352 {AliasPatternCond::K_Reg, AArch64::WZR},
20353 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
20354 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
20355 {AliasPatternCond::K_Feature, AArch64::FeatureLSE},
20356 // (LDADDX XZR, GPR64:$Rs, GPR64sp:$Rn) - 1612
20357 {AliasPatternCond::K_Reg, AArch64::XZR},
20358 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
20359 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
20360 {AliasPatternCond::K_Feature, AArch64::FeatureLSE},
20361 // (LDAPURBi GPR32:$Rt, GPR64sp:$Rn, 0) - 1616
20362 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
20363 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
20364 {AliasPatternCond::K_Imm, uint32_t(0)},
20365 {AliasPatternCond::K_Feature, AArch64::FeatureRCPC_IMMO},
20366 // (LDAPURHi GPR32:$Rt, GPR64sp:$Rn, 0) - 1620
20367 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
20368 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
20369 {AliasPatternCond::K_Imm, uint32_t(0)},
20370 {AliasPatternCond::K_Feature, AArch64::FeatureRCPC_IMMO},
20371 // (LDAPURSBWi GPR32:$Rt, GPR64sp:$Rn, 0) - 1624
20372 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
20373 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
20374 {AliasPatternCond::K_Imm, uint32_t(0)},
20375 {AliasPatternCond::K_Feature, AArch64::FeatureRCPC_IMMO},
20376 // (LDAPURSBXi GPR64:$Rt, GPR64sp:$Rn, 0) - 1628
20377 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
20378 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
20379 {AliasPatternCond::K_Imm, uint32_t(0)},
20380 {AliasPatternCond::K_Feature, AArch64::FeatureRCPC_IMMO},
20381 // (LDAPURSHWi GPR32:$Rt, GPR64sp:$Rn, 0) - 1632
20382 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
20383 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
20384 {AliasPatternCond::K_Imm, uint32_t(0)},
20385 {AliasPatternCond::K_Feature, AArch64::FeatureRCPC_IMMO},
20386 // (LDAPURSHXi GPR64:$Rt, GPR64sp:$Rn, 0) - 1636
20387 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
20388 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
20389 {AliasPatternCond::K_Imm, uint32_t(0)},
20390 {AliasPatternCond::K_Feature, AArch64::FeatureRCPC_IMMO},
20391 // (LDAPURSWi GPR64:$Rt, GPR64sp:$Rn, 0) - 1640
20392 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
20393 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
20394 {AliasPatternCond::K_Imm, uint32_t(0)},
20395 {AliasPatternCond::K_Feature, AArch64::FeatureRCPC_IMMO},
20396 // (LDAPURXi GPR64:$Rt, GPR64sp:$Rn, 0) - 1644
20397 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
20398 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
20399 {AliasPatternCond::K_Imm, uint32_t(0)},
20400 {AliasPatternCond::K_Feature, AArch64::FeatureRCPC_IMMO},
20401 // (LDAPURi GPR32:$Rt, GPR64sp:$Rn, 0) - 1648
20402 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
20403 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
20404 {AliasPatternCond::K_Imm, uint32_t(0)},
20405 {AliasPatternCond::K_Feature, AArch64::FeatureRCPC_IMMO},
20406 // (LDCLRB WZR, GPR32:$Rs, GPR64sp:$Rn) - 1652
20407 {AliasPatternCond::K_Reg, AArch64::WZR},
20408 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
20409 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
20410 {AliasPatternCond::K_Feature, AArch64::FeatureLSE},
20411 // (LDCLRH WZR, GPR32:$Rs, GPR64sp:$Rn) - 1656
20412 {AliasPatternCond::K_Reg, AArch64::WZR},
20413 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
20414 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
20415 {AliasPatternCond::K_Feature, AArch64::FeatureLSE},
20416 // (LDCLRLB WZR, GPR32:$Rs, GPR64sp:$Rn) - 1660
20417 {AliasPatternCond::K_Reg, AArch64::WZR},
20418 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
20419 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
20420 {AliasPatternCond::K_Feature, AArch64::FeatureLSE},
20421 // (LDCLRLH WZR, GPR32:$Rs, GPR64sp:$Rn) - 1664
20422 {AliasPatternCond::K_Reg, AArch64::WZR},
20423 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
20424 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
20425 {AliasPatternCond::K_Feature, AArch64::FeatureLSE},
20426 // (LDCLRLW WZR, GPR32:$Rs, GPR64sp:$Rn) - 1668
20427 {AliasPatternCond::K_Reg, AArch64::WZR},
20428 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
20429 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
20430 {AliasPatternCond::K_Feature, AArch64::FeatureLSE},
20431 // (LDCLRLX XZR, GPR64:$Rs, GPR64sp:$Rn) - 1672
20432 {AliasPatternCond::K_Reg, AArch64::XZR},
20433 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
20434 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
20435 {AliasPatternCond::K_Feature, AArch64::FeatureLSE},
20436 // (LDCLRW WZR, GPR32:$Rs, GPR64sp:$Rn) - 1676
20437 {AliasPatternCond::K_Reg, AArch64::WZR},
20438 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
20439 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
20440 {AliasPatternCond::K_Feature, AArch64::FeatureLSE},
20441 // (LDCLRX XZR, GPR64:$Rs, GPR64sp:$Rn) - 1680
20442 {AliasPatternCond::K_Reg, AArch64::XZR},
20443 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
20444 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
20445 {AliasPatternCond::K_Feature, AArch64::FeatureLSE},
20446 // (LDEORB WZR, GPR32:$Rs, GPR64sp:$Rn) - 1684
20447 {AliasPatternCond::K_Reg, AArch64::WZR},
20448 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
20449 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
20450 {AliasPatternCond::K_Feature, AArch64::FeatureLSE},
20451 // (LDEORH WZR, GPR32:$Rs, GPR64sp:$Rn) - 1688
20452 {AliasPatternCond::K_Reg, AArch64::WZR},
20453 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
20454 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
20455 {AliasPatternCond::K_Feature, AArch64::FeatureLSE},
20456 // (LDEORLB WZR, GPR32:$Rs, GPR64sp:$Rn) - 1692
20457 {AliasPatternCond::K_Reg, AArch64::WZR},
20458 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
20459 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
20460 {AliasPatternCond::K_Feature, AArch64::FeatureLSE},
20461 // (LDEORLH WZR, GPR32:$Rs, GPR64sp:$Rn) - 1696
20462 {AliasPatternCond::K_Reg, AArch64::WZR},
20463 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
20464 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
20465 {AliasPatternCond::K_Feature, AArch64::FeatureLSE},
20466 // (LDEORLW WZR, GPR32:$Rs, GPR64sp:$Rn) - 1700
20467 {AliasPatternCond::K_Reg, AArch64::WZR},
20468 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
20469 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
20470 {AliasPatternCond::K_Feature, AArch64::FeatureLSE},
20471 // (LDEORLX XZR, GPR64:$Rs, GPR64sp:$Rn) - 1704
20472 {AliasPatternCond::K_Reg, AArch64::XZR},
20473 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
20474 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
20475 {AliasPatternCond::K_Feature, AArch64::FeatureLSE},
20476 // (LDEORW WZR, GPR32:$Rs, GPR64sp:$Rn) - 1708
20477 {AliasPatternCond::K_Reg, AArch64::WZR},
20478 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
20479 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
20480 {AliasPatternCond::K_Feature, AArch64::FeatureLSE},
20481 // (LDEORX XZR, GPR64:$Rs, GPR64sp:$Rn) - 1712
20482 {AliasPatternCond::K_Reg, AArch64::XZR},
20483 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
20484 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
20485 {AliasPatternCond::K_Feature, AArch64::FeatureLSE},
20486 // (LDFF1B_D_REAL Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, XZR) - 1716
20487 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
20488 {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID},
20489 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
20490 {AliasPatternCond::K_Reg, AArch64::XZR},
20491 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
20492 // (LDFF1B_H_REAL Z_h:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, XZR) - 1721
20493 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
20494 {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID},
20495 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
20496 {AliasPatternCond::K_Reg, AArch64::XZR},
20497 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
20498 // (LDFF1B_REAL Z_b:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, XZR) - 1726
20499 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
20500 {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID},
20501 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
20502 {AliasPatternCond::K_Reg, AArch64::XZR},
20503 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
20504 // (LDFF1B_S_REAL Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, XZR) - 1731
20505 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
20506 {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID},
20507 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
20508 {AliasPatternCond::K_Reg, AArch64::XZR},
20509 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
20510 // (LDFF1D_REAL Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, XZR) - 1736
20511 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
20512 {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID},
20513 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
20514 {AliasPatternCond::K_Reg, AArch64::XZR},
20515 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
20516 // (LDFF1H_D_REAL Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, XZR) - 1741
20517 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
20518 {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID},
20519 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
20520 {AliasPatternCond::K_Reg, AArch64::XZR},
20521 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
20522 // (LDFF1H_REAL Z_h:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, XZR) - 1746
20523 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
20524 {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID},
20525 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
20526 {AliasPatternCond::K_Reg, AArch64::XZR},
20527 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
20528 // (LDFF1H_S_REAL Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, XZR) - 1751
20529 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
20530 {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID},
20531 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
20532 {AliasPatternCond::K_Reg, AArch64::XZR},
20533 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
20534 // (LDFF1SB_D_REAL Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, XZR) - 1756
20535 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
20536 {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID},
20537 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
20538 {AliasPatternCond::K_Reg, AArch64::XZR},
20539 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
20540 // (LDFF1SB_H_REAL Z_h:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, XZR) - 1761
20541 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
20542 {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID},
20543 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
20544 {AliasPatternCond::K_Reg, AArch64::XZR},
20545 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
20546 // (LDFF1SB_S_REAL Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, XZR) - 1766
20547 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
20548 {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID},
20549 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
20550 {AliasPatternCond::K_Reg, AArch64::XZR},
20551 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
20552 // (LDFF1SH_D_REAL Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, XZR) - 1771
20553 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
20554 {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID},
20555 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
20556 {AliasPatternCond::K_Reg, AArch64::XZR},
20557 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
20558 // (LDFF1SH_S_REAL Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, XZR) - 1776
20559 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
20560 {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID},
20561 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
20562 {AliasPatternCond::K_Reg, AArch64::XZR},
20563 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
20564 // (LDFF1SW_D_REAL Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, XZR) - 1781
20565 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
20566 {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID},
20567 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
20568 {AliasPatternCond::K_Reg, AArch64::XZR},
20569 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
20570 // (LDFF1W_D_REAL Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, XZR) - 1786
20571 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
20572 {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID},
20573 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
20574 {AliasPatternCond::K_Reg, AArch64::XZR},
20575 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
20576 // (LDFF1W_REAL Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, XZR) - 1791
20577 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
20578 {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID},
20579 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
20580 {AliasPatternCond::K_Reg, AArch64::XZR},
20581 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
20582 // (LDG GPR64:$Rt, GPR64sp:$Rn, 0) - 1796
20583 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
20584 {AliasPatternCond::K_Ignore, 0},
20585 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
20586 {AliasPatternCond::K_Imm, uint32_t(0)},
20587 {AliasPatternCond::K_Feature, AArch64::FeatureMTE},
20588 // (LDNF1B_D_IMM_REAL Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1801
20589 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
20590 {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID},
20591 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
20592 {AliasPatternCond::K_Imm, uint32_t(0)},
20593 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
20594 // (LDNF1B_H_IMM_REAL Z_h:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1806
20595 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
20596 {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID},
20597 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
20598 {AliasPatternCond::K_Imm, uint32_t(0)},
20599 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
20600 // (LDNF1B_IMM_REAL Z_b:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1811
20601 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
20602 {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID},
20603 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
20604 {AliasPatternCond::K_Imm, uint32_t(0)},
20605 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
20606 // (LDNF1B_S_IMM_REAL Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1816
20607 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
20608 {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID},
20609 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
20610 {AliasPatternCond::K_Imm, uint32_t(0)},
20611 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
20612 // (LDNF1D_IMM_REAL Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1821
20613 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
20614 {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID},
20615 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
20616 {AliasPatternCond::K_Imm, uint32_t(0)},
20617 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
20618 // (LDNF1H_D_IMM_REAL Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1826
20619 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
20620 {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID},
20621 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
20622 {AliasPatternCond::K_Imm, uint32_t(0)},
20623 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
20624 // (LDNF1H_IMM_REAL Z_h:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1831
20625 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
20626 {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID},
20627 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
20628 {AliasPatternCond::K_Imm, uint32_t(0)},
20629 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
20630 // (LDNF1H_S_IMM_REAL Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1836
20631 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
20632 {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID},
20633 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
20634 {AliasPatternCond::K_Imm, uint32_t(0)},
20635 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
20636 // (LDNF1SB_D_IMM_REAL Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1841
20637 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
20638 {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID},
20639 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
20640 {AliasPatternCond::K_Imm, uint32_t(0)},
20641 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
20642 // (LDNF1SB_H_IMM_REAL Z_h:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1846
20643 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
20644 {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID},
20645 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
20646 {AliasPatternCond::K_Imm, uint32_t(0)},
20647 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
20648 // (LDNF1SB_S_IMM_REAL Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1851
20649 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
20650 {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID},
20651 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
20652 {AliasPatternCond::K_Imm, uint32_t(0)},
20653 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
20654 // (LDNF1SH_D_IMM_REAL Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1856
20655 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
20656 {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID},
20657 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
20658 {AliasPatternCond::K_Imm, uint32_t(0)},
20659 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
20660 // (LDNF1SH_S_IMM_REAL Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1861
20661 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
20662 {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID},
20663 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
20664 {AliasPatternCond::K_Imm, uint32_t(0)},
20665 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
20666 // (LDNF1SW_D_IMM_REAL Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1866
20667 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
20668 {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID},
20669 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
20670 {AliasPatternCond::K_Imm, uint32_t(0)},
20671 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
20672 // (LDNF1W_D_IMM_REAL Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1871
20673 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
20674 {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID},
20675 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
20676 {AliasPatternCond::K_Imm, uint32_t(0)},
20677 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
20678 // (LDNF1W_IMM_REAL Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1876
20679 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
20680 {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID},
20681 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
20682 {AliasPatternCond::K_Imm, uint32_t(0)},
20683 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
20684 // (LDNPDi FPR64Op:$Rt, FPR64Op:$Rt2, GPR64sp:$Rn, 0) - 1881
20685 {AliasPatternCond::K_RegClass, AArch64::FPR64RegClassID},
20686 {AliasPatternCond::K_RegClass, AArch64::FPR64RegClassID},
20687 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
20688 {AliasPatternCond::K_Imm, uint32_t(0)},
20689 // (LDNPQi FPR128Op:$Rt, FPR128Op:$Rt2, GPR64sp:$Rn, 0) - 1885
20690 {AliasPatternCond::K_RegClass, AArch64::FPR128RegClassID},
20691 {AliasPatternCond::K_RegClass, AArch64::FPR128RegClassID},
20692 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
20693 {AliasPatternCond::K_Imm, uint32_t(0)},
20694 // (LDNPSi FPR32Op:$Rt, FPR32Op:$Rt2, GPR64sp:$Rn, 0) - 1889
20695 {AliasPatternCond::K_RegClass, AArch64::FPR32RegClassID},
20696 {AliasPatternCond::K_RegClass, AArch64::FPR32RegClassID},
20697 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
20698 {AliasPatternCond::K_Imm, uint32_t(0)},
20699 // (LDNPWi GPR32z:$Rt, GPR32z:$Rt2, GPR64sp:$Rn, 0) - 1893
20700 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
20701 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
20702 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
20703 {AliasPatternCond::K_Imm, uint32_t(0)},
20704 // (LDNPXi GPR64z:$Rt, GPR64z:$Rt2, GPR64sp:$Rn, 0) - 1897
20705 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
20706 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
20707 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
20708 {AliasPatternCond::K_Imm, uint32_t(0)},
20709 // (LDNT1B_ZRI Z_b:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1901
20710 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
20711 {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID},
20712 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
20713 {AliasPatternCond::K_Imm, uint32_t(0)},
20714 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
20715 // (LDNT1B_ZZR_D_REAL Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, XZR) - 1906
20716 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
20717 {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID},
20718 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
20719 {AliasPatternCond::K_Reg, AArch64::XZR},
20720 {AliasPatternCond::K_Feature, AArch64::FeatureSVE2},
20721 // (LDNT1B_ZZR_S_REAL Z_s:$Zt, PPR3bAny:$Pg, ZPR32:$Zn, XZR) - 1911
20722 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
20723 {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID},
20724 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
20725 {AliasPatternCond::K_Reg, AArch64::XZR},
20726 {AliasPatternCond::K_Feature, AArch64::FeatureSVE2},
20727 // (LDNT1D_ZRI Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1916
20728 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
20729 {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID},
20730 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
20731 {AliasPatternCond::K_Imm, uint32_t(0)},
20732 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
20733 // (LDNT1D_ZZR_D_REAL Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, XZR) - 1921
20734 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
20735 {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID},
20736 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
20737 {AliasPatternCond::K_Reg, AArch64::XZR},
20738 {AliasPatternCond::K_Feature, AArch64::FeatureSVE2},
20739 // (LDNT1H_ZRI Z_h:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1926
20740 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
20741 {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID},
20742 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
20743 {AliasPatternCond::K_Imm, uint32_t(0)},
20744 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
20745 // (LDNT1H_ZZR_D_REAL Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, XZR) - 1931
20746 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
20747 {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID},
20748 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
20749 {AliasPatternCond::K_Reg, AArch64::XZR},
20750 {AliasPatternCond::K_Feature, AArch64::FeatureSVE2},
20751 // (LDNT1H_ZZR_S_REAL Z_s:$Zt, PPR3bAny:$Pg, ZPR32:$Zn, XZR) - 1936
20752 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
20753 {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID},
20754 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
20755 {AliasPatternCond::K_Reg, AArch64::XZR},
20756 {AliasPatternCond::K_Feature, AArch64::FeatureSVE2},
20757 // (LDNT1SB_ZZR_D_REAL Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, XZR) - 1941
20758 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
20759 {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID},
20760 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
20761 {AliasPatternCond::K_Reg, AArch64::XZR},
20762 {AliasPatternCond::K_Feature, AArch64::FeatureSVE2},
20763 // (LDNT1SB_ZZR_S_REAL Z_s:$Zt, PPR3bAny:$Pg, ZPR32:$Zn, XZR) - 1946
20764 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
20765 {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID},
20766 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
20767 {AliasPatternCond::K_Reg, AArch64::XZR},
20768 {AliasPatternCond::K_Feature, AArch64::FeatureSVE2},
20769 // (LDNT1SH_ZZR_D_REAL Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, XZR) - 1951
20770 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
20771 {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID},
20772 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
20773 {AliasPatternCond::K_Reg, AArch64::XZR},
20774 {AliasPatternCond::K_Feature, AArch64::FeatureSVE2},
20775 // (LDNT1SH_ZZR_S_REAL Z_s:$Zt, PPR3bAny:$Pg, ZPR32:$Zn, XZR) - 1956
20776 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
20777 {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID},
20778 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
20779 {AliasPatternCond::K_Reg, AArch64::XZR},
20780 {AliasPatternCond::K_Feature, AArch64::FeatureSVE2},
20781 // (LDNT1SW_ZZR_D_REAL Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, XZR) - 1961
20782 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
20783 {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID},
20784 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
20785 {AliasPatternCond::K_Reg, AArch64::XZR},
20786 {AliasPatternCond::K_Feature, AArch64::FeatureSVE2},
20787 // (LDNT1W_ZRI Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1966
20788 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
20789 {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID},
20790 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
20791 {AliasPatternCond::K_Imm, uint32_t(0)},
20792 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
20793 // (LDNT1W_ZZR_D_REAL Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, XZR) - 1971
20794 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
20795 {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID},
20796 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
20797 {AliasPatternCond::K_Reg, AArch64::XZR},
20798 {AliasPatternCond::K_Feature, AArch64::FeatureSVE2},
20799 // (LDNT1W_ZZR_S_REAL Z_s:$Zt, PPR3bAny:$Pg, ZPR32:$Zn, XZR) - 1976
20800 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
20801 {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID},
20802 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
20803 {AliasPatternCond::K_Reg, AArch64::XZR},
20804 {AliasPatternCond::K_Feature, AArch64::FeatureSVE2},
20805 // (LDPDi FPR64Op:$Rt, FPR64Op:$Rt2, GPR64sp:$Rn, 0) - 1981
20806 {AliasPatternCond::K_RegClass, AArch64::FPR64RegClassID},
20807 {AliasPatternCond::K_RegClass, AArch64::FPR64RegClassID},
20808 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
20809 {AliasPatternCond::K_Imm, uint32_t(0)},
20810 // (LDPQi FPR128Op:$Rt, FPR128Op:$Rt2, GPR64sp:$Rn, 0) - 1985
20811 {AliasPatternCond::K_RegClass, AArch64::FPR128RegClassID},
20812 {AliasPatternCond::K_RegClass, AArch64::FPR128RegClassID},
20813 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
20814 {AliasPatternCond::K_Imm, uint32_t(0)},
20815 // (LDPSWi GPR64z:$Rt, GPR64z:$Rt2, GPR64sp:$Rn, 0) - 1989
20816 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
20817 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
20818 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
20819 {AliasPatternCond::K_Imm, uint32_t(0)},
20820 // (LDPSi FPR32Op:$Rt, FPR32Op:$Rt2, GPR64sp:$Rn, 0) - 1993
20821 {AliasPatternCond::K_RegClass, AArch64::FPR32RegClassID},
20822 {AliasPatternCond::K_RegClass, AArch64::FPR32RegClassID},
20823 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
20824 {AliasPatternCond::K_Imm, uint32_t(0)},
20825 // (LDPWi GPR32z:$Rt, GPR32z:$Rt2, GPR64sp:$Rn, 0) - 1997
20826 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
20827 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
20828 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
20829 {AliasPatternCond::K_Imm, uint32_t(0)},
20830 // (LDPXi GPR64z:$Rt, GPR64z:$Rt2, GPR64sp:$Rn, 0) - 2001
20831 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
20832 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
20833 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
20834 {AliasPatternCond::K_Imm, uint32_t(0)},
20835 // (LDRAAindexed GPR64:$Rt, GPR64sp:$Rn, 0) - 2005
20836 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
20837 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
20838 {AliasPatternCond::K_Imm, uint32_t(0)},
20839 {AliasPatternCond::K_Feature, AArch64::FeaturePAuth},
20840 // (LDRABindexed GPR64:$Rt, GPR64sp:$Rn, 0) - 2009
20841 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
20842 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
20843 {AliasPatternCond::K_Imm, uint32_t(0)},
20844 {AliasPatternCond::K_Feature, AArch64::FeaturePAuth},
20845 // (LDRBBroX GPR32:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) - 2013
20846 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
20847 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
20848 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
20849 {AliasPatternCond::K_Imm, uint32_t(0)},
20850 {AliasPatternCond::K_Imm, uint32_t(0)},
20851 // (LDRBBui GPR32:$Rt, GPR64sp:$Rn, 0) - 2018
20852 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
20853 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
20854 {AliasPatternCond::K_Imm, uint32_t(0)},
20855 // (LDRBroX FPR8Op:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) - 2021
20856 {AliasPatternCond::K_RegClass, AArch64::FPR8RegClassID},
20857 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
20858 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
20859 {AliasPatternCond::K_Imm, uint32_t(0)},
20860 {AliasPatternCond::K_Imm, uint32_t(0)},
20861 // (LDRBui FPR8Op:$Rt, GPR64sp:$Rn, 0) - 2026
20862 {AliasPatternCond::K_RegClass, AArch64::FPR8RegClassID},
20863 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
20864 {AliasPatternCond::K_Imm, uint32_t(0)},
20865 // (LDRDroX FPR64Op:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) - 2029
20866 {AliasPatternCond::K_RegClass, AArch64::FPR64RegClassID},
20867 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
20868 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
20869 {AliasPatternCond::K_Imm, uint32_t(0)},
20870 {AliasPatternCond::K_Imm, uint32_t(0)},
20871 // (LDRDui FPR64Op:$Rt, GPR64sp:$Rn, 0) - 2034
20872 {AliasPatternCond::K_RegClass, AArch64::FPR64RegClassID},
20873 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
20874 {AliasPatternCond::K_Imm, uint32_t(0)},
20875 // (LDRHHroX GPR32:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) - 2037
20876 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
20877 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
20878 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
20879 {AliasPatternCond::K_Imm, uint32_t(0)},
20880 {AliasPatternCond::K_Imm, uint32_t(0)},
20881 // (LDRHHui GPR32:$Rt, GPR64sp:$Rn, 0) - 2042
20882 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
20883 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
20884 {AliasPatternCond::K_Imm, uint32_t(0)},
20885 // (LDRHroX FPR16Op:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) - 2045
20886 {AliasPatternCond::K_RegClass, AArch64::FPR16RegClassID},
20887 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
20888 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
20889 {AliasPatternCond::K_Imm, uint32_t(0)},
20890 {AliasPatternCond::K_Imm, uint32_t(0)},
20891 // (LDRHui FPR16Op:$Rt, GPR64sp:$Rn, 0) - 2050
20892 {AliasPatternCond::K_RegClass, AArch64::FPR16RegClassID},
20893 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
20894 {AliasPatternCond::K_Imm, uint32_t(0)},
20895 // (LDRQroX FPR128Op:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) - 2053
20896 {AliasPatternCond::K_RegClass, AArch64::FPR128RegClassID},
20897 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
20898 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
20899 {AliasPatternCond::K_Imm, uint32_t(0)},
20900 {AliasPatternCond::K_Imm, uint32_t(0)},
20901 // (LDRQui FPR128Op:$Rt, GPR64sp:$Rn, 0) - 2058
20902 {AliasPatternCond::K_RegClass, AArch64::FPR128RegClassID},
20903 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
20904 {AliasPatternCond::K_Imm, uint32_t(0)},
20905 // (LDRSBWroX GPR32:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) - 2061
20906 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
20907 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
20908 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
20909 {AliasPatternCond::K_Imm, uint32_t(0)},
20910 {AliasPatternCond::K_Imm, uint32_t(0)},
20911 // (LDRSBWui GPR32:$Rt, GPR64sp:$Rn, 0) - 2066
20912 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
20913 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
20914 {AliasPatternCond::K_Imm, uint32_t(0)},
20915 // (LDRSBXroX GPR64:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) - 2069
20916 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
20917 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
20918 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
20919 {AliasPatternCond::K_Imm, uint32_t(0)},
20920 {AliasPatternCond::K_Imm, uint32_t(0)},
20921 // (LDRSBXui GPR64:$Rt, GPR64sp:$Rn, 0) - 2074
20922 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
20923 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
20924 {AliasPatternCond::K_Imm, uint32_t(0)},
20925 // (LDRSHWroX GPR32:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) - 2077
20926 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
20927 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
20928 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
20929 {AliasPatternCond::K_Imm, uint32_t(0)},
20930 {AliasPatternCond::K_Imm, uint32_t(0)},
20931 // (LDRSHWui GPR32:$Rt, GPR64sp:$Rn, 0) - 2082
20932 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
20933 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
20934 {AliasPatternCond::K_Imm, uint32_t(0)},
20935 // (LDRSHXroX GPR64:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) - 2085
20936 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
20937 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
20938 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
20939 {AliasPatternCond::K_Imm, uint32_t(0)},
20940 {AliasPatternCond::K_Imm, uint32_t(0)},
20941 // (LDRSHXui GPR64:$Rt, GPR64sp:$Rn, 0) - 2090
20942 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
20943 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
20944 {AliasPatternCond::K_Imm, uint32_t(0)},
20945 // (LDRSWroX GPR64:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) - 2093
20946 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
20947 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
20948 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
20949 {AliasPatternCond::K_Imm, uint32_t(0)},
20950 {AliasPatternCond::K_Imm, uint32_t(0)},
20951 // (LDRSWui GPR64:$Rt, GPR64sp:$Rn, 0) - 2098
20952 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
20953 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
20954 {AliasPatternCond::K_Imm, uint32_t(0)},
20955 // (LDRSroX FPR32Op:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) - 2101
20956 {AliasPatternCond::K_RegClass, AArch64::FPR32RegClassID},
20957 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
20958 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
20959 {AliasPatternCond::K_Imm, uint32_t(0)},
20960 {AliasPatternCond::K_Imm, uint32_t(0)},
20961 // (LDRSui FPR32Op:$Rt, GPR64sp:$Rn, 0) - 2106
20962 {AliasPatternCond::K_RegClass, AArch64::FPR32RegClassID},
20963 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
20964 {AliasPatternCond::K_Imm, uint32_t(0)},
20965 // (LDRWroX GPR32:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) - 2109
20966 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
20967 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
20968 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
20969 {AliasPatternCond::K_Imm, uint32_t(0)},
20970 {AliasPatternCond::K_Imm, uint32_t(0)},
20971 // (LDRWui GPR32z:$Rt, GPR64sp:$Rn, 0) - 2114
20972 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
20973 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
20974 {AliasPatternCond::K_Imm, uint32_t(0)},
20975 // (LDRXroX GPR64:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) - 2117
20976 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
20977 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
20978 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
20979 {AliasPatternCond::K_Imm, uint32_t(0)},
20980 {AliasPatternCond::K_Imm, uint32_t(0)},
20981 // (LDRXui GPR64z:$Rt, GPR64sp:$Rn, 0) - 2122
20982 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
20983 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
20984 {AliasPatternCond::K_Imm, uint32_t(0)},
20985 // (LDR_PXI PPRAny:$Pt, GPR64sp:$Rn, 0) - 2125
20986 {AliasPatternCond::K_RegClass, AArch64::PPRRegClassID},
20987 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
20988 {AliasPatternCond::K_Imm, uint32_t(0)},
20989 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
20990 // (LDR_ZXI ZPRAny:$Zt, GPR64sp:$Rn, 0) - 2129
20991 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
20992 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
20993 {AliasPatternCond::K_Imm, uint32_t(0)},
20994 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
20995 // (LDSETB WZR, GPR32:$Rs, GPR64sp:$Rn) - 2133
20996 {AliasPatternCond::K_Reg, AArch64::WZR},
20997 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
20998 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
20999 {AliasPatternCond::K_Feature, AArch64::FeatureLSE},
21000 // (LDSETH WZR, GPR32:$Rs, GPR64sp:$Rn) - 2137
21001 {AliasPatternCond::K_Reg, AArch64::WZR},
21002 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
21003 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
21004 {AliasPatternCond::K_Feature, AArch64::FeatureLSE},
21005 // (LDSETLB WZR, GPR32:$Rs, GPR64sp:$Rn) - 2141
21006 {AliasPatternCond::K_Reg, AArch64::WZR},
21007 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
21008 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
21009 {AliasPatternCond::K_Feature, AArch64::FeatureLSE},
21010 // (LDSETLH WZR, GPR32:$Rs, GPR64sp:$Rn) - 2145
21011 {AliasPatternCond::K_Reg, AArch64::WZR},
21012 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
21013 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
21014 {AliasPatternCond::K_Feature, AArch64::FeatureLSE},
21015 // (LDSETLW WZR, GPR32:$Rs, GPR64sp:$Rn) - 2149
21016 {AliasPatternCond::K_Reg, AArch64::WZR},
21017 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
21018 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
21019 {AliasPatternCond::K_Feature, AArch64::FeatureLSE},
21020 // (LDSETLX XZR, GPR64:$Rs, GPR64sp:$Rn) - 2153
21021 {AliasPatternCond::K_Reg, AArch64::XZR},
21022 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
21023 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
21024 {AliasPatternCond::K_Feature, AArch64::FeatureLSE},
21025 // (LDSETW WZR, GPR32:$Rs, GPR64sp:$Rn) - 2157
21026 {AliasPatternCond::K_Reg, AArch64::WZR},
21027 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
21028 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
21029 {AliasPatternCond::K_Feature, AArch64::FeatureLSE},
21030 // (LDSETX XZR, GPR64:$Rs, GPR64sp:$Rn) - 2161
21031 {AliasPatternCond::K_Reg, AArch64::XZR},
21032 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
21033 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
21034 {AliasPatternCond::K_Feature, AArch64::FeatureLSE},
21035 // (LDSMAXB WZR, GPR32:$Rs, GPR64sp:$Rn) - 2165
21036 {AliasPatternCond::K_Reg, AArch64::WZR},
21037 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
21038 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
21039 {AliasPatternCond::K_Feature, AArch64::FeatureLSE},
21040 // (LDSMAXH WZR, GPR32:$Rs, GPR64sp:$Rn) - 2169
21041 {AliasPatternCond::K_Reg, AArch64::WZR},
21042 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
21043 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
21044 {AliasPatternCond::K_Feature, AArch64::FeatureLSE},
21045 // (LDSMAXLB WZR, GPR32:$Rs, GPR64sp:$Rn) - 2173
21046 {AliasPatternCond::K_Reg, AArch64::WZR},
21047 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
21048 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
21049 {AliasPatternCond::K_Feature, AArch64::FeatureLSE},
21050 // (LDSMAXLH WZR, GPR32:$Rs, GPR64sp:$Rn) - 2177
21051 {AliasPatternCond::K_Reg, AArch64::WZR},
21052 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
21053 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
21054 {AliasPatternCond::K_Feature, AArch64::FeatureLSE},
21055 // (LDSMAXLW WZR, GPR32:$Rs, GPR64sp:$Rn) - 2181
21056 {AliasPatternCond::K_Reg, AArch64::WZR},
21057 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
21058 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
21059 {AliasPatternCond::K_Feature, AArch64::FeatureLSE},
21060 // (LDSMAXLX XZR, GPR64:$Rs, GPR64sp:$Rn) - 2185
21061 {AliasPatternCond::K_Reg, AArch64::XZR},
21062 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
21063 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
21064 {AliasPatternCond::K_Feature, AArch64::FeatureLSE},
21065 // (LDSMAXW WZR, GPR32:$Rs, GPR64sp:$Rn) - 2189
21066 {AliasPatternCond::K_Reg, AArch64::WZR},
21067 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
21068 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
21069 {AliasPatternCond::K_Feature, AArch64::FeatureLSE},
21070 // (LDSMAXX XZR, GPR64:$Rs, GPR64sp:$Rn) - 2193
21071 {AliasPatternCond::K_Reg, AArch64::XZR},
21072 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
21073 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
21074 {AliasPatternCond::K_Feature, AArch64::FeatureLSE},
21075 // (LDSMINB WZR, GPR32:$Rs, GPR64sp:$Rn) - 2197
21076 {AliasPatternCond::K_Reg, AArch64::WZR},
21077 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
21078 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
21079 {AliasPatternCond::K_Feature, AArch64::FeatureLSE},
21080 // (LDSMINH WZR, GPR32:$Rs, GPR64sp:$Rn) - 2201
21081 {AliasPatternCond::K_Reg, AArch64::WZR},
21082 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
21083 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
21084 {AliasPatternCond::K_Feature, AArch64::FeatureLSE},
21085 // (LDSMINLB WZR, GPR32:$Rs, GPR64sp:$Rn) - 2205
21086 {AliasPatternCond::K_Reg, AArch64::WZR},
21087 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
21088 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
21089 {AliasPatternCond::K_Feature, AArch64::FeatureLSE},
21090 // (LDSMINLH WZR, GPR32:$Rs, GPR64sp:$Rn) - 2209
21091 {AliasPatternCond::K_Reg, AArch64::WZR},
21092 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
21093 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
21094 {AliasPatternCond::K_Feature, AArch64::FeatureLSE},
21095 // (LDSMINLW WZR, GPR32:$Rs, GPR64sp:$Rn) - 2213
21096 {AliasPatternCond::K_Reg, AArch64::WZR},
21097 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
21098 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
21099 {AliasPatternCond::K_Feature, AArch64::FeatureLSE},
21100 // (LDSMINLX XZR, GPR64:$Rs, GPR64sp:$Rn) - 2217
21101 {AliasPatternCond::K_Reg, AArch64::XZR},
21102 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
21103 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
21104 {AliasPatternCond::K_Feature, AArch64::FeatureLSE},
21105 // (LDSMINW WZR, GPR32:$Rs, GPR64sp:$Rn) - 2221
21106 {AliasPatternCond::K_Reg, AArch64::WZR},
21107 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
21108 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
21109 {AliasPatternCond::K_Feature, AArch64::FeatureLSE},
21110 // (LDSMINX XZR, GPR64:$Rs, GPR64sp:$Rn) - 2225
21111 {AliasPatternCond::K_Reg, AArch64::XZR},
21112 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
21113 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
21114 {AliasPatternCond::K_Feature, AArch64::FeatureLSE},
21115 // (LDTRBi GPR32:$Rt, GPR64sp:$Rn, 0) - 2229
21116 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
21117 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
21118 {AliasPatternCond::K_Imm, uint32_t(0)},
21119 // (LDTRHi GPR32:$Rt, GPR64sp:$Rn, 0) - 2232
21120 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
21121 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
21122 {AliasPatternCond::K_Imm, uint32_t(0)},
21123 // (LDTRSBWi GPR32:$Rt, GPR64sp:$Rn, 0) - 2235
21124 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
21125 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
21126 {AliasPatternCond::K_Imm, uint32_t(0)},
21127 // (LDTRSBXi GPR64:$Rt, GPR64sp:$Rn, 0) - 2238
21128 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
21129 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
21130 {AliasPatternCond::K_Imm, uint32_t(0)},
21131 // (LDTRSHWi GPR32:$Rt, GPR64sp:$Rn, 0) - 2241
21132 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
21133 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
21134 {AliasPatternCond::K_Imm, uint32_t(0)},
21135 // (LDTRSHXi GPR64:$Rt, GPR64sp:$Rn, 0) - 2244
21136 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
21137 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
21138 {AliasPatternCond::K_Imm, uint32_t(0)},
21139 // (LDTRSWi GPR64:$Rt, GPR64sp:$Rn, 0) - 2247
21140 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
21141 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
21142 {AliasPatternCond::K_Imm, uint32_t(0)},
21143 // (LDTRWi GPR32:$Rt, GPR64sp:$Rn, 0) - 2250
21144 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
21145 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
21146 {AliasPatternCond::K_Imm, uint32_t(0)},
21147 // (LDTRXi GPR64:$Rt, GPR64sp:$Rn, 0) - 2253
21148 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
21149 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
21150 {AliasPatternCond::K_Imm, uint32_t(0)},
21151 // (LDUMAXB WZR, GPR32:$Rs, GPR64sp:$Rn) - 2256
21152 {AliasPatternCond::K_Reg, AArch64::WZR},
21153 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
21154 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
21155 {AliasPatternCond::K_Feature, AArch64::FeatureLSE},
21156 // (LDUMAXH WZR, GPR32:$Rs, GPR64sp:$Rn) - 2260
21157 {AliasPatternCond::K_Reg, AArch64::WZR},
21158 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
21159 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
21160 {AliasPatternCond::K_Feature, AArch64::FeatureLSE},
21161 // (LDUMAXLB WZR, GPR32:$Rs, GPR64sp:$Rn) - 2264
21162 {AliasPatternCond::K_Reg, AArch64::WZR},
21163 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
21164 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
21165 {AliasPatternCond::K_Feature, AArch64::FeatureLSE},
21166 // (LDUMAXLH WZR, GPR32:$Rs, GPR64sp:$Rn) - 2268
21167 {AliasPatternCond::K_Reg, AArch64::WZR},
21168 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
21169 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
21170 {AliasPatternCond::K_Feature, AArch64::FeatureLSE},
21171 // (LDUMAXLW WZR, GPR32:$Rs, GPR64sp:$Rn) - 2272
21172 {AliasPatternCond::K_Reg, AArch64::WZR},
21173 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
21174 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
21175 {AliasPatternCond::K_Feature, AArch64::FeatureLSE},
21176 // (LDUMAXLX XZR, GPR64:$Rs, GPR64sp:$Rn) - 2276
21177 {AliasPatternCond::K_Reg, AArch64::XZR},
21178 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
21179 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
21180 {AliasPatternCond::K_Feature, AArch64::FeatureLSE},
21181 // (LDUMAXW WZR, GPR32:$Rs, GPR64sp:$Rn) - 2280
21182 {AliasPatternCond::K_Reg, AArch64::WZR},
21183 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
21184 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
21185 {AliasPatternCond::K_Feature, AArch64::FeatureLSE},
21186 // (LDUMAXX XZR, GPR64:$Rs, GPR64sp:$Rn) - 2284
21187 {AliasPatternCond::K_Reg, AArch64::XZR},
21188 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
21189 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
21190 {AliasPatternCond::K_Feature, AArch64::FeatureLSE},
21191 // (LDUMINB WZR, GPR32:$Rs, GPR64sp:$Rn) - 2288
21192 {AliasPatternCond::K_Reg, AArch64::WZR},
21193 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
21194 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
21195 {AliasPatternCond::K_Feature, AArch64::FeatureLSE},
21196 // (LDUMINH WZR, GPR32:$Rs, GPR64sp:$Rn) - 2292
21197 {AliasPatternCond::K_Reg, AArch64::WZR},
21198 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
21199 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
21200 {AliasPatternCond::K_Feature, AArch64::FeatureLSE},
21201 // (LDUMINLB WZR, GPR32:$Rs, GPR64sp:$Rn) - 2296
21202 {AliasPatternCond::K_Reg, AArch64::WZR},
21203 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
21204 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
21205 {AliasPatternCond::K_Feature, AArch64::FeatureLSE},
21206 // (LDUMINLH WZR, GPR32:$Rs, GPR64sp:$Rn) - 2300
21207 {AliasPatternCond::K_Reg, AArch64::WZR},
21208 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
21209 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
21210 {AliasPatternCond::K_Feature, AArch64::FeatureLSE},
21211 // (LDUMINLW WZR, GPR32:$Rs, GPR64sp:$Rn) - 2304
21212 {AliasPatternCond::K_Reg, AArch64::WZR},
21213 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
21214 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
21215 {AliasPatternCond::K_Feature, AArch64::FeatureLSE},
21216 // (LDUMINLX XZR, GPR64:$Rs, GPR64sp:$Rn) - 2308
21217 {AliasPatternCond::K_Reg, AArch64::XZR},
21218 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
21219 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
21220 {AliasPatternCond::K_Feature, AArch64::FeatureLSE},
21221 // (LDUMINW WZR, GPR32:$Rs, GPR64sp:$Rn) - 2312
21222 {AliasPatternCond::K_Reg, AArch64::WZR},
21223 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
21224 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
21225 {AliasPatternCond::K_Feature, AArch64::FeatureLSE},
21226 // (LDUMINX XZR, GPR64:$Rs, GPR64sp:$Rn) - 2316
21227 {AliasPatternCond::K_Reg, AArch64::XZR},
21228 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
21229 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
21230 {AliasPatternCond::K_Feature, AArch64::FeatureLSE},
21231 // (LDURBBi GPR32:$Rt, GPR64sp:$Rn, 0) - 2320
21232 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
21233 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
21234 {AliasPatternCond::K_Imm, uint32_t(0)},
21235 // (LDURBi FPR8Op:$Rt, GPR64sp:$Rn, 0) - 2323
21236 {AliasPatternCond::K_RegClass, AArch64::FPR8RegClassID},
21237 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
21238 {AliasPatternCond::K_Imm, uint32_t(0)},
21239 // (LDURDi FPR64Op:$Rt, GPR64sp:$Rn, 0) - 2326
21240 {AliasPatternCond::K_RegClass, AArch64::FPR64RegClassID},
21241 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
21242 {AliasPatternCond::K_Imm, uint32_t(0)},
21243 // (LDURHHi GPR32:$Rt, GPR64sp:$Rn, 0) - 2329
21244 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
21245 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
21246 {AliasPatternCond::K_Imm, uint32_t(0)},
21247 // (LDURHi FPR16Op:$Rt, GPR64sp:$Rn, 0) - 2332
21248 {AliasPatternCond::K_RegClass, AArch64::FPR16RegClassID},
21249 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
21250 {AliasPatternCond::K_Imm, uint32_t(0)},
21251 // (LDURQi FPR128Op:$Rt, GPR64sp:$Rn, 0) - 2335
21252 {AliasPatternCond::K_RegClass, AArch64::FPR128RegClassID},
21253 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
21254 {AliasPatternCond::K_Imm, uint32_t(0)},
21255 // (LDURSBWi GPR32:$Rt, GPR64sp:$Rn, 0) - 2338
21256 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
21257 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
21258 {AliasPatternCond::K_Imm, uint32_t(0)},
21259 // (LDURSBXi GPR64:$Rt, GPR64sp:$Rn, 0) - 2341
21260 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
21261 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
21262 {AliasPatternCond::K_Imm, uint32_t(0)},
21263 // (LDURSHWi GPR32:$Rt, GPR64sp:$Rn, 0) - 2344
21264 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
21265 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
21266 {AliasPatternCond::K_Imm, uint32_t(0)},
21267 // (LDURSHXi GPR64:$Rt, GPR64sp:$Rn, 0) - 2347
21268 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
21269 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
21270 {AliasPatternCond::K_Imm, uint32_t(0)},
21271 // (LDURSWi GPR64:$Rt, GPR64sp:$Rn, 0) - 2350
21272 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
21273 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
21274 {AliasPatternCond::K_Imm, uint32_t(0)},
21275 // (LDURSi FPR32Op:$Rt, GPR64sp:$Rn, 0) - 2353
21276 {AliasPatternCond::K_RegClass, AArch64::FPR32RegClassID},
21277 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
21278 {AliasPatternCond::K_Imm, uint32_t(0)},
21279 // (LDURWi GPR32z:$Rt, GPR64sp:$Rn, 0) - 2356
21280 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
21281 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
21282 {AliasPatternCond::K_Imm, uint32_t(0)},
21283 // (LDURXi GPR64z:$Rt, GPR64sp:$Rn, 0) - 2359
21284 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
21285 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
21286 {AliasPatternCond::K_Imm, uint32_t(0)},
21287 // (MADDWrrr GPR32:$dst, GPR32:$src1, GPR32:$src2, WZR) - 2362
21288 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
21289 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
21290 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
21291 {AliasPatternCond::K_Reg, AArch64::WZR},
21292 // (MADDXrrr GPR64:$dst, GPR64:$src1, GPR64:$src2, XZR) - 2366
21293 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
21294 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
21295 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
21296 {AliasPatternCond::K_Reg, AArch64::XZR},
21297 // (MSUBWrrr GPR32:$dst, GPR32:$src1, GPR32:$src2, WZR) - 2370
21298 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
21299 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
21300 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
21301 {AliasPatternCond::K_Reg, AArch64::WZR},
21302 // (MSUBXrrr GPR64:$dst, GPR64:$src1, GPR64:$src2, XZR) - 2374
21303 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
21304 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
21305 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
21306 {AliasPatternCond::K_Reg, AArch64::XZR},
21307 // (NOTv16i8 V128:$Vd, V128:$Vn) - 2378
21308 {AliasPatternCond::K_RegClass, AArch64::FPR128RegClassID},
21309 {AliasPatternCond::K_RegClass, AArch64::FPR128RegClassID},
21310 // (NOTv8i8 V64:$Vd, V64:$Vn) - 2380
21311 {AliasPatternCond::K_RegClass, AArch64::FPR64RegClassID},
21312 {AliasPatternCond::K_RegClass, AArch64::FPR64RegClassID},
21313 // (ORNWrs GPR32:$Wd, WZR, GPR32:$Wm, 0) - 2382
21314 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
21315 {AliasPatternCond::K_Reg, AArch64::WZR},
21316 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
21317 {AliasPatternCond::K_Imm, uint32_t(0)},
21318 // (ORNWrs GPR32:$Wd, WZR, GPR32:$Wm, logical_shift32:$sh) - 2386
21319 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
21320 {AliasPatternCond::K_Reg, AArch64::WZR},
21321 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
21322 // (ORNWrs GPR32:$dst, GPR32:$src1, GPR32:$src2, 0) - 2389
21323 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
21324 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
21325 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
21326 {AliasPatternCond::K_Imm, uint32_t(0)},
21327 // (ORNXrs GPR64:$Xd, XZR, GPR64:$Xm, 0) - 2393
21328 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
21329 {AliasPatternCond::K_Reg, AArch64::XZR},
21330 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
21331 {AliasPatternCond::K_Imm, uint32_t(0)},
21332 // (ORNXrs GPR64:$Xd, XZR, GPR64:$Xm, logical_shift64:$sh) - 2397
21333 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
21334 {AliasPatternCond::K_Reg, AArch64::XZR},
21335 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
21336 // (ORNXrs GPR64:$dst, GPR64:$src1, GPR64:$src2, 0) - 2400
21337 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
21338 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
21339 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
21340 {AliasPatternCond::K_Imm, uint32_t(0)},
21341 // (ORRS_PPzPP PPR8:$Pd, PPR8:$Pn, PPR8:$Pn, PPR8:$Pn) - 2404
21342 {AliasPatternCond::K_RegClass, AArch64::PPRRegClassID},
21343 {AliasPatternCond::K_RegClass, AArch64::PPRRegClassID},
21344 {AliasPatternCond::K_TiedReg, 1},
21345 {AliasPatternCond::K_TiedReg, 1},
21346 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
21347 // (ORRWrs GPR32:$dst, WZR, GPR32:$src, 0) - 2409
21348 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
21349 {AliasPatternCond::K_Reg, AArch64::WZR},
21350 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
21351 {AliasPatternCond::K_Imm, uint32_t(0)},
21352 // (ORRWrs GPR32:$dst, GPR32:$src1, GPR32:$src2, 0) - 2413
21353 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
21354 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
21355 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
21356 {AliasPatternCond::K_Imm, uint32_t(0)},
21357 // (ORRXrs GPR64:$dst, XZR, GPR64:$src, 0) - 2417
21358 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
21359 {AliasPatternCond::K_Reg, AArch64::XZR},
21360 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
21361 {AliasPatternCond::K_Imm, uint32_t(0)},
21362 // (ORRXrs GPR64:$dst, GPR64:$src1, GPR64:$src2, 0) - 2421
21363 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
21364 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
21365 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
21366 {AliasPatternCond::K_Imm, uint32_t(0)},
21367 // (ORR_PPzPP PPR8:$Pd, PPR8:$Pn, PPR8:$Pn, PPR8:$Pn) - 2425
21368 {AliasPatternCond::K_RegClass, AArch64::PPRRegClassID},
21369 {AliasPatternCond::K_RegClass, AArch64::PPRRegClassID},
21370 {AliasPatternCond::K_TiedReg, 1},
21371 {AliasPatternCond::K_TiedReg, 1},
21372 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
21373 // (ORR_ZI ZPR8:$Zdn, sve_logical_imm8:$imm) - 2430
21374 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
21375 {AliasPatternCond::K_Ignore, 0},
21376 {AliasPatternCond::K_Custom, 1},
21377 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
21378 // (ORR_ZI ZPR16:$Zdn, sve_logical_imm16:$imm) - 2434
21379 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
21380 {AliasPatternCond::K_Ignore, 0},
21381 {AliasPatternCond::K_Custom, 2},
21382 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
21383 // (ORR_ZI ZPR32:$Zdn, sve_logical_imm32:$imm) - 2438
21384 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
21385 {AliasPatternCond::K_Ignore, 0},
21386 {AliasPatternCond::K_Custom, 3},
21387 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
21388 // (ORR_ZZZ ZPR64:$Zd, ZPR64:$Zn, ZPR64:$Zn) - 2442
21389 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
21390 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
21391 {AliasPatternCond::K_TiedReg, 1},
21392 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
21393 // (ORRv16i8 V128:$dst, V128:$src, V128:$src) - 2446
21394 {AliasPatternCond::K_RegClass, AArch64::FPR128RegClassID},
21395 {AliasPatternCond::K_RegClass, AArch64::FPR128RegClassID},
21396 {AliasPatternCond::K_TiedReg, 1},
21397 // (ORRv8i8 V64:$dst, V64:$src, V64:$src) - 2449
21398 {AliasPatternCond::K_RegClass, AArch64::FPR64RegClassID},
21399 {AliasPatternCond::K_RegClass, AArch64::FPR64RegClassID},
21400 {AliasPatternCond::K_TiedReg, 1},
21401 // (PACIA1716) - 2452
21402 {AliasPatternCond::K_Feature, AArch64::FeaturePAuth},
21403 // (PACIASP) - 2453
21404 {AliasPatternCond::K_Feature, AArch64::FeaturePAuth},
21405 // (PACIAZ) - 2454
21406 {AliasPatternCond::K_Feature, AArch64::FeaturePAuth},
21407 // (PACIB1716) - 2455
21408 {AliasPatternCond::K_Feature, AArch64::FeaturePAuth},
21409 // (PACIBSP) - 2456
21410 {AliasPatternCond::K_Feature, AArch64::FeaturePAuth},
21411 // (PACIBZ) - 2457
21412 {AliasPatternCond::K_Feature, AArch64::FeaturePAuth},
21413 // (PRFB_D_PZI sve_prfop:$prfop, PPR3bAny:$Pg, ZPR64:$Zn, 0) - 2458
21414 {AliasPatternCond::K_Ignore, 0},
21415 {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID},
21416 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
21417 {AliasPatternCond::K_Imm, uint32_t(0)},
21418 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
21419 // (PRFB_PRI sve_prfop:$prfop, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 2463
21420 {AliasPatternCond::K_Ignore, 0},
21421 {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID},
21422 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
21423 {AliasPatternCond::K_Imm, uint32_t(0)},
21424 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
21425 // (PRFB_S_PZI sve_prfop:$prfop, PPR3bAny:$Pg, ZPR32:$Zn, 0) - 2468
21426 {AliasPatternCond::K_Ignore, 0},
21427 {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID},
21428 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
21429 {AliasPatternCond::K_Imm, uint32_t(0)},
21430 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
21431 // (PRFD_D_PZI sve_prfop:$prfop, PPR3bAny:$Pg, ZPR64:$Zn, 0) - 2473
21432 {AliasPatternCond::K_Ignore, 0},
21433 {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID},
21434 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
21435 {AliasPatternCond::K_Imm, uint32_t(0)},
21436 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
21437 // (PRFD_PRI sve_prfop:$prfop, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 2478
21438 {AliasPatternCond::K_Ignore, 0},
21439 {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID},
21440 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
21441 {AliasPatternCond::K_Imm, uint32_t(0)},
21442 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
21443 // (PRFD_S_PZI sve_prfop:$prfop, PPR3bAny:$Pg, ZPR32:$Zn, 0) - 2483
21444 {AliasPatternCond::K_Ignore, 0},
21445 {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID},
21446 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
21447 {AliasPatternCond::K_Imm, uint32_t(0)},
21448 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
21449 // (PRFH_D_PZI sve_prfop:$prfop, PPR3bAny:$Pg, ZPR64:$Zn, 0) - 2488
21450 {AliasPatternCond::K_Ignore, 0},
21451 {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID},
21452 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
21453 {AliasPatternCond::K_Imm, uint32_t(0)},
21454 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
21455 // (PRFH_PRI sve_prfop:$prfop, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 2493
21456 {AliasPatternCond::K_Ignore, 0},
21457 {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID},
21458 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
21459 {AliasPatternCond::K_Imm, uint32_t(0)},
21460 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
21461 // (PRFH_S_PZI sve_prfop:$prfop, PPR3bAny:$Pg, ZPR32:$Zn, 0) - 2498
21462 {AliasPatternCond::K_Ignore, 0},
21463 {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID},
21464 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
21465 {AliasPatternCond::K_Imm, uint32_t(0)},
21466 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
21467 // (PRFMroX prfop:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) - 2503
21468 {AliasPatternCond::K_Ignore, 0},
21469 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
21470 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
21471 {AliasPatternCond::K_Imm, uint32_t(0)},
21472 {AliasPatternCond::K_Imm, uint32_t(0)},
21473 // (PRFMui prfop:$Rt, GPR64sp:$Rn, 0) - 2508
21474 {AliasPatternCond::K_Ignore, 0},
21475 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
21476 {AliasPatternCond::K_Imm, uint32_t(0)},
21477 // (PRFUMi prfop:$Rt, GPR64sp:$Rn, 0) - 2511
21478 {AliasPatternCond::K_Ignore, 0},
21479 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
21480 {AliasPatternCond::K_Imm, uint32_t(0)},
21481 // (PRFW_D_PZI sve_prfop:$prfop, PPR3bAny:$Pg, ZPR64:$Zn, 0) - 2514
21482 {AliasPatternCond::K_Ignore, 0},
21483 {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID},
21484 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
21485 {AliasPatternCond::K_Imm, uint32_t(0)},
21486 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
21487 // (PRFW_PRI sve_prfop:$prfop, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 2519
21488 {AliasPatternCond::K_Ignore, 0},
21489 {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID},
21490 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
21491 {AliasPatternCond::K_Imm, uint32_t(0)},
21492 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
21493 // (PRFW_S_PZI sve_prfop:$prfop, PPR3bAny:$Pg, ZPR32:$Zn, 0) - 2524
21494 {AliasPatternCond::K_Ignore, 0},
21495 {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID},
21496 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
21497 {AliasPatternCond::K_Imm, uint32_t(0)},
21498 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
21499 // (PTRUES_B PPR8:$Pd, { 1, 1, 1, 1, 1 }) - 2529
21500 {AliasPatternCond::K_RegClass, AArch64::PPRRegClassID},
21501 {AliasPatternCond::K_Imm, uint32_t(31)},
21502 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
21503 // (PTRUES_D PPR64:$Pd, { 1, 1, 1, 1, 1 }) - 2532
21504 {AliasPatternCond::K_RegClass, AArch64::PPRRegClassID},
21505 {AliasPatternCond::K_Imm, uint32_t(31)},
21506 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
21507 // (PTRUES_H PPR16:$Pd, { 1, 1, 1, 1, 1 }) - 2535
21508 {AliasPatternCond::K_RegClass, AArch64::PPRRegClassID},
21509 {AliasPatternCond::K_Imm, uint32_t(31)},
21510 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
21511 // (PTRUES_S PPR32:$Pd, { 1, 1, 1, 1, 1 }) - 2538
21512 {AliasPatternCond::K_RegClass, AArch64::PPRRegClassID},
21513 {AliasPatternCond::K_Imm, uint32_t(31)},
21514 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
21515 // (PTRUE_B PPR8:$Pd, { 1, 1, 1, 1, 1 }) - 2541
21516 {AliasPatternCond::K_RegClass, AArch64::PPRRegClassID},
21517 {AliasPatternCond::K_Imm, uint32_t(31)},
21518 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
21519 // (PTRUE_D PPR64:$Pd, { 1, 1, 1, 1, 1 }) - 2544
21520 {AliasPatternCond::K_RegClass, AArch64::PPRRegClassID},
21521 {AliasPatternCond::K_Imm, uint32_t(31)},
21522 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
21523 // (PTRUE_H PPR16:$Pd, { 1, 1, 1, 1, 1 }) - 2547
21524 {AliasPatternCond::K_RegClass, AArch64::PPRRegClassID},
21525 {AliasPatternCond::K_Imm, uint32_t(31)},
21526 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
21527 // (PTRUE_S PPR32:$Pd, { 1, 1, 1, 1, 1 }) - 2550
21528 {AliasPatternCond::K_RegClass, AArch64::PPRRegClassID},
21529 {AliasPatternCond::K_Imm, uint32_t(31)},
21530 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
21531 // (RET LR) - 2553
21532 {AliasPatternCond::K_Reg, AArch64::LR},
21533 // (SBCSWr GPR32:$dst, WZR, GPR32:$src) - 2554
21534 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
21535 {AliasPatternCond::K_Reg, AArch64::WZR},
21536 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
21537 // (SBCSXr GPR64:$dst, XZR, GPR64:$src) - 2557
21538 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
21539 {AliasPatternCond::K_Reg, AArch64::XZR},
21540 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
21541 // (SBCWr GPR32:$dst, WZR, GPR32:$src) - 2560
21542 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
21543 {AliasPatternCond::K_Reg, AArch64::WZR},
21544 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
21545 // (SBCXr GPR64:$dst, XZR, GPR64:$src) - 2563
21546 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
21547 {AliasPatternCond::K_Reg, AArch64::XZR},
21548 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
21549 // (SBFMWri GPR32:$dst, GPR32:$src, imm0_31:$shift, 31) - 2566
21550 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
21551 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
21552 {AliasPatternCond::K_Ignore, 0},
21553 {AliasPatternCond::K_Imm, uint32_t(31)},
21554 // (SBFMWri GPR32:$dst, GPR32:$src, 0, 7) - 2570
21555 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
21556 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
21557 {AliasPatternCond::K_Imm, uint32_t(0)},
21558 {AliasPatternCond::K_Imm, uint32_t(7)},
21559 // (SBFMWri GPR32:$dst, GPR32:$src, 0, 15) - 2574
21560 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
21561 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
21562 {AliasPatternCond::K_Imm, uint32_t(0)},
21563 {AliasPatternCond::K_Imm, uint32_t(15)},
21564 // (SBFMXri GPR64:$dst, GPR64:$src, imm0_63:$shift, 63) - 2578
21565 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
21566 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
21567 {AliasPatternCond::K_Ignore, 0},
21568 {AliasPatternCond::K_Imm, uint32_t(63)},
21569 // (SBFMXri GPR64:$dst, GPR64:$src, 0, 7) - 2582
21570 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
21571 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
21572 {AliasPatternCond::K_Imm, uint32_t(0)},
21573 {AliasPatternCond::K_Imm, uint32_t(7)},
21574 // (SBFMXri GPR64:$dst, GPR64:$src, 0, 15) - 2586
21575 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
21576 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
21577 {AliasPatternCond::K_Imm, uint32_t(0)},
21578 {AliasPatternCond::K_Imm, uint32_t(15)},
21579 // (SBFMXri GPR64:$dst, GPR64:$src, 0, 31) - 2590
21580 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
21581 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
21582 {AliasPatternCond::K_Imm, uint32_t(0)},
21583 {AliasPatternCond::K_Imm, uint32_t(31)},
21584 // (SEL_PPPP PPR8:$Pd, PPRAny:$Pg, PPR8:$Pn, PPR8:$Pd) - 2594
21585 {AliasPatternCond::K_RegClass, AArch64::PPRRegClassID},
21586 {AliasPatternCond::K_RegClass, AArch64::PPRRegClassID},
21587 {AliasPatternCond::K_RegClass, AArch64::PPRRegClassID},
21588 {AliasPatternCond::K_TiedReg, 0},
21589 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
21590 // (SEL_ZPZZ_B ZPR8:$Zd, PPRAny:$Pg, ZPR8:$Zn, ZPR8:$Zd) - 2599
21591 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
21592 {AliasPatternCond::K_RegClass, AArch64::PPRRegClassID},
21593 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
21594 {AliasPatternCond::K_TiedReg, 0},
21595 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
21596 // (SEL_ZPZZ_D ZPR64:$Zd, PPRAny:$Pg, ZPR64:$Zn, ZPR64:$Zd) - 2604
21597 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
21598 {AliasPatternCond::K_RegClass, AArch64::PPRRegClassID},
21599 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
21600 {AliasPatternCond::K_TiedReg, 0},
21601 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
21602 // (SEL_ZPZZ_H ZPR16:$Zd, PPRAny:$Pg, ZPR16:$Zn, ZPR16:$Zd) - 2609
21603 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
21604 {AliasPatternCond::K_RegClass, AArch64::PPRRegClassID},
21605 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
21606 {AliasPatternCond::K_TiedReg, 0},
21607 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
21608 // (SEL_ZPZZ_S ZPR32:$Zd, PPRAny:$Pg, ZPR32:$Zn, ZPR32:$Zd) - 2614
21609 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
21610 {AliasPatternCond::K_RegClass, AArch64::PPRRegClassID},
21611 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
21612 {AliasPatternCond::K_TiedReg, 0},
21613 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
21614 // (SMADDLrrr GPR64:$dst, GPR32:$src1, GPR32:$src2, XZR) - 2619
21615 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
21616 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
21617 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
21618 {AliasPatternCond::K_Reg, AArch64::XZR},
21619 // (SMSUBLrrr GPR64:$dst, GPR32:$src1, GPR32:$src2, XZR) - 2623
21620 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
21621 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
21622 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
21623 {AliasPatternCond::K_Reg, AArch64::XZR},
21624 // (SQDECB_XPiI GPR64z:$Rdn, { 1, 1, 1, 1, 1 }, 1) - 2627
21625 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
21626 {AliasPatternCond::K_Ignore, 0},
21627 {AliasPatternCond::K_Imm, uint32_t(31)},
21628 {AliasPatternCond::K_Imm, uint32_t(1)},
21629 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
21630 // (SQDECB_XPiI GPR64z:$Rdn, sve_pred_enum:$pattern, 1) - 2632
21631 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
21632 {AliasPatternCond::K_Ignore, 0},
21633 {AliasPatternCond::K_Ignore, 0},
21634 {AliasPatternCond::K_Imm, uint32_t(1)},
21635 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
21636 // (SQDECB_XPiWdI GPR64z:$Rd, GPR64as32:$Rn, { 1, 1, 1, 1, 1 }, 1) - 2637
21637 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
21638 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
21639 {AliasPatternCond::K_Imm, uint32_t(31)},
21640 {AliasPatternCond::K_Imm, uint32_t(1)},
21641 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
21642 // (SQDECB_XPiWdI GPR64z:$Rd, GPR64as32:$Rn, sve_pred_enum:$pattern, 1) - 2642
21643 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
21644 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
21645 {AliasPatternCond::K_Ignore, 0},
21646 {AliasPatternCond::K_Imm, uint32_t(1)},
21647 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
21648 // (SQDECD_XPiI GPR64z:$Rdn, { 1, 1, 1, 1, 1 }, 1) - 2647
21649 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
21650 {AliasPatternCond::K_Ignore, 0},
21651 {AliasPatternCond::K_Imm, uint32_t(31)},
21652 {AliasPatternCond::K_Imm, uint32_t(1)},
21653 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
21654 // (SQDECD_XPiI GPR64z:$Rdn, sve_pred_enum:$pattern, 1) - 2652
21655 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
21656 {AliasPatternCond::K_Ignore, 0},
21657 {AliasPatternCond::K_Ignore, 0},
21658 {AliasPatternCond::K_Imm, uint32_t(1)},
21659 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
21660 // (SQDECD_XPiWdI GPR64z:$Rd, GPR64as32:$Rn, { 1, 1, 1, 1, 1 }, 1) - 2657
21661 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
21662 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
21663 {AliasPatternCond::K_Imm, uint32_t(31)},
21664 {AliasPatternCond::K_Imm, uint32_t(1)},
21665 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
21666 // (SQDECD_XPiWdI GPR64z:$Rd, GPR64as32:$Rn, sve_pred_enum:$pattern, 1) - 2662
21667 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
21668 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
21669 {AliasPatternCond::K_Ignore, 0},
21670 {AliasPatternCond::K_Imm, uint32_t(1)},
21671 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
21672 // (SQDECD_ZPiI ZPR64:$Zdn, { 1, 1, 1, 1, 1 }, 1) - 2667
21673 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
21674 {AliasPatternCond::K_Ignore, 0},
21675 {AliasPatternCond::K_Imm, uint32_t(31)},
21676 {AliasPatternCond::K_Imm, uint32_t(1)},
21677 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
21678 // (SQDECD_ZPiI ZPR64:$Zdn, sve_pred_enum:$pattern, 1) - 2672
21679 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
21680 {AliasPatternCond::K_Ignore, 0},
21681 {AliasPatternCond::K_Ignore, 0},
21682 {AliasPatternCond::K_Imm, uint32_t(1)},
21683 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
21684 // (SQDECH_XPiI GPR64z:$Rdn, { 1, 1, 1, 1, 1 }, 1) - 2677
21685 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
21686 {AliasPatternCond::K_Ignore, 0},
21687 {AliasPatternCond::K_Imm, uint32_t(31)},
21688 {AliasPatternCond::K_Imm, uint32_t(1)},
21689 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
21690 // (SQDECH_XPiI GPR64z:$Rdn, sve_pred_enum:$pattern, 1) - 2682
21691 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
21692 {AliasPatternCond::K_Ignore, 0},
21693 {AliasPatternCond::K_Ignore, 0},
21694 {AliasPatternCond::K_Imm, uint32_t(1)},
21695 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
21696 // (SQDECH_XPiWdI GPR64z:$Rd, GPR64as32:$Rn, { 1, 1, 1, 1, 1 }, 1) - 2687
21697 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
21698 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
21699 {AliasPatternCond::K_Imm, uint32_t(31)},
21700 {AliasPatternCond::K_Imm, uint32_t(1)},
21701 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
21702 // (SQDECH_XPiWdI GPR64z:$Rd, GPR64as32:$Rn, sve_pred_enum:$pattern, 1) - 2692
21703 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
21704 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
21705 {AliasPatternCond::K_Ignore, 0},
21706 {AliasPatternCond::K_Imm, uint32_t(1)},
21707 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
21708 // (SQDECH_ZPiI ZPR16:$Zdn, { 1, 1, 1, 1, 1 }, 1) - 2697
21709 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
21710 {AliasPatternCond::K_Ignore, 0},
21711 {AliasPatternCond::K_Imm, uint32_t(31)},
21712 {AliasPatternCond::K_Imm, uint32_t(1)},
21713 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
21714 // (SQDECH_ZPiI ZPR16:$Zdn, sve_pred_enum:$pattern, 1) - 2702
21715 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
21716 {AliasPatternCond::K_Ignore, 0},
21717 {AliasPatternCond::K_Ignore, 0},
21718 {AliasPatternCond::K_Imm, uint32_t(1)},
21719 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
21720 // (SQDECW_XPiI GPR64z:$Rdn, { 1, 1, 1, 1, 1 }, 1) - 2707
21721 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
21722 {AliasPatternCond::K_Ignore, 0},
21723 {AliasPatternCond::K_Imm, uint32_t(31)},
21724 {AliasPatternCond::K_Imm, uint32_t(1)},
21725 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
21726 // (SQDECW_XPiI GPR64z:$Rdn, sve_pred_enum:$pattern, 1) - 2712
21727 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
21728 {AliasPatternCond::K_Ignore, 0},
21729 {AliasPatternCond::K_Ignore, 0},
21730 {AliasPatternCond::K_Imm, uint32_t(1)},
21731 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
21732 // (SQDECW_XPiWdI GPR64z:$Rd, GPR64as32:$Rn, { 1, 1, 1, 1, 1 }, 1) - 2717
21733 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
21734 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
21735 {AliasPatternCond::K_Imm, uint32_t(31)},
21736 {AliasPatternCond::K_Imm, uint32_t(1)},
21737 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
21738 // (SQDECW_XPiWdI GPR64z:$Rd, GPR64as32:$Rn, sve_pred_enum:$pattern, 1) - 2722
21739 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
21740 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
21741 {AliasPatternCond::K_Ignore, 0},
21742 {AliasPatternCond::K_Imm, uint32_t(1)},
21743 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
21744 // (SQDECW_ZPiI ZPR32:$Zdn, { 1, 1, 1, 1, 1 }, 1) - 2727
21745 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
21746 {AliasPatternCond::K_Ignore, 0},
21747 {AliasPatternCond::K_Imm, uint32_t(31)},
21748 {AliasPatternCond::K_Imm, uint32_t(1)},
21749 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
21750 // (SQDECW_ZPiI ZPR32:$Zdn, sve_pred_enum:$pattern, 1) - 2732
21751 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
21752 {AliasPatternCond::K_Ignore, 0},
21753 {AliasPatternCond::K_Ignore, 0},
21754 {AliasPatternCond::K_Imm, uint32_t(1)},
21755 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
21756 // (SQINCB_XPiI GPR64z:$Rdn, { 1, 1, 1, 1, 1 }, 1) - 2737
21757 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
21758 {AliasPatternCond::K_Ignore, 0},
21759 {AliasPatternCond::K_Imm, uint32_t(31)},
21760 {AliasPatternCond::K_Imm, uint32_t(1)},
21761 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
21762 // (SQINCB_XPiI GPR64z:$Rdn, sve_pred_enum:$pattern, 1) - 2742
21763 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
21764 {AliasPatternCond::K_Ignore, 0},
21765 {AliasPatternCond::K_Ignore, 0},
21766 {AliasPatternCond::K_Imm, uint32_t(1)},
21767 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
21768 // (SQINCB_XPiWdI GPR64z:$Rd, GPR64as32:$Rn, { 1, 1, 1, 1, 1 }, 1) - 2747
21769 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
21770 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
21771 {AliasPatternCond::K_Imm, uint32_t(31)},
21772 {AliasPatternCond::K_Imm, uint32_t(1)},
21773 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
21774 // (SQINCB_XPiWdI GPR64z:$Rd, GPR64as32:$Rn, sve_pred_enum:$pattern, 1) - 2752
21775 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
21776 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
21777 {AliasPatternCond::K_Ignore, 0},
21778 {AliasPatternCond::K_Imm, uint32_t(1)},
21779 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
21780 // (SQINCD_XPiI GPR64z:$Rdn, { 1, 1, 1, 1, 1 }, 1) - 2757
21781 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
21782 {AliasPatternCond::K_Ignore, 0},
21783 {AliasPatternCond::K_Imm, uint32_t(31)},
21784 {AliasPatternCond::K_Imm, uint32_t(1)},
21785 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
21786 // (SQINCD_XPiI GPR64z:$Rdn, sve_pred_enum:$pattern, 1) - 2762
21787 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
21788 {AliasPatternCond::K_Ignore, 0},
21789 {AliasPatternCond::K_Ignore, 0},
21790 {AliasPatternCond::K_Imm, uint32_t(1)},
21791 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
21792 // (SQINCD_XPiWdI GPR64z:$Rd, GPR64as32:$Rn, { 1, 1, 1, 1, 1 }, 1) - 2767
21793 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
21794 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
21795 {AliasPatternCond::K_Imm, uint32_t(31)},
21796 {AliasPatternCond::K_Imm, uint32_t(1)},
21797 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
21798 // (SQINCD_XPiWdI GPR64z:$Rd, GPR64as32:$Rn, sve_pred_enum:$pattern, 1) - 2772
21799 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
21800 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
21801 {AliasPatternCond::K_Ignore, 0},
21802 {AliasPatternCond::K_Imm, uint32_t(1)},
21803 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
21804 // (SQINCD_ZPiI ZPR64:$Zdn, { 1, 1, 1, 1, 1 }, 1) - 2777
21805 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
21806 {AliasPatternCond::K_Ignore, 0},
21807 {AliasPatternCond::K_Imm, uint32_t(31)},
21808 {AliasPatternCond::K_Imm, uint32_t(1)},
21809 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
21810 // (SQINCD_ZPiI ZPR64:$Zdn, sve_pred_enum:$pattern, 1) - 2782
21811 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
21812 {AliasPatternCond::K_Ignore, 0},
21813 {AliasPatternCond::K_Ignore, 0},
21814 {AliasPatternCond::K_Imm, uint32_t(1)},
21815 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
21816 // (SQINCH_XPiI GPR64z:$Rdn, { 1, 1, 1, 1, 1 }, 1) - 2787
21817 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
21818 {AliasPatternCond::K_Ignore, 0},
21819 {AliasPatternCond::K_Imm, uint32_t(31)},
21820 {AliasPatternCond::K_Imm, uint32_t(1)},
21821 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
21822 // (SQINCH_XPiI GPR64z:$Rdn, sve_pred_enum:$pattern, 1) - 2792
21823 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
21824 {AliasPatternCond::K_Ignore, 0},
21825 {AliasPatternCond::K_Ignore, 0},
21826 {AliasPatternCond::K_Imm, uint32_t(1)},
21827 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
21828 // (SQINCH_XPiWdI GPR64z:$Rd, GPR64as32:$Rn, { 1, 1, 1, 1, 1 }, 1) - 2797
21829 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
21830 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
21831 {AliasPatternCond::K_Imm, uint32_t(31)},
21832 {AliasPatternCond::K_Imm, uint32_t(1)},
21833 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
21834 // (SQINCH_XPiWdI GPR64z:$Rd, GPR64as32:$Rn, sve_pred_enum:$pattern, 1) - 2802
21835 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
21836 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
21837 {AliasPatternCond::K_Ignore, 0},
21838 {AliasPatternCond::K_Imm, uint32_t(1)},
21839 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
21840 // (SQINCH_ZPiI ZPR16:$Zdn, { 1, 1, 1, 1, 1 }, 1) - 2807
21841 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
21842 {AliasPatternCond::K_Ignore, 0},
21843 {AliasPatternCond::K_Imm, uint32_t(31)},
21844 {AliasPatternCond::K_Imm, uint32_t(1)},
21845 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
21846 // (SQINCH_ZPiI ZPR16:$Zdn, sve_pred_enum:$pattern, 1) - 2812
21847 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
21848 {AliasPatternCond::K_Ignore, 0},
21849 {AliasPatternCond::K_Ignore, 0},
21850 {AliasPatternCond::K_Imm, uint32_t(1)},
21851 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
21852 // (SQINCW_XPiI GPR64z:$Rdn, { 1, 1, 1, 1, 1 }, 1) - 2817
21853 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
21854 {AliasPatternCond::K_Ignore, 0},
21855 {AliasPatternCond::K_Imm, uint32_t(31)},
21856 {AliasPatternCond::K_Imm, uint32_t(1)},
21857 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
21858 // (SQINCW_XPiI GPR64z:$Rdn, sve_pred_enum:$pattern, 1) - 2822
21859 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
21860 {AliasPatternCond::K_Ignore, 0},
21861 {AliasPatternCond::K_Ignore, 0},
21862 {AliasPatternCond::K_Imm, uint32_t(1)},
21863 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
21864 // (SQINCW_XPiWdI GPR64z:$Rd, GPR64as32:$Rn, { 1, 1, 1, 1, 1 }, 1) - 2827
21865 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
21866 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
21867 {AliasPatternCond::K_Imm, uint32_t(31)},
21868 {AliasPatternCond::K_Imm, uint32_t(1)},
21869 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
21870 // (SQINCW_XPiWdI GPR64z:$Rd, GPR64as32:$Rn, sve_pred_enum:$pattern, 1) - 2832
21871 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
21872 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
21873 {AliasPatternCond::K_Ignore, 0},
21874 {AliasPatternCond::K_Imm, uint32_t(1)},
21875 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
21876 // (SQINCW_ZPiI ZPR32:$Zdn, { 1, 1, 1, 1, 1 }, 1) - 2837
21877 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
21878 {AliasPatternCond::K_Ignore, 0},
21879 {AliasPatternCond::K_Imm, uint32_t(31)},
21880 {AliasPatternCond::K_Imm, uint32_t(1)},
21881 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
21882 // (SQINCW_ZPiI ZPR32:$Zdn, sve_pred_enum:$pattern, 1) - 2842
21883 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
21884 {AliasPatternCond::K_Ignore, 0},
21885 {AliasPatternCond::K_Ignore, 0},
21886 {AliasPatternCond::K_Imm, uint32_t(1)},
21887 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
21888 // (SST1B_D_IMM Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, 0) - 2847
21889 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
21890 {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID},
21891 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
21892 {AliasPatternCond::K_Imm, uint32_t(0)},
21893 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
21894 // (SST1B_S_IMM Z_s:$Zt, PPR3bAny:$Pg, ZPR32:$Zn, 0) - 2852
21895 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
21896 {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID},
21897 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
21898 {AliasPatternCond::K_Imm, uint32_t(0)},
21899 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
21900 // (SST1D_IMM Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, 0) - 2857
21901 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
21902 {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID},
21903 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
21904 {AliasPatternCond::K_Imm, uint32_t(0)},
21905 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
21906 // (SST1H_D_IMM Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, 0) - 2862
21907 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
21908 {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID},
21909 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
21910 {AliasPatternCond::K_Imm, uint32_t(0)},
21911 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
21912 // (SST1H_S_IMM Z_s:$Zt, PPR3bAny:$Pg, ZPR32:$Zn, 0) - 2867
21913 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
21914 {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID},
21915 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
21916 {AliasPatternCond::K_Imm, uint32_t(0)},
21917 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
21918 // (SST1W_D_IMM Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, 0) - 2872
21919 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
21920 {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID},
21921 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
21922 {AliasPatternCond::K_Imm, uint32_t(0)},
21923 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
21924 // (SST1W_IMM Z_s:$Zt, PPR3bAny:$Pg, ZPR32:$Zn, 0) - 2877
21925 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
21926 {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID},
21927 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
21928 {AliasPatternCond::K_Imm, uint32_t(0)},
21929 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
21930 // (ST1B_D_IMM Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 2882
21931 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
21932 {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID},
21933 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
21934 {AliasPatternCond::K_Imm, uint32_t(0)},
21935 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
21936 // (ST1B_H_IMM Z_h:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 2887
21937 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
21938 {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID},
21939 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
21940 {AliasPatternCond::K_Imm, uint32_t(0)},
21941 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
21942 // (ST1B_IMM Z_b:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 2892
21943 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
21944 {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID},
21945 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
21946 {AliasPatternCond::K_Imm, uint32_t(0)},
21947 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
21948 // (ST1B_S_IMM Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 2897
21949 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
21950 {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID},
21951 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
21952 {AliasPatternCond::K_Imm, uint32_t(0)},
21953 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
21954 // (ST1D_IMM Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 2902
21955 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
21956 {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID},
21957 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
21958 {AliasPatternCond::K_Imm, uint32_t(0)},
21959 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
21960 // (ST1Fourv16b_POST GPR64sp:$Rn, VecListFour16b:$Vt, XZR) - 2907
21961 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
21962 {AliasPatternCond::K_RegClass, AArch64::QQQQRegClassID},
21963 {AliasPatternCond::K_Ignore, 0},
21964 {AliasPatternCond::K_Reg, AArch64::XZR},
21965 {AliasPatternCond::K_Feature, AArch64::FeatureNEON},
21966 // (ST1Fourv1d_POST GPR64sp:$Rn, VecListFour1d:$Vt, XZR) - 2912
21967 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
21968 {AliasPatternCond::K_RegClass, AArch64::DDDDRegClassID},
21969 {AliasPatternCond::K_Ignore, 0},
21970 {AliasPatternCond::K_Reg, AArch64::XZR},
21971 {AliasPatternCond::K_Feature, AArch64::FeatureNEON},
21972 // (ST1Fourv2d_POST GPR64sp:$Rn, VecListFour2d:$Vt, XZR) - 2917
21973 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
21974 {AliasPatternCond::K_RegClass, AArch64::QQQQRegClassID},
21975 {AliasPatternCond::K_Ignore, 0},
21976 {AliasPatternCond::K_Reg, AArch64::XZR},
21977 {AliasPatternCond::K_Feature, AArch64::FeatureNEON},
21978 // (ST1Fourv2s_POST GPR64sp:$Rn, VecListFour2s:$Vt, XZR) - 2922
21979 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
21980 {AliasPatternCond::K_RegClass, AArch64::DDDDRegClassID},
21981 {AliasPatternCond::K_Ignore, 0},
21982 {AliasPatternCond::K_Reg, AArch64::XZR},
21983 {AliasPatternCond::K_Feature, AArch64::FeatureNEON},
21984 // (ST1Fourv4h_POST GPR64sp:$Rn, VecListFour4h:$Vt, XZR) - 2927
21985 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
21986 {AliasPatternCond::K_RegClass, AArch64::DDDDRegClassID},
21987 {AliasPatternCond::K_Ignore, 0},
21988 {AliasPatternCond::K_Reg, AArch64::XZR},
21989 {AliasPatternCond::K_Feature, AArch64::FeatureNEON},
21990 // (ST1Fourv4s_POST GPR64sp:$Rn, VecListFour4s:$Vt, XZR) - 2932
21991 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
21992 {AliasPatternCond::K_RegClass, AArch64::QQQQRegClassID},
21993 {AliasPatternCond::K_Ignore, 0},
21994 {AliasPatternCond::K_Reg, AArch64::XZR},
21995 {AliasPatternCond::K_Feature, AArch64::FeatureNEON},
21996 // (ST1Fourv8b_POST GPR64sp:$Rn, VecListFour8b:$Vt, XZR) - 2937
21997 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
21998 {AliasPatternCond::K_RegClass, AArch64::DDDDRegClassID},
21999 {AliasPatternCond::K_Ignore, 0},
22000 {AliasPatternCond::K_Reg, AArch64::XZR},
22001 {AliasPatternCond::K_Feature, AArch64::FeatureNEON},
22002 // (ST1Fourv8h_POST GPR64sp:$Rn, VecListFour8h:$Vt, XZR) - 2942
22003 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
22004 {AliasPatternCond::K_RegClass, AArch64::QQQQRegClassID},
22005 {AliasPatternCond::K_Ignore, 0},
22006 {AliasPatternCond::K_Reg, AArch64::XZR},
22007 {AliasPatternCond::K_Feature, AArch64::FeatureNEON},
22008 // (ST1H_D_IMM Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 2947
22009 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
22010 {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID},
22011 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
22012 {AliasPatternCond::K_Imm, uint32_t(0)},
22013 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
22014 // (ST1H_IMM Z_h:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 2952
22015 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
22016 {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID},
22017 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
22018 {AliasPatternCond::K_Imm, uint32_t(0)},
22019 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
22020 // (ST1H_S_IMM Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 2957
22021 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
22022 {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID},
22023 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
22024 {AliasPatternCond::K_Imm, uint32_t(0)},
22025 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
22026 // (ST1Onev16b_POST GPR64sp:$Rn, VecListOne16b:$Vt, XZR) - 2962
22027 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
22028 {AliasPatternCond::K_RegClass, AArch64::FPR128RegClassID},
22029 {AliasPatternCond::K_Ignore, 0},
22030 {AliasPatternCond::K_Reg, AArch64::XZR},
22031 {AliasPatternCond::K_Feature, AArch64::FeatureNEON},
22032 // (ST1Onev1d_POST GPR64sp:$Rn, VecListOne1d:$Vt, XZR) - 2967
22033 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
22034 {AliasPatternCond::K_RegClass, AArch64::FPR64RegClassID},
22035 {AliasPatternCond::K_Ignore, 0},
22036 {AliasPatternCond::K_Reg, AArch64::XZR},
22037 {AliasPatternCond::K_Feature, AArch64::FeatureNEON},
22038 // (ST1Onev2d_POST GPR64sp:$Rn, VecListOne2d:$Vt, XZR) - 2972
22039 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
22040 {AliasPatternCond::K_RegClass, AArch64::FPR128RegClassID},
22041 {AliasPatternCond::K_Ignore, 0},
22042 {AliasPatternCond::K_Reg, AArch64::XZR},
22043 {AliasPatternCond::K_Feature, AArch64::FeatureNEON},
22044 // (ST1Onev2s_POST GPR64sp:$Rn, VecListOne2s:$Vt, XZR) - 2977
22045 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
22046 {AliasPatternCond::K_RegClass, AArch64::FPR64RegClassID},
22047 {AliasPatternCond::K_Ignore, 0},
22048 {AliasPatternCond::K_Reg, AArch64::XZR},
22049 {AliasPatternCond::K_Feature, AArch64::FeatureNEON},
22050 // (ST1Onev4h_POST GPR64sp:$Rn, VecListOne4h:$Vt, XZR) - 2982
22051 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
22052 {AliasPatternCond::K_RegClass, AArch64::FPR64RegClassID},
22053 {AliasPatternCond::K_Ignore, 0},
22054 {AliasPatternCond::K_Reg, AArch64::XZR},
22055 {AliasPatternCond::K_Feature, AArch64::FeatureNEON},
22056 // (ST1Onev4s_POST GPR64sp:$Rn, VecListOne4s:$Vt, XZR) - 2987
22057 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
22058 {AliasPatternCond::K_RegClass, AArch64::FPR128RegClassID},
22059 {AliasPatternCond::K_Ignore, 0},
22060 {AliasPatternCond::K_Reg, AArch64::XZR},
22061 {AliasPatternCond::K_Feature, AArch64::FeatureNEON},
22062 // (ST1Onev8b_POST GPR64sp:$Rn, VecListOne8b:$Vt, XZR) - 2992
22063 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
22064 {AliasPatternCond::K_RegClass, AArch64::FPR64RegClassID},
22065 {AliasPatternCond::K_Ignore, 0},
22066 {AliasPatternCond::K_Reg, AArch64::XZR},
22067 {AliasPatternCond::K_Feature, AArch64::FeatureNEON},
22068 // (ST1Onev8h_POST GPR64sp:$Rn, VecListOne8h:$Vt, XZR) - 2997
22069 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
22070 {AliasPatternCond::K_RegClass, AArch64::FPR128RegClassID},
22071 {AliasPatternCond::K_Ignore, 0},
22072 {AliasPatternCond::K_Reg, AArch64::XZR},
22073 {AliasPatternCond::K_Feature, AArch64::FeatureNEON},
22074 // (ST1Threev16b_POST GPR64sp:$Rn, VecListThree16b:$Vt, XZR) - 3002
22075 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
22076 {AliasPatternCond::K_RegClass, AArch64::QQQRegClassID},
22077 {AliasPatternCond::K_Ignore, 0},
22078 {AliasPatternCond::K_Reg, AArch64::XZR},
22079 {AliasPatternCond::K_Feature, AArch64::FeatureNEON},
22080 // (ST1Threev1d_POST GPR64sp:$Rn, VecListThree1d:$Vt, XZR) - 3007
22081 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
22082 {AliasPatternCond::K_RegClass, AArch64::DDDRegClassID},
22083 {AliasPatternCond::K_Ignore, 0},
22084 {AliasPatternCond::K_Reg, AArch64::XZR},
22085 {AliasPatternCond::K_Feature, AArch64::FeatureNEON},
22086 // (ST1Threev2d_POST GPR64sp:$Rn, VecListThree2d:$Vt, XZR) - 3012
22087 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
22088 {AliasPatternCond::K_RegClass, AArch64::QQQRegClassID},
22089 {AliasPatternCond::K_Ignore, 0},
22090 {AliasPatternCond::K_Reg, AArch64::XZR},
22091 {AliasPatternCond::K_Feature, AArch64::FeatureNEON},
22092 // (ST1Threev2s_POST GPR64sp:$Rn, VecListThree2s:$Vt, XZR) - 3017
22093 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
22094 {AliasPatternCond::K_RegClass, AArch64::DDDRegClassID},
22095 {AliasPatternCond::K_Ignore, 0},
22096 {AliasPatternCond::K_Reg, AArch64::XZR},
22097 {AliasPatternCond::K_Feature, AArch64::FeatureNEON},
22098 // (ST1Threev4h_POST GPR64sp:$Rn, VecListThree4h:$Vt, XZR) - 3022
22099 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
22100 {AliasPatternCond::K_RegClass, AArch64::DDDRegClassID},
22101 {AliasPatternCond::K_Ignore, 0},
22102 {AliasPatternCond::K_Reg, AArch64::XZR},
22103 {AliasPatternCond::K_Feature, AArch64::FeatureNEON},
22104 // (ST1Threev4s_POST GPR64sp:$Rn, VecListThree4s:$Vt, XZR) - 3027
22105 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
22106 {AliasPatternCond::K_RegClass, AArch64::QQQRegClassID},
22107 {AliasPatternCond::K_Ignore, 0},
22108 {AliasPatternCond::K_Reg, AArch64::XZR},
22109 {AliasPatternCond::K_Feature, AArch64::FeatureNEON},
22110 // (ST1Threev8b_POST GPR64sp:$Rn, VecListThree8b:$Vt, XZR) - 3032
22111 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
22112 {AliasPatternCond::K_RegClass, AArch64::DDDRegClassID},
22113 {AliasPatternCond::K_Ignore, 0},
22114 {AliasPatternCond::K_Reg, AArch64::XZR},
22115 {AliasPatternCond::K_Feature, AArch64::FeatureNEON},
22116 // (ST1Threev8h_POST GPR64sp:$Rn, VecListThree8h:$Vt, XZR) - 3037
22117 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
22118 {AliasPatternCond::K_RegClass, AArch64::QQQRegClassID},
22119 {AliasPatternCond::K_Ignore, 0},
22120 {AliasPatternCond::K_Reg, AArch64::XZR},
22121 {AliasPatternCond::K_Feature, AArch64::FeatureNEON},
22122 // (ST1Twov16b_POST GPR64sp:$Rn, VecListTwo16b:$Vt, XZR) - 3042
22123 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
22124 {AliasPatternCond::K_RegClass, AArch64::QQRegClassID},
22125 {AliasPatternCond::K_Ignore, 0},
22126 {AliasPatternCond::K_Reg, AArch64::XZR},
22127 {AliasPatternCond::K_Feature, AArch64::FeatureNEON},
22128 // (ST1Twov1d_POST GPR64sp:$Rn, VecListTwo1d:$Vt, XZR) - 3047
22129 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
22130 {AliasPatternCond::K_RegClass, AArch64::DDRegClassID},
22131 {AliasPatternCond::K_Ignore, 0},
22132 {AliasPatternCond::K_Reg, AArch64::XZR},
22133 {AliasPatternCond::K_Feature, AArch64::FeatureNEON},
22134 // (ST1Twov2d_POST GPR64sp:$Rn, VecListTwo2d:$Vt, XZR) - 3052
22135 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
22136 {AliasPatternCond::K_RegClass, AArch64::QQRegClassID},
22137 {AliasPatternCond::K_Ignore, 0},
22138 {AliasPatternCond::K_Reg, AArch64::XZR},
22139 {AliasPatternCond::K_Feature, AArch64::FeatureNEON},
22140 // (ST1Twov2s_POST GPR64sp:$Rn, VecListTwo2s:$Vt, XZR) - 3057
22141 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
22142 {AliasPatternCond::K_RegClass, AArch64::DDRegClassID},
22143 {AliasPatternCond::K_Ignore, 0},
22144 {AliasPatternCond::K_Reg, AArch64::XZR},
22145 {AliasPatternCond::K_Feature, AArch64::FeatureNEON},
22146 // (ST1Twov4h_POST GPR64sp:$Rn, VecListTwo4h:$Vt, XZR) - 3062
22147 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
22148 {AliasPatternCond::K_RegClass, AArch64::DDRegClassID},
22149 {AliasPatternCond::K_Ignore, 0},
22150 {AliasPatternCond::K_Reg, AArch64::XZR},
22151 {AliasPatternCond::K_Feature, AArch64::FeatureNEON},
22152 // (ST1Twov4s_POST GPR64sp:$Rn, VecListTwo4s:$Vt, XZR) - 3067
22153 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
22154 {AliasPatternCond::K_RegClass, AArch64::QQRegClassID},
22155 {AliasPatternCond::K_Ignore, 0},
22156 {AliasPatternCond::K_Reg, AArch64::XZR},
22157 {AliasPatternCond::K_Feature, AArch64::FeatureNEON},
22158 // (ST1Twov8b_POST GPR64sp:$Rn, VecListTwo8b:$Vt, XZR) - 3072
22159 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
22160 {AliasPatternCond::K_RegClass, AArch64::DDRegClassID},
22161 {AliasPatternCond::K_Ignore, 0},
22162 {AliasPatternCond::K_Reg, AArch64::XZR},
22163 {AliasPatternCond::K_Feature, AArch64::FeatureNEON},
22164 // (ST1Twov8h_POST GPR64sp:$Rn, VecListTwo8h:$Vt, XZR) - 3077
22165 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
22166 {AliasPatternCond::K_RegClass, AArch64::QQRegClassID},
22167 {AliasPatternCond::K_Ignore, 0},
22168 {AliasPatternCond::K_Reg, AArch64::XZR},
22169 {AliasPatternCond::K_Feature, AArch64::FeatureNEON},
22170 // (ST1W_D_IMM Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 3082
22171 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
22172 {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID},
22173 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
22174 {AliasPatternCond::K_Imm, uint32_t(0)},
22175 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
22176 // (ST1W_IMM Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 3087
22177 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
22178 {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID},
22179 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
22180 {AliasPatternCond::K_Imm, uint32_t(0)},
22181 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
22182 // (ST1i16_POST GPR64sp:$Rn, VecListOneh:$Vt, VectorIndexH:$idx, XZR) - 3092
22183 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
22184 {AliasPatternCond::K_RegClass, AArch64::FPR128RegClassID},
22185 {AliasPatternCond::K_Ignore, 0},
22186 {AliasPatternCond::K_Ignore, 0},
22187 {AliasPatternCond::K_Reg, AArch64::XZR},
22188 {AliasPatternCond::K_Feature, AArch64::FeatureNEON},
22189 // (ST1i32_POST GPR64sp:$Rn, VecListOnes:$Vt, VectorIndexS:$idx, XZR) - 3098
22190 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
22191 {AliasPatternCond::K_RegClass, AArch64::FPR128RegClassID},
22192 {AliasPatternCond::K_Ignore, 0},
22193 {AliasPatternCond::K_Ignore, 0},
22194 {AliasPatternCond::K_Reg, AArch64::XZR},
22195 {AliasPatternCond::K_Feature, AArch64::FeatureNEON},
22196 // (ST1i64_POST GPR64sp:$Rn, VecListOned:$Vt, VectorIndexD:$idx, XZR) - 3104
22197 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
22198 {AliasPatternCond::K_RegClass, AArch64::FPR128RegClassID},
22199 {AliasPatternCond::K_Ignore, 0},
22200 {AliasPatternCond::K_Ignore, 0},
22201 {AliasPatternCond::K_Reg, AArch64::XZR},
22202 {AliasPatternCond::K_Feature, AArch64::FeatureNEON},
22203 // (ST1i8_POST GPR64sp:$Rn, VecListOneb:$Vt, VectorIndexB:$idx, XZR) - 3110
22204 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
22205 {AliasPatternCond::K_RegClass, AArch64::FPR128RegClassID},
22206 {AliasPatternCond::K_Ignore, 0},
22207 {AliasPatternCond::K_Ignore, 0},
22208 {AliasPatternCond::K_Reg, AArch64::XZR},
22209 {AliasPatternCond::K_Feature, AArch64::FeatureNEON},
22210 // (ST2B_IMM ZZ_b:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 3116
22211 {AliasPatternCond::K_RegClass, AArch64::ZPR2RegClassID},
22212 {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID},
22213 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
22214 {AliasPatternCond::K_Imm, uint32_t(0)},
22215 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
22216 // (ST2D_IMM ZZ_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 3121
22217 {AliasPatternCond::K_RegClass, AArch64::ZPR2RegClassID},
22218 {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID},
22219 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
22220 {AliasPatternCond::K_Imm, uint32_t(0)},
22221 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
22222 // (ST2GOffset GPR64sp:$Rt, GPR64sp:$Rn, 0) - 3126
22223 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
22224 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
22225 {AliasPatternCond::K_Imm, uint32_t(0)},
22226 {AliasPatternCond::K_Feature, AArch64::FeatureMTE},
22227 // (ST2H_IMM ZZ_h:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 3130
22228 {AliasPatternCond::K_RegClass, AArch64::ZPR2RegClassID},
22229 {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID},
22230 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
22231 {AliasPatternCond::K_Imm, uint32_t(0)},
22232 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
22233 // (ST2Twov16b_POST GPR64sp:$Rn, VecListTwo16b:$Vt, XZR) - 3135
22234 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
22235 {AliasPatternCond::K_RegClass, AArch64::QQRegClassID},
22236 {AliasPatternCond::K_Ignore, 0},
22237 {AliasPatternCond::K_Reg, AArch64::XZR},
22238 {AliasPatternCond::K_Feature, AArch64::FeatureNEON},
22239 // (ST2Twov2d_POST GPR64sp:$Rn, VecListTwo2d:$Vt, XZR) - 3140
22240 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
22241 {AliasPatternCond::K_RegClass, AArch64::QQRegClassID},
22242 {AliasPatternCond::K_Ignore, 0},
22243 {AliasPatternCond::K_Reg, AArch64::XZR},
22244 {AliasPatternCond::K_Feature, AArch64::FeatureNEON},
22245 // (ST2Twov2s_POST GPR64sp:$Rn, VecListTwo2s:$Vt, XZR) - 3145
22246 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
22247 {AliasPatternCond::K_RegClass, AArch64::DDRegClassID},
22248 {AliasPatternCond::K_Ignore, 0},
22249 {AliasPatternCond::K_Reg, AArch64::XZR},
22250 {AliasPatternCond::K_Feature, AArch64::FeatureNEON},
22251 // (ST2Twov4h_POST GPR64sp:$Rn, VecListTwo4h:$Vt, XZR) - 3150
22252 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
22253 {AliasPatternCond::K_RegClass, AArch64::DDRegClassID},
22254 {AliasPatternCond::K_Ignore, 0},
22255 {AliasPatternCond::K_Reg, AArch64::XZR},
22256 {AliasPatternCond::K_Feature, AArch64::FeatureNEON},
22257 // (ST2Twov4s_POST GPR64sp:$Rn, VecListTwo4s:$Vt, XZR) - 3155
22258 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
22259 {AliasPatternCond::K_RegClass, AArch64::QQRegClassID},
22260 {AliasPatternCond::K_Ignore, 0},
22261 {AliasPatternCond::K_Reg, AArch64::XZR},
22262 {AliasPatternCond::K_Feature, AArch64::FeatureNEON},
22263 // (ST2Twov8b_POST GPR64sp:$Rn, VecListTwo8b:$Vt, XZR) - 3160
22264 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
22265 {AliasPatternCond::K_RegClass, AArch64::DDRegClassID},
22266 {AliasPatternCond::K_Ignore, 0},
22267 {AliasPatternCond::K_Reg, AArch64::XZR},
22268 {AliasPatternCond::K_Feature, AArch64::FeatureNEON},
22269 // (ST2Twov8h_POST GPR64sp:$Rn, VecListTwo8h:$Vt, XZR) - 3165
22270 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
22271 {AliasPatternCond::K_RegClass, AArch64::QQRegClassID},
22272 {AliasPatternCond::K_Ignore, 0},
22273 {AliasPatternCond::K_Reg, AArch64::XZR},
22274 {AliasPatternCond::K_Feature, AArch64::FeatureNEON},
22275 // (ST2W_IMM ZZ_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 3170
22276 {AliasPatternCond::K_RegClass, AArch64::ZPR2RegClassID},
22277 {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID},
22278 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
22279 {AliasPatternCond::K_Imm, uint32_t(0)},
22280 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
22281 // (ST2i16_POST GPR64sp:$Rn, VecListTwoh:$Vt, VectorIndexH:$idx, XZR) - 3175
22282 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
22283 {AliasPatternCond::K_RegClass, AArch64::QQRegClassID},
22284 {AliasPatternCond::K_Ignore, 0},
22285 {AliasPatternCond::K_Ignore, 0},
22286 {AliasPatternCond::K_Reg, AArch64::XZR},
22287 {AliasPatternCond::K_Feature, AArch64::FeatureNEON},
22288 // (ST2i32_POST GPR64sp:$Rn, VecListTwos:$Vt, VectorIndexS:$idx, XZR) - 3181
22289 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
22290 {AliasPatternCond::K_RegClass, AArch64::QQRegClassID},
22291 {AliasPatternCond::K_Ignore, 0},
22292 {AliasPatternCond::K_Ignore, 0},
22293 {AliasPatternCond::K_Reg, AArch64::XZR},
22294 {AliasPatternCond::K_Feature, AArch64::FeatureNEON},
22295 // (ST2i64_POST GPR64sp:$Rn, VecListTwod:$Vt, VectorIndexD:$idx, XZR) - 3187
22296 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
22297 {AliasPatternCond::K_RegClass, AArch64::QQRegClassID},
22298 {AliasPatternCond::K_Ignore, 0},
22299 {AliasPatternCond::K_Ignore, 0},
22300 {AliasPatternCond::K_Reg, AArch64::XZR},
22301 {AliasPatternCond::K_Feature, AArch64::FeatureNEON},
22302 // (ST2i8_POST GPR64sp:$Rn, VecListTwob:$Vt, VectorIndexB:$idx, XZR) - 3193
22303 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
22304 {AliasPatternCond::K_RegClass, AArch64::QQRegClassID},
22305 {AliasPatternCond::K_Ignore, 0},
22306 {AliasPatternCond::K_Ignore, 0},
22307 {AliasPatternCond::K_Reg, AArch64::XZR},
22308 {AliasPatternCond::K_Feature, AArch64::FeatureNEON},
22309 // (ST3B_IMM ZZZ_b:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 3199
22310 {AliasPatternCond::K_RegClass, AArch64::ZPR3RegClassID},
22311 {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID},
22312 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
22313 {AliasPatternCond::K_Imm, uint32_t(0)},
22314 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
22315 // (ST3D_IMM ZZZ_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 3204
22316 {AliasPatternCond::K_RegClass, AArch64::ZPR3RegClassID},
22317 {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID},
22318 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
22319 {AliasPatternCond::K_Imm, uint32_t(0)},
22320 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
22321 // (ST3H_IMM ZZZ_h:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 3209
22322 {AliasPatternCond::K_RegClass, AArch64::ZPR3RegClassID},
22323 {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID},
22324 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
22325 {AliasPatternCond::K_Imm, uint32_t(0)},
22326 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
22327 // (ST3Threev16b_POST GPR64sp:$Rn, VecListThree16b:$Vt, XZR) - 3214
22328 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
22329 {AliasPatternCond::K_RegClass, AArch64::QQQRegClassID},
22330 {AliasPatternCond::K_Ignore, 0},
22331 {AliasPatternCond::K_Reg, AArch64::XZR},
22332 {AliasPatternCond::K_Feature, AArch64::FeatureNEON},
22333 // (ST3Threev2d_POST GPR64sp:$Rn, VecListThree2d:$Vt, XZR) - 3219
22334 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
22335 {AliasPatternCond::K_RegClass, AArch64::QQQRegClassID},
22336 {AliasPatternCond::K_Ignore, 0},
22337 {AliasPatternCond::K_Reg, AArch64::XZR},
22338 {AliasPatternCond::K_Feature, AArch64::FeatureNEON},
22339 // (ST3Threev2s_POST GPR64sp:$Rn, VecListThree2s:$Vt, XZR) - 3224
22340 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
22341 {AliasPatternCond::K_RegClass, AArch64::DDDRegClassID},
22342 {AliasPatternCond::K_Ignore, 0},
22343 {AliasPatternCond::K_Reg, AArch64::XZR},
22344 {AliasPatternCond::K_Feature, AArch64::FeatureNEON},
22345 // (ST3Threev4h_POST GPR64sp:$Rn, VecListThree4h:$Vt, XZR) - 3229
22346 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
22347 {AliasPatternCond::K_RegClass, AArch64::DDDRegClassID},
22348 {AliasPatternCond::K_Ignore, 0},
22349 {AliasPatternCond::K_Reg, AArch64::XZR},
22350 {AliasPatternCond::K_Feature, AArch64::FeatureNEON},
22351 // (ST3Threev4s_POST GPR64sp:$Rn, VecListThree4s:$Vt, XZR) - 3234
22352 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
22353 {AliasPatternCond::K_RegClass, AArch64::QQQRegClassID},
22354 {AliasPatternCond::K_Ignore, 0},
22355 {AliasPatternCond::K_Reg, AArch64::XZR},
22356 {AliasPatternCond::K_Feature, AArch64::FeatureNEON},
22357 // (ST3Threev8b_POST GPR64sp:$Rn, VecListThree8b:$Vt, XZR) - 3239
22358 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
22359 {AliasPatternCond::K_RegClass, AArch64::DDDRegClassID},
22360 {AliasPatternCond::K_Ignore, 0},
22361 {AliasPatternCond::K_Reg, AArch64::XZR},
22362 {AliasPatternCond::K_Feature, AArch64::FeatureNEON},
22363 // (ST3Threev8h_POST GPR64sp:$Rn, VecListThree8h:$Vt, XZR) - 3244
22364 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
22365 {AliasPatternCond::K_RegClass, AArch64::QQQRegClassID},
22366 {AliasPatternCond::K_Ignore, 0},
22367 {AliasPatternCond::K_Reg, AArch64::XZR},
22368 {AliasPatternCond::K_Feature, AArch64::FeatureNEON},
22369 // (ST3W_IMM ZZZ_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 3249
22370 {AliasPatternCond::K_RegClass, AArch64::ZPR3RegClassID},
22371 {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID},
22372 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
22373 {AliasPatternCond::K_Imm, uint32_t(0)},
22374 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
22375 // (ST3i16_POST GPR64sp:$Rn, VecListThreeh:$Vt, VectorIndexH:$idx, XZR) - 3254
22376 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
22377 {AliasPatternCond::K_RegClass, AArch64::QQQRegClassID},
22378 {AliasPatternCond::K_Ignore, 0},
22379 {AliasPatternCond::K_Ignore, 0},
22380 {AliasPatternCond::K_Reg, AArch64::XZR},
22381 {AliasPatternCond::K_Feature, AArch64::FeatureNEON},
22382 // (ST3i32_POST GPR64sp:$Rn, VecListThrees:$Vt, VectorIndexS:$idx, XZR) - 3260
22383 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
22384 {AliasPatternCond::K_RegClass, AArch64::QQQRegClassID},
22385 {AliasPatternCond::K_Ignore, 0},
22386 {AliasPatternCond::K_Ignore, 0},
22387 {AliasPatternCond::K_Reg, AArch64::XZR},
22388 {AliasPatternCond::K_Feature, AArch64::FeatureNEON},
22389 // (ST3i64_POST GPR64sp:$Rn, VecListThreed:$Vt, VectorIndexD:$idx, XZR) - 3266
22390 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
22391 {AliasPatternCond::K_RegClass, AArch64::QQQRegClassID},
22392 {AliasPatternCond::K_Ignore, 0},
22393 {AliasPatternCond::K_Ignore, 0},
22394 {AliasPatternCond::K_Reg, AArch64::XZR},
22395 {AliasPatternCond::K_Feature, AArch64::FeatureNEON},
22396 // (ST3i8_POST GPR64sp:$Rn, VecListThreeb:$Vt, VectorIndexB:$idx, XZR) - 3272
22397 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
22398 {AliasPatternCond::K_RegClass, AArch64::QQQRegClassID},
22399 {AliasPatternCond::K_Ignore, 0},
22400 {AliasPatternCond::K_Ignore, 0},
22401 {AliasPatternCond::K_Reg, AArch64::XZR},
22402 {AliasPatternCond::K_Feature, AArch64::FeatureNEON},
22403 // (ST4B_IMM ZZZZ_b:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 3278
22404 {AliasPatternCond::K_RegClass, AArch64::ZPR4RegClassID},
22405 {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID},
22406 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
22407 {AliasPatternCond::K_Imm, uint32_t(0)},
22408 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
22409 // (ST4D_IMM ZZZZ_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 3283
22410 {AliasPatternCond::K_RegClass, AArch64::ZPR4RegClassID},
22411 {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID},
22412 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
22413 {AliasPatternCond::K_Imm, uint32_t(0)},
22414 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
22415 // (ST4Fourv16b_POST GPR64sp:$Rn, VecListFour16b:$Vt, XZR) - 3288
22416 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
22417 {AliasPatternCond::K_RegClass, AArch64::QQQQRegClassID},
22418 {AliasPatternCond::K_Ignore, 0},
22419 {AliasPatternCond::K_Reg, AArch64::XZR},
22420 {AliasPatternCond::K_Feature, AArch64::FeatureNEON},
22421 // (ST4Fourv2d_POST GPR64sp:$Rn, VecListFour2d:$Vt, XZR) - 3293
22422 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
22423 {AliasPatternCond::K_RegClass, AArch64::QQQQRegClassID},
22424 {AliasPatternCond::K_Ignore, 0},
22425 {AliasPatternCond::K_Reg, AArch64::XZR},
22426 {AliasPatternCond::K_Feature, AArch64::FeatureNEON},
22427 // (ST4Fourv2s_POST GPR64sp:$Rn, VecListFour2s:$Vt, XZR) - 3298
22428 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
22429 {AliasPatternCond::K_RegClass, AArch64::DDDDRegClassID},
22430 {AliasPatternCond::K_Ignore, 0},
22431 {AliasPatternCond::K_Reg, AArch64::XZR},
22432 {AliasPatternCond::K_Feature, AArch64::FeatureNEON},
22433 // (ST4Fourv4h_POST GPR64sp:$Rn, VecListFour4h:$Vt, XZR) - 3303
22434 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
22435 {AliasPatternCond::K_RegClass, AArch64::DDDDRegClassID},
22436 {AliasPatternCond::K_Ignore, 0},
22437 {AliasPatternCond::K_Reg, AArch64::XZR},
22438 {AliasPatternCond::K_Feature, AArch64::FeatureNEON},
22439 // (ST4Fourv4s_POST GPR64sp:$Rn, VecListFour4s:$Vt, XZR) - 3308
22440 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
22441 {AliasPatternCond::K_RegClass, AArch64::QQQQRegClassID},
22442 {AliasPatternCond::K_Ignore, 0},
22443 {AliasPatternCond::K_Reg, AArch64::XZR},
22444 {AliasPatternCond::K_Feature, AArch64::FeatureNEON},
22445 // (ST4Fourv8b_POST GPR64sp:$Rn, VecListFour8b:$Vt, XZR) - 3313
22446 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
22447 {AliasPatternCond::K_RegClass, AArch64::DDDDRegClassID},
22448 {AliasPatternCond::K_Ignore, 0},
22449 {AliasPatternCond::K_Reg, AArch64::XZR},
22450 {AliasPatternCond::K_Feature, AArch64::FeatureNEON},
22451 // (ST4Fourv8h_POST GPR64sp:$Rn, VecListFour8h:$Vt, XZR) - 3318
22452 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
22453 {AliasPatternCond::K_RegClass, AArch64::QQQQRegClassID},
22454 {AliasPatternCond::K_Ignore, 0},
22455 {AliasPatternCond::K_Reg, AArch64::XZR},
22456 {AliasPatternCond::K_Feature, AArch64::FeatureNEON},
22457 // (ST4H_IMM ZZZZ_h:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 3323
22458 {AliasPatternCond::K_RegClass, AArch64::ZPR4RegClassID},
22459 {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID},
22460 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
22461 {AliasPatternCond::K_Imm, uint32_t(0)},
22462 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
22463 // (ST4W_IMM ZZZZ_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 3328
22464 {AliasPatternCond::K_RegClass, AArch64::ZPR4RegClassID},
22465 {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID},
22466 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
22467 {AliasPatternCond::K_Imm, uint32_t(0)},
22468 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
22469 // (ST4i16_POST GPR64sp:$Rn, VecListFourh:$Vt, VectorIndexH:$idx, XZR) - 3333
22470 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
22471 {AliasPatternCond::K_RegClass, AArch64::QQQQRegClassID},
22472 {AliasPatternCond::K_Ignore, 0},
22473 {AliasPatternCond::K_Ignore, 0},
22474 {AliasPatternCond::K_Reg, AArch64::XZR},
22475 {AliasPatternCond::K_Feature, AArch64::FeatureNEON},
22476 // (ST4i32_POST GPR64sp:$Rn, VecListFours:$Vt, VectorIndexS:$idx, XZR) - 3339
22477 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
22478 {AliasPatternCond::K_RegClass, AArch64::QQQQRegClassID},
22479 {AliasPatternCond::K_Ignore, 0},
22480 {AliasPatternCond::K_Ignore, 0},
22481 {AliasPatternCond::K_Reg, AArch64::XZR},
22482 {AliasPatternCond::K_Feature, AArch64::FeatureNEON},
22483 // (ST4i64_POST GPR64sp:$Rn, VecListFourd:$Vt, VectorIndexD:$idx, XZR) - 3345
22484 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
22485 {AliasPatternCond::K_RegClass, AArch64::QQQQRegClassID},
22486 {AliasPatternCond::K_Ignore, 0},
22487 {AliasPatternCond::K_Ignore, 0},
22488 {AliasPatternCond::K_Reg, AArch64::XZR},
22489 {AliasPatternCond::K_Feature, AArch64::FeatureNEON},
22490 // (ST4i8_POST GPR64sp:$Rn, VecListFourb:$Vt, VectorIndexB:$idx, XZR) - 3351
22491 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
22492 {AliasPatternCond::K_RegClass, AArch64::QQQQRegClassID},
22493 {AliasPatternCond::K_Ignore, 0},
22494 {AliasPatternCond::K_Ignore, 0},
22495 {AliasPatternCond::K_Reg, AArch64::XZR},
22496 {AliasPatternCond::K_Feature, AArch64::FeatureNEON},
22497 // (STGOffset GPR64sp:$Rt, GPR64sp:$Rn, 0) - 3357
22498 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
22499 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
22500 {AliasPatternCond::K_Imm, uint32_t(0)},
22501 {AliasPatternCond::K_Feature, AArch64::FeatureMTE},
22502 // (STGPi GPR64z:$Rt, GPR64z:$Rt2, GPR64sp:$Rn, 0) - 3361
22503 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
22504 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
22505 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
22506 {AliasPatternCond::K_Imm, uint32_t(0)},
22507 {AliasPatternCond::K_Feature, AArch64::FeatureMTE},
22508 // (STLURBi GPR32:$Rt, GPR64sp:$Rn, 0) - 3366
22509 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
22510 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
22511 {AliasPatternCond::K_Imm, uint32_t(0)},
22512 {AliasPatternCond::K_Feature, AArch64::FeatureRCPC_IMMO},
22513 // (STLURHi GPR32:$Rt, GPR64sp:$Rn, 0) - 3370
22514 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
22515 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
22516 {AliasPatternCond::K_Imm, uint32_t(0)},
22517 {AliasPatternCond::K_Feature, AArch64::FeatureRCPC_IMMO},
22518 // (STLURWi GPR32:$Rt, GPR64sp:$Rn, 0) - 3374
22519 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
22520 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
22521 {AliasPatternCond::K_Imm, uint32_t(0)},
22522 {AliasPatternCond::K_Feature, AArch64::FeatureRCPC_IMMO},
22523 // (STLURXi GPR64:$Rt, GPR64sp:$Rn, 0) - 3378
22524 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
22525 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
22526 {AliasPatternCond::K_Imm, uint32_t(0)},
22527 {AliasPatternCond::K_Feature, AArch64::FeatureRCPC_IMMO},
22528 // (STNPDi FPR64Op:$Rt, FPR64Op:$Rt2, GPR64sp:$Rn, 0) - 3382
22529 {AliasPatternCond::K_RegClass, AArch64::FPR64RegClassID},
22530 {AliasPatternCond::K_RegClass, AArch64::FPR64RegClassID},
22531 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
22532 {AliasPatternCond::K_Imm, uint32_t(0)},
22533 // (STNPQi FPR128Op:$Rt, FPR128Op:$Rt2, GPR64sp:$Rn, 0) - 3386
22534 {AliasPatternCond::K_RegClass, AArch64::FPR128RegClassID},
22535 {AliasPatternCond::K_RegClass, AArch64::FPR128RegClassID},
22536 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
22537 {AliasPatternCond::K_Imm, uint32_t(0)},
22538 // (STNPSi FPR32Op:$Rt, FPR32Op:$Rt2, GPR64sp:$Rn, 0) - 3390
22539 {AliasPatternCond::K_RegClass, AArch64::FPR32RegClassID},
22540 {AliasPatternCond::K_RegClass, AArch64::FPR32RegClassID},
22541 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
22542 {AliasPatternCond::K_Imm, uint32_t(0)},
22543 // (STNPWi GPR32z:$Rt, GPR32z:$Rt2, GPR64sp:$Rn, 0) - 3394
22544 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
22545 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
22546 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
22547 {AliasPatternCond::K_Imm, uint32_t(0)},
22548 // (STNPXi GPR64z:$Rt, GPR64z:$Rt2, GPR64sp:$Rn, 0) - 3398
22549 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
22550 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
22551 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
22552 {AliasPatternCond::K_Imm, uint32_t(0)},
22553 // (STNT1B_ZRI Z_b:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 3402
22554 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
22555 {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID},
22556 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
22557 {AliasPatternCond::K_Imm, uint32_t(0)},
22558 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
22559 // (STNT1B_ZZR_D_REAL Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, XZR) - 3407
22560 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
22561 {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID},
22562 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
22563 {AliasPatternCond::K_Reg, AArch64::XZR},
22564 {AliasPatternCond::K_Feature, AArch64::FeatureSVE2},
22565 // (STNT1B_ZZR_S_REAL Z_s:$Zt, PPR3bAny:$Pg, ZPR32:$Zn, XZR) - 3412
22566 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
22567 {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID},
22568 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
22569 {AliasPatternCond::K_Reg, AArch64::XZR},
22570 {AliasPatternCond::K_Feature, AArch64::FeatureSVE2},
22571 // (STNT1D_ZRI Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 3417
22572 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
22573 {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID},
22574 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
22575 {AliasPatternCond::K_Imm, uint32_t(0)},
22576 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
22577 // (STNT1D_ZZR_D_REAL Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, XZR) - 3422
22578 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
22579 {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID},
22580 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
22581 {AliasPatternCond::K_Reg, AArch64::XZR},
22582 {AliasPatternCond::K_Feature, AArch64::FeatureSVE2},
22583 // (STNT1H_ZRI Z_h:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 3427
22584 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
22585 {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID},
22586 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
22587 {AliasPatternCond::K_Imm, uint32_t(0)},
22588 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
22589 // (STNT1H_ZZR_D_REAL Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, XZR) - 3432
22590 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
22591 {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID},
22592 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
22593 {AliasPatternCond::K_Reg, AArch64::XZR},
22594 {AliasPatternCond::K_Feature, AArch64::FeatureSVE2},
22595 // (STNT1H_ZZR_S_REAL Z_s:$Zt, PPR3bAny:$Pg, ZPR32:$Zn, XZR) - 3437
22596 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
22597 {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID},
22598 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
22599 {AliasPatternCond::K_Reg, AArch64::XZR},
22600 {AliasPatternCond::K_Feature, AArch64::FeatureSVE2},
22601 // (STNT1W_ZRI Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 3442
22602 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
22603 {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID},
22604 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
22605 {AliasPatternCond::K_Imm, uint32_t(0)},
22606 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
22607 // (STNT1W_ZZR_D_REAL Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, XZR) - 3447
22608 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
22609 {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID},
22610 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
22611 {AliasPatternCond::K_Reg, AArch64::XZR},
22612 {AliasPatternCond::K_Feature, AArch64::FeatureSVE2},
22613 // (STNT1W_ZZR_S_REAL Z_s:$Zt, PPR3bAny:$Pg, ZPR32:$Zn, XZR) - 3452
22614 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
22615 {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID},
22616 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
22617 {AliasPatternCond::K_Reg, AArch64::XZR},
22618 {AliasPatternCond::K_Feature, AArch64::FeatureSVE2},
22619 // (STPDi FPR64Op:$Rt, FPR64Op:$Rt2, GPR64sp:$Rn, 0) - 3457
22620 {AliasPatternCond::K_RegClass, AArch64::FPR64RegClassID},
22621 {AliasPatternCond::K_RegClass, AArch64::FPR64RegClassID},
22622 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
22623 {AliasPatternCond::K_Imm, uint32_t(0)},
22624 // (STPQi FPR128Op:$Rt, FPR128Op:$Rt2, GPR64sp:$Rn, 0) - 3461
22625 {AliasPatternCond::K_RegClass, AArch64::FPR128RegClassID},
22626 {AliasPatternCond::K_RegClass, AArch64::FPR128RegClassID},
22627 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
22628 {AliasPatternCond::K_Imm, uint32_t(0)},
22629 // (STPSi FPR32Op:$Rt, FPR32Op:$Rt2, GPR64sp:$Rn, 0) - 3465
22630 {AliasPatternCond::K_RegClass, AArch64::FPR32RegClassID},
22631 {AliasPatternCond::K_RegClass, AArch64::FPR32RegClassID},
22632 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
22633 {AliasPatternCond::K_Imm, uint32_t(0)},
22634 // (STPWi GPR32z:$Rt, GPR32z:$Rt2, GPR64sp:$Rn, 0) - 3469
22635 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
22636 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
22637 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
22638 {AliasPatternCond::K_Imm, uint32_t(0)},
22639 // (STPXi GPR64z:$Rt, GPR64z:$Rt2, GPR64sp:$Rn, 0) - 3473
22640 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
22641 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
22642 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
22643 {AliasPatternCond::K_Imm, uint32_t(0)},
22644 // (STRBBroX GPR32:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) - 3477
22645 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
22646 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
22647 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
22648 {AliasPatternCond::K_Imm, uint32_t(0)},
22649 {AliasPatternCond::K_Imm, uint32_t(0)},
22650 // (STRBBui GPR32z:$Rt, GPR64sp:$Rn, 0) - 3482
22651 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
22652 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
22653 {AliasPatternCond::K_Imm, uint32_t(0)},
22654 // (STRBroX FPR8Op:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) - 3485
22655 {AliasPatternCond::K_RegClass, AArch64::FPR8RegClassID},
22656 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
22657 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
22658 {AliasPatternCond::K_Imm, uint32_t(0)},
22659 {AliasPatternCond::K_Imm, uint32_t(0)},
22660 // (STRBui FPR8Op:$Rt, GPR64sp:$Rn, 0) - 3490
22661 {AliasPatternCond::K_RegClass, AArch64::FPR8RegClassID},
22662 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
22663 {AliasPatternCond::K_Imm, uint32_t(0)},
22664 // (STRDroX FPR64Op:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) - 3493
22665 {AliasPatternCond::K_RegClass, AArch64::FPR64RegClassID},
22666 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
22667 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
22668 {AliasPatternCond::K_Imm, uint32_t(0)},
22669 {AliasPatternCond::K_Imm, uint32_t(0)},
22670 // (STRDui FPR64Op:$Rt, GPR64sp:$Rn, 0) - 3498
22671 {AliasPatternCond::K_RegClass, AArch64::FPR64RegClassID},
22672 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
22673 {AliasPatternCond::K_Imm, uint32_t(0)},
22674 // (STRHHroX GPR32:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) - 3501
22675 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
22676 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
22677 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
22678 {AliasPatternCond::K_Imm, uint32_t(0)},
22679 {AliasPatternCond::K_Imm, uint32_t(0)},
22680 // (STRHHui GPR32z:$Rt, GPR64sp:$Rn, 0) - 3506
22681 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
22682 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
22683 {AliasPatternCond::K_Imm, uint32_t(0)},
22684 // (STRHroX FPR16Op:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) - 3509
22685 {AliasPatternCond::K_RegClass, AArch64::FPR16RegClassID},
22686 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
22687 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
22688 {AliasPatternCond::K_Imm, uint32_t(0)},
22689 {AliasPatternCond::K_Imm, uint32_t(0)},
22690 // (STRHui FPR16Op:$Rt, GPR64sp:$Rn, 0) - 3514
22691 {AliasPatternCond::K_RegClass, AArch64::FPR16RegClassID},
22692 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
22693 {AliasPatternCond::K_Imm, uint32_t(0)},
22694 // (STRQroX FPR128Op:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) - 3517
22695 {AliasPatternCond::K_RegClass, AArch64::FPR128RegClassID},
22696 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
22697 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
22698 {AliasPatternCond::K_Imm, uint32_t(0)},
22699 {AliasPatternCond::K_Imm, uint32_t(0)},
22700 // (STRQui FPR128Op:$Rt, GPR64sp:$Rn, 0) - 3522
22701 {AliasPatternCond::K_RegClass, AArch64::FPR128RegClassID},
22702 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
22703 {AliasPatternCond::K_Imm, uint32_t(0)},
22704 // (STRSroX FPR32Op:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) - 3525
22705 {AliasPatternCond::K_RegClass, AArch64::FPR32RegClassID},
22706 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
22707 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
22708 {AliasPatternCond::K_Imm, uint32_t(0)},
22709 {AliasPatternCond::K_Imm, uint32_t(0)},
22710 // (STRSui FPR32Op:$Rt, GPR64sp:$Rn, 0) - 3530
22711 {AliasPatternCond::K_RegClass, AArch64::FPR32RegClassID},
22712 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
22713 {AliasPatternCond::K_Imm, uint32_t(0)},
22714 // (STRWroX GPR32:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) - 3533
22715 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
22716 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
22717 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
22718 {AliasPatternCond::K_Imm, uint32_t(0)},
22719 {AliasPatternCond::K_Imm, uint32_t(0)},
22720 // (STRWui GPR32z:$Rt, GPR64sp:$Rn, 0) - 3538
22721 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
22722 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
22723 {AliasPatternCond::K_Imm, uint32_t(0)},
22724 // (STRXroX GPR64:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) - 3541
22725 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
22726 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
22727 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
22728 {AliasPatternCond::K_Imm, uint32_t(0)},
22729 {AliasPatternCond::K_Imm, uint32_t(0)},
22730 // (STRXui GPR64z:$Rt, GPR64sp:$Rn, 0) - 3546
22731 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
22732 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
22733 {AliasPatternCond::K_Imm, uint32_t(0)},
22734 // (STR_PXI PPRAny:$Pt, GPR64sp:$Rn, 0) - 3549
22735 {AliasPatternCond::K_RegClass, AArch64::PPRRegClassID},
22736 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
22737 {AliasPatternCond::K_Imm, uint32_t(0)},
22738 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
22739 // (STR_ZXI ZPRAny:$Zt, GPR64sp:$Rn, 0) - 3553
22740 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
22741 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
22742 {AliasPatternCond::K_Imm, uint32_t(0)},
22743 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
22744 // (STTRBi GPR32:$Rt, GPR64sp:$Rn, 0) - 3557
22745 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
22746 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
22747 {AliasPatternCond::K_Imm, uint32_t(0)},
22748 // (STTRHi GPR32:$Rt, GPR64sp:$Rn, 0) - 3560
22749 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
22750 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
22751 {AliasPatternCond::K_Imm, uint32_t(0)},
22752 // (STTRWi GPR32:$Rt, GPR64sp:$Rn, 0) - 3563
22753 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
22754 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
22755 {AliasPatternCond::K_Imm, uint32_t(0)},
22756 // (STTRXi GPR64:$Rt, GPR64sp:$Rn, 0) - 3566
22757 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
22758 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
22759 {AliasPatternCond::K_Imm, uint32_t(0)},
22760 // (STURBBi GPR32z:$Rt, GPR64sp:$Rn, 0) - 3569
22761 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
22762 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
22763 {AliasPatternCond::K_Imm, uint32_t(0)},
22764 // (STURBi FPR8Op:$Rt, GPR64sp:$Rn, 0) - 3572
22765 {AliasPatternCond::K_RegClass, AArch64::FPR8RegClassID},
22766 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
22767 {AliasPatternCond::K_Imm, uint32_t(0)},
22768 // (STURDi FPR64Op:$Rt, GPR64sp:$Rn, 0) - 3575
22769 {AliasPatternCond::K_RegClass, AArch64::FPR64RegClassID},
22770 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
22771 {AliasPatternCond::K_Imm, uint32_t(0)},
22772 // (STURHHi GPR32z:$Rt, GPR64sp:$Rn, 0) - 3578
22773 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
22774 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
22775 {AliasPatternCond::K_Imm, uint32_t(0)},
22776 // (STURHi FPR16Op:$Rt, GPR64sp:$Rn, 0) - 3581
22777 {AliasPatternCond::K_RegClass, AArch64::FPR16RegClassID},
22778 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
22779 {AliasPatternCond::K_Imm, uint32_t(0)},
22780 // (STURQi FPR128Op:$Rt, GPR64sp:$Rn, 0) - 3584
22781 {AliasPatternCond::K_RegClass, AArch64::FPR128RegClassID},
22782 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
22783 {AliasPatternCond::K_Imm, uint32_t(0)},
22784 // (STURSi FPR32Op:$Rt, GPR64sp:$Rn, 0) - 3587
22785 {AliasPatternCond::K_RegClass, AArch64::FPR32RegClassID},
22786 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
22787 {AliasPatternCond::K_Imm, uint32_t(0)},
22788 // (STURWi GPR32z:$Rt, GPR64sp:$Rn, 0) - 3590
22789 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
22790 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
22791 {AliasPatternCond::K_Imm, uint32_t(0)},
22792 // (STURXi GPR64z:$Rt, GPR64sp:$Rn, 0) - 3593
22793 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
22794 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
22795 {AliasPatternCond::K_Imm, uint32_t(0)},
22796 // (STZ2GOffset GPR64sp:$Rt, GPR64sp:$Rn, 0) - 3596
22797 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
22798 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
22799 {AliasPatternCond::K_Imm, uint32_t(0)},
22800 {AliasPatternCond::K_Feature, AArch64::FeatureMTE},
22801 // (STZGOffset GPR64sp:$Rt, GPR64sp:$Rn, 0) - 3600
22802 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
22803 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
22804 {AliasPatternCond::K_Imm, uint32_t(0)},
22805 {AliasPatternCond::K_Feature, AArch64::FeatureMTE},
22806 // (SUBSWri WZR, GPR32sp:$src, addsub_shifted_imm32:$imm) - 3604
22807 {AliasPatternCond::K_Reg, AArch64::WZR},
22808 {AliasPatternCond::K_RegClass, AArch64::GPR32spRegClassID},
22809 // (SUBSWrs WZR, GPR32:$src1, GPR32:$src2, 0) - 3606
22810 {AliasPatternCond::K_Reg, AArch64::WZR},
22811 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
22812 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
22813 {AliasPatternCond::K_Imm, uint32_t(0)},
22814 // (SUBSWrs WZR, GPR32:$src1, GPR32:$src2, arith_shift32:$sh) - 3610
22815 {AliasPatternCond::K_Reg, AArch64::WZR},
22816 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
22817 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
22818 // (SUBSWrs GPR32:$dst, WZR, GPR32:$src, 0) - 3613
22819 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
22820 {AliasPatternCond::K_Reg, AArch64::WZR},
22821 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
22822 {AliasPatternCond::K_Imm, uint32_t(0)},
22823 // (SUBSWrs GPR32:$dst, WZR, GPR32:$src, arith_shift32:$shift) - 3617
22824 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
22825 {AliasPatternCond::K_Reg, AArch64::WZR},
22826 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
22827 // (SUBSWrs GPR32:$dst, GPR32:$src1, GPR32:$src2, 0) - 3620
22828 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
22829 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
22830 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
22831 {AliasPatternCond::K_Imm, uint32_t(0)},
22832 // (SUBSWrx WZR, GPR32sponly:$src1, GPR32:$src2, 16) - 3624
22833 {AliasPatternCond::K_Reg, AArch64::WZR},
22834 {AliasPatternCond::K_RegClass, AArch64::GPR32sponlyRegClassID},
22835 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
22836 {AliasPatternCond::K_Imm, uint32_t(16)},
22837 // (SUBSWrx WZR, GPR32sp:$src1, GPR32:$src2, arith_extend:$sh) - 3628
22838 {AliasPatternCond::K_Reg, AArch64::WZR},
22839 {AliasPatternCond::K_RegClass, AArch64::GPR32spRegClassID},
22840 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
22841 // (SUBSWrx GPR32:$dst, GPR32sponly:$src1, GPR32:$src2, 16) - 3631
22842 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
22843 {AliasPatternCond::K_RegClass, AArch64::GPR32sponlyRegClassID},
22844 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
22845 {AliasPatternCond::K_Imm, uint32_t(16)},
22846 // (SUBSXri XZR, GPR64sp:$src, addsub_shifted_imm64:$imm) - 3635
22847 {AliasPatternCond::K_Reg, AArch64::XZR},
22848 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
22849 // (SUBSXrs XZR, GPR64:$src1, GPR64:$src2, 0) - 3637
22850 {AliasPatternCond::K_Reg, AArch64::XZR},
22851 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
22852 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
22853 {AliasPatternCond::K_Imm, uint32_t(0)},
22854 // (SUBSXrs XZR, GPR64:$src1, GPR64:$src2, arith_shift64:$sh) - 3641
22855 {AliasPatternCond::K_Reg, AArch64::XZR},
22856 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
22857 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
22858 // (SUBSXrs GPR64:$dst, XZR, GPR64:$src, 0) - 3644
22859 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
22860 {AliasPatternCond::K_Reg, AArch64::XZR},
22861 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
22862 {AliasPatternCond::K_Imm, uint32_t(0)},
22863 // (SUBSXrs GPR64:$dst, XZR, GPR64:$src, arith_shift64:$shift) - 3648
22864 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
22865 {AliasPatternCond::K_Reg, AArch64::XZR},
22866 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
22867 // (SUBSXrs GPR64:$dst, GPR64:$src1, GPR64:$src2, 0) - 3651
22868 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
22869 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
22870 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
22871 {AliasPatternCond::K_Imm, uint32_t(0)},
22872 // (SUBSXrx XZR, GPR64sp:$src1, GPR32:$src2, arith_extend:$sh) - 3655
22873 {AliasPatternCond::K_Reg, AArch64::XZR},
22874 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
22875 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
22876 // (SUBSXrx64 XZR, GPR64sponly:$src1, GPR64:$src2, 24) - 3658
22877 {AliasPatternCond::K_Reg, AArch64::XZR},
22878 {AliasPatternCond::K_RegClass, AArch64::GPR64sponlyRegClassID},
22879 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
22880 {AliasPatternCond::K_Imm, uint32_t(24)},
22881 // (SUBSXrx64 XZR, GPR64sp:$src1, GPR64:$src2, arith_extendlsl64:$sh) - 3662
22882 {AliasPatternCond::K_Reg, AArch64::XZR},
22883 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
22884 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
22885 // (SUBSXrx64 GPR64:$dst, GPR64sponly:$src1, GPR64:$src2, 24) - 3665
22886 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
22887 {AliasPatternCond::K_RegClass, AArch64::GPR64sponlyRegClassID},
22888 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
22889 {AliasPatternCond::K_Imm, uint32_t(24)},
22890 // (SUBWrs GPR32:$dst, WZR, GPR32:$src, 0) - 3669
22891 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
22892 {AliasPatternCond::K_Reg, AArch64::WZR},
22893 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
22894 {AliasPatternCond::K_Imm, uint32_t(0)},
22895 // (SUBWrs GPR32:$dst, WZR, GPR32:$src, arith_shift32:$shift) - 3673
22896 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
22897 {AliasPatternCond::K_Reg, AArch64::WZR},
22898 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
22899 // (SUBWrs GPR32:$dst, GPR32:$src1, GPR32:$src2, 0) - 3676
22900 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
22901 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
22902 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
22903 {AliasPatternCond::K_Imm, uint32_t(0)},
22904 // (SUBWrx GPR32sponly:$dst, GPR32sp:$src1, GPR32:$src2, 16) - 3680
22905 {AliasPatternCond::K_RegClass, AArch64::GPR32sponlyRegClassID},
22906 {AliasPatternCond::K_RegClass, AArch64::GPR32spRegClassID},
22907 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
22908 {AliasPatternCond::K_Imm, uint32_t(16)},
22909 // (SUBWrx GPR32sp:$dst, GPR32sponly:$src1, GPR32:$src2, 16) - 3684
22910 {AliasPatternCond::K_RegClass, AArch64::GPR32spRegClassID},
22911 {AliasPatternCond::K_RegClass, AArch64::GPR32sponlyRegClassID},
22912 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
22913 {AliasPatternCond::K_Imm, uint32_t(16)},
22914 // (SUBXrs GPR64:$dst, XZR, GPR64:$src, 0) - 3688
22915 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
22916 {AliasPatternCond::K_Reg, AArch64::XZR},
22917 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
22918 {AliasPatternCond::K_Imm, uint32_t(0)},
22919 // (SUBXrs GPR64:$dst, XZR, GPR64:$src, arith_shift64:$shift) - 3692
22920 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
22921 {AliasPatternCond::K_Reg, AArch64::XZR},
22922 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
22923 // (SUBXrs GPR64:$dst, GPR64:$src1, GPR64:$src2, 0) - 3695
22924 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
22925 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
22926 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
22927 {AliasPatternCond::K_Imm, uint32_t(0)},
22928 // (SUBXrx64 GPR64sponly:$dst, GPR64sp:$src1, GPR64:$src2, 24) - 3699
22929 {AliasPatternCond::K_RegClass, AArch64::GPR64sponlyRegClassID},
22930 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
22931 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
22932 {AliasPatternCond::K_Imm, uint32_t(24)},
22933 // (SUBXrx64 GPR64sp:$dst, GPR64sponly:$src1, GPR64:$src2, 24) - 3703
22934 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
22935 {AliasPatternCond::K_RegClass, AArch64::GPR64sponlyRegClassID},
22936 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
22937 {AliasPatternCond::K_Imm, uint32_t(24)},
22938 // (SYSxt imm0_7:$op1, sys_cr_op:$Cn, sys_cr_op:$Cm, imm0_7:$op2, XZR) - 3707
22939 {AliasPatternCond::K_Ignore, 0},
22940 {AliasPatternCond::K_Ignore, 0},
22941 {AliasPatternCond::K_Ignore, 0},
22942 {AliasPatternCond::K_Ignore, 0},
22943 {AliasPatternCond::K_Reg, AArch64::XZR},
22944 // (UBFMWri GPR32:$dst, GPR32:$src, imm0_31:$shift, 31) - 3712
22945 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
22946 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
22947 {AliasPatternCond::K_Ignore, 0},
22948 {AliasPatternCond::K_Imm, uint32_t(31)},
22949 // (UBFMWri GPR32:$dst, GPR32:$src, 0, 7) - 3716
22950 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
22951 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
22952 {AliasPatternCond::K_Imm, uint32_t(0)},
22953 {AliasPatternCond::K_Imm, uint32_t(7)},
22954 // (UBFMWri GPR32:$dst, GPR32:$src, 0, 15) - 3720
22955 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
22956 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
22957 {AliasPatternCond::K_Imm, uint32_t(0)},
22958 {AliasPatternCond::K_Imm, uint32_t(15)},
22959 // (UBFMXri GPR64:$dst, GPR64:$src, imm0_63:$shift, 63) - 3724
22960 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
22961 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
22962 {AliasPatternCond::K_Ignore, 0},
22963 {AliasPatternCond::K_Imm, uint32_t(63)},
22964 // (UBFMXri GPR64:$dst, GPR64:$src, 0, 7) - 3728
22965 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
22966 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
22967 {AliasPatternCond::K_Imm, uint32_t(0)},
22968 {AliasPatternCond::K_Imm, uint32_t(7)},
22969 // (UBFMXri GPR64:$dst, GPR64:$src, 0, 15) - 3732
22970 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
22971 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
22972 {AliasPatternCond::K_Imm, uint32_t(0)},
22973 {AliasPatternCond::K_Imm, uint32_t(15)},
22974 // (UBFMXri GPR64:$dst, GPR64:$src, 0, 31) - 3736
22975 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
22976 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
22977 {AliasPatternCond::K_Imm, uint32_t(0)},
22978 {AliasPatternCond::K_Imm, uint32_t(31)},
22979 // (UMADDLrrr GPR64:$dst, GPR32:$src1, GPR32:$src2, XZR) - 3740
22980 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
22981 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
22982 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
22983 {AliasPatternCond::K_Reg, AArch64::XZR},
22984 // (UMOVvi32 GPR32:$dst, V128:$src, VectorIndexS:$idx) - 3744
22985 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
22986 {AliasPatternCond::K_RegClass, AArch64::FPR128RegClassID},
22987 {AliasPatternCond::K_Feature, AArch64::FeatureNEON},
22988 // (UMOVvi64 GPR64:$dst, V128:$src, VectorIndexD:$idx) - 3747
22989 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
22990 {AliasPatternCond::K_RegClass, AArch64::FPR128RegClassID},
22991 {AliasPatternCond::K_Feature, AArch64::FeatureNEON},
22992 // (UMSUBLrrr GPR64:$dst, GPR32:$src1, GPR32:$src2, XZR) - 3750
22993 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
22994 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
22995 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
22996 {AliasPatternCond::K_Reg, AArch64::XZR},
22997 // (UQDECB_WPiI GPR32z:$Rdn, { 1, 1, 1, 1, 1 }, 1) - 3754
22998 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
22999 {AliasPatternCond::K_Ignore, 0},
23000 {AliasPatternCond::K_Imm, uint32_t(31)},
23001 {AliasPatternCond::K_Imm, uint32_t(1)},
23002 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
23003 // (UQDECB_WPiI GPR32z:$Rdn, sve_pred_enum:$pattern, 1) - 3759
23004 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
23005 {AliasPatternCond::K_Ignore, 0},
23006 {AliasPatternCond::K_Ignore, 0},
23007 {AliasPatternCond::K_Imm, uint32_t(1)},
23008 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
23009 // (UQDECB_XPiI GPR64z:$Rdn, { 1, 1, 1, 1, 1 }, 1) - 3764
23010 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
23011 {AliasPatternCond::K_Ignore, 0},
23012 {AliasPatternCond::K_Imm, uint32_t(31)},
23013 {AliasPatternCond::K_Imm, uint32_t(1)},
23014 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
23015 // (UQDECB_XPiI GPR64z:$Rdn, sve_pred_enum:$pattern, 1) - 3769
23016 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
23017 {AliasPatternCond::K_Ignore, 0},
23018 {AliasPatternCond::K_Ignore, 0},
23019 {AliasPatternCond::K_Imm, uint32_t(1)},
23020 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
23021 // (UQDECD_WPiI GPR32z:$Rdn, { 1, 1, 1, 1, 1 }, 1) - 3774
23022 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
23023 {AliasPatternCond::K_Ignore, 0},
23024 {AliasPatternCond::K_Imm, uint32_t(31)},
23025 {AliasPatternCond::K_Imm, uint32_t(1)},
23026 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
23027 // (UQDECD_WPiI GPR32z:$Rdn, sve_pred_enum:$pattern, 1) - 3779
23028 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
23029 {AliasPatternCond::K_Ignore, 0},
23030 {AliasPatternCond::K_Ignore, 0},
23031 {AliasPatternCond::K_Imm, uint32_t(1)},
23032 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
23033 // (UQDECD_XPiI GPR64z:$Rdn, { 1, 1, 1, 1, 1 }, 1) - 3784
23034 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
23035 {AliasPatternCond::K_Ignore, 0},
23036 {AliasPatternCond::K_Imm, uint32_t(31)},
23037 {AliasPatternCond::K_Imm, uint32_t(1)},
23038 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
23039 // (UQDECD_XPiI GPR64z:$Rdn, sve_pred_enum:$pattern, 1) - 3789
23040 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
23041 {AliasPatternCond::K_Ignore, 0},
23042 {AliasPatternCond::K_Ignore, 0},
23043 {AliasPatternCond::K_Imm, uint32_t(1)},
23044 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
23045 // (UQDECD_ZPiI ZPR64:$Zdn, { 1, 1, 1, 1, 1 }, 1) - 3794
23046 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
23047 {AliasPatternCond::K_Ignore, 0},
23048 {AliasPatternCond::K_Imm, uint32_t(31)},
23049 {AliasPatternCond::K_Imm, uint32_t(1)},
23050 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
23051 // (UQDECD_ZPiI ZPR64:$Zdn, sve_pred_enum:$pattern, 1) - 3799
23052 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
23053 {AliasPatternCond::K_Ignore, 0},
23054 {AliasPatternCond::K_Ignore, 0},
23055 {AliasPatternCond::K_Imm, uint32_t(1)},
23056 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
23057 // (UQDECH_WPiI GPR32z:$Rdn, { 1, 1, 1, 1, 1 }, 1) - 3804
23058 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
23059 {AliasPatternCond::K_Ignore, 0},
23060 {AliasPatternCond::K_Imm, uint32_t(31)},
23061 {AliasPatternCond::K_Imm, uint32_t(1)},
23062 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
23063 // (UQDECH_WPiI GPR32z:$Rdn, sve_pred_enum:$pattern, 1) - 3809
23064 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
23065 {AliasPatternCond::K_Ignore, 0},
23066 {AliasPatternCond::K_Ignore, 0},
23067 {AliasPatternCond::K_Imm, uint32_t(1)},
23068 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
23069 // (UQDECH_XPiI GPR64z:$Rdn, { 1, 1, 1, 1, 1 }, 1) - 3814
23070 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
23071 {AliasPatternCond::K_Ignore, 0},
23072 {AliasPatternCond::K_Imm, uint32_t(31)},
23073 {AliasPatternCond::K_Imm, uint32_t(1)},
23074 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
23075 // (UQDECH_XPiI GPR64z:$Rdn, sve_pred_enum:$pattern, 1) - 3819
23076 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
23077 {AliasPatternCond::K_Ignore, 0},
23078 {AliasPatternCond::K_Ignore, 0},
23079 {AliasPatternCond::K_Imm, uint32_t(1)},
23080 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
23081 // (UQDECH_ZPiI ZPR16:$Zdn, { 1, 1, 1, 1, 1 }, 1) - 3824
23082 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
23083 {AliasPatternCond::K_Ignore, 0},
23084 {AliasPatternCond::K_Imm, uint32_t(31)},
23085 {AliasPatternCond::K_Imm, uint32_t(1)},
23086 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
23087 // (UQDECH_ZPiI ZPR16:$Zdn, sve_pred_enum:$pattern, 1) - 3829
23088 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
23089 {AliasPatternCond::K_Ignore, 0},
23090 {AliasPatternCond::K_Ignore, 0},
23091 {AliasPatternCond::K_Imm, uint32_t(1)},
23092 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
23093 // (UQDECW_WPiI GPR32z:$Rdn, { 1, 1, 1, 1, 1 }, 1) - 3834
23094 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
23095 {AliasPatternCond::K_Ignore, 0},
23096 {AliasPatternCond::K_Imm, uint32_t(31)},
23097 {AliasPatternCond::K_Imm, uint32_t(1)},
23098 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
23099 // (UQDECW_WPiI GPR32z:$Rdn, sve_pred_enum:$pattern, 1) - 3839
23100 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
23101 {AliasPatternCond::K_Ignore, 0},
23102 {AliasPatternCond::K_Ignore, 0},
23103 {AliasPatternCond::K_Imm, uint32_t(1)},
23104 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
23105 // (UQDECW_XPiI GPR64z:$Rdn, { 1, 1, 1, 1, 1 }, 1) - 3844
23106 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
23107 {AliasPatternCond::K_Ignore, 0},
23108 {AliasPatternCond::K_Imm, uint32_t(31)},
23109 {AliasPatternCond::K_Imm, uint32_t(1)},
23110 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
23111 // (UQDECW_XPiI GPR64z:$Rdn, sve_pred_enum:$pattern, 1) - 3849
23112 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
23113 {AliasPatternCond::K_Ignore, 0},
23114 {AliasPatternCond::K_Ignore, 0},
23115 {AliasPatternCond::K_Imm, uint32_t(1)},
23116 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
23117 // (UQDECW_ZPiI ZPR32:$Zdn, { 1, 1, 1, 1, 1 }, 1) - 3854
23118 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
23119 {AliasPatternCond::K_Ignore, 0},
23120 {AliasPatternCond::K_Imm, uint32_t(31)},
23121 {AliasPatternCond::K_Imm, uint32_t(1)},
23122 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
23123 // (UQDECW_ZPiI ZPR32:$Zdn, sve_pred_enum:$pattern, 1) - 3859
23124 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
23125 {AliasPatternCond::K_Ignore, 0},
23126 {AliasPatternCond::K_Ignore, 0},
23127 {AliasPatternCond::K_Imm, uint32_t(1)},
23128 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
23129 // (UQINCB_WPiI GPR32z:$Rdn, { 1, 1, 1, 1, 1 }, 1) - 3864
23130 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
23131 {AliasPatternCond::K_Ignore, 0},
23132 {AliasPatternCond::K_Imm, uint32_t(31)},
23133 {AliasPatternCond::K_Imm, uint32_t(1)},
23134 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
23135 // (UQINCB_WPiI GPR32z:$Rdn, sve_pred_enum:$pattern, 1) - 3869
23136 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
23137 {AliasPatternCond::K_Ignore, 0},
23138 {AliasPatternCond::K_Ignore, 0},
23139 {AliasPatternCond::K_Imm, uint32_t(1)},
23140 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
23141 // (UQINCB_XPiI GPR64z:$Rdn, { 1, 1, 1, 1, 1 }, 1) - 3874
23142 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
23143 {AliasPatternCond::K_Ignore, 0},
23144 {AliasPatternCond::K_Imm, uint32_t(31)},
23145 {AliasPatternCond::K_Imm, uint32_t(1)},
23146 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
23147 // (UQINCB_XPiI GPR64z:$Rdn, sve_pred_enum:$pattern, 1) - 3879
23148 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
23149 {AliasPatternCond::K_Ignore, 0},
23150 {AliasPatternCond::K_Ignore, 0},
23151 {AliasPatternCond::K_Imm, uint32_t(1)},
23152 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
23153 // (UQINCD_WPiI GPR32z:$Rdn, { 1, 1, 1, 1, 1 }, 1) - 3884
23154 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
23155 {AliasPatternCond::K_Ignore, 0},
23156 {AliasPatternCond::K_Imm, uint32_t(31)},
23157 {AliasPatternCond::K_Imm, uint32_t(1)},
23158 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
23159 // (UQINCD_WPiI GPR32z:$Rdn, sve_pred_enum:$pattern, 1) - 3889
23160 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
23161 {AliasPatternCond::K_Ignore, 0},
23162 {AliasPatternCond::K_Ignore, 0},
23163 {AliasPatternCond::K_Imm, uint32_t(1)},
23164 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
23165 // (UQINCD_XPiI GPR64z:$Rdn, { 1, 1, 1, 1, 1 }, 1) - 3894
23166 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
23167 {AliasPatternCond::K_Ignore, 0},
23168 {AliasPatternCond::K_Imm, uint32_t(31)},
23169 {AliasPatternCond::K_Imm, uint32_t(1)},
23170 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
23171 // (UQINCD_XPiI GPR64z:$Rdn, sve_pred_enum:$pattern, 1) - 3899
23172 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
23173 {AliasPatternCond::K_Ignore, 0},
23174 {AliasPatternCond::K_Ignore, 0},
23175 {AliasPatternCond::K_Imm, uint32_t(1)},
23176 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
23177 // (UQINCD_ZPiI ZPR64:$Zdn, { 1, 1, 1, 1, 1 }, 1) - 3904
23178 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
23179 {AliasPatternCond::K_Ignore, 0},
23180 {AliasPatternCond::K_Imm, uint32_t(31)},
23181 {AliasPatternCond::K_Imm, uint32_t(1)},
23182 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
23183 // (UQINCD_ZPiI ZPR64:$Zdn, sve_pred_enum:$pattern, 1) - 3909
23184 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
23185 {AliasPatternCond::K_Ignore, 0},
23186 {AliasPatternCond::K_Ignore, 0},
23187 {AliasPatternCond::K_Imm, uint32_t(1)},
23188 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
23189 // (UQINCH_WPiI GPR32z:$Rdn, { 1, 1, 1, 1, 1 }, 1) - 3914
23190 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
23191 {AliasPatternCond::K_Ignore, 0},
23192 {AliasPatternCond::K_Imm, uint32_t(31)},
23193 {AliasPatternCond::K_Imm, uint32_t(1)},
23194 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
23195 // (UQINCH_WPiI GPR32z:$Rdn, sve_pred_enum:$pattern, 1) - 3919
23196 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
23197 {AliasPatternCond::K_Ignore, 0},
23198 {AliasPatternCond::K_Ignore, 0},
23199 {AliasPatternCond::K_Imm, uint32_t(1)},
23200 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
23201 // (UQINCH_XPiI GPR64z:$Rdn, { 1, 1, 1, 1, 1 }, 1) - 3924
23202 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
23203 {AliasPatternCond::K_Ignore, 0},
23204 {AliasPatternCond::K_Imm, uint32_t(31)},
23205 {AliasPatternCond::K_Imm, uint32_t(1)},
23206 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
23207 // (UQINCH_XPiI GPR64z:$Rdn, sve_pred_enum:$pattern, 1) - 3929
23208 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
23209 {AliasPatternCond::K_Ignore, 0},
23210 {AliasPatternCond::K_Ignore, 0},
23211 {AliasPatternCond::K_Imm, uint32_t(1)},
23212 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
23213 // (UQINCH_ZPiI ZPR16:$Zdn, { 1, 1, 1, 1, 1 }, 1) - 3934
23214 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
23215 {AliasPatternCond::K_Ignore, 0},
23216 {AliasPatternCond::K_Imm, uint32_t(31)},
23217 {AliasPatternCond::K_Imm, uint32_t(1)},
23218 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
23219 // (UQINCH_ZPiI ZPR16:$Zdn, sve_pred_enum:$pattern, 1) - 3939
23220 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
23221 {AliasPatternCond::K_Ignore, 0},
23222 {AliasPatternCond::K_Ignore, 0},
23223 {AliasPatternCond::K_Imm, uint32_t(1)},
23224 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
23225 // (UQINCW_WPiI GPR32z:$Rdn, { 1, 1, 1, 1, 1 }, 1) - 3944
23226 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
23227 {AliasPatternCond::K_Ignore, 0},
23228 {AliasPatternCond::K_Imm, uint32_t(31)},
23229 {AliasPatternCond::K_Imm, uint32_t(1)},
23230 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
23231 // (UQINCW_WPiI GPR32z:$Rdn, sve_pred_enum:$pattern, 1) - 3949
23232 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
23233 {AliasPatternCond::K_Ignore, 0},
23234 {AliasPatternCond::K_Ignore, 0},
23235 {AliasPatternCond::K_Imm, uint32_t(1)},
23236 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
23237 // (UQINCW_XPiI GPR64z:$Rdn, { 1, 1, 1, 1, 1 }, 1) - 3954
23238 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
23239 {AliasPatternCond::K_Ignore, 0},
23240 {AliasPatternCond::K_Imm, uint32_t(31)},
23241 {AliasPatternCond::K_Imm, uint32_t(1)},
23242 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
23243 // (UQINCW_XPiI GPR64z:$Rdn, sve_pred_enum:$pattern, 1) - 3959
23244 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
23245 {AliasPatternCond::K_Ignore, 0},
23246 {AliasPatternCond::K_Ignore, 0},
23247 {AliasPatternCond::K_Imm, uint32_t(1)},
23248 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
23249 // (UQINCW_ZPiI ZPR32:$Zdn, { 1, 1, 1, 1, 1 }, 1) - 3964
23250 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
23251 {AliasPatternCond::K_Ignore, 0},
23252 {AliasPatternCond::K_Imm, uint32_t(31)},
23253 {AliasPatternCond::K_Imm, uint32_t(1)},
23254 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
23255 // (UQINCW_ZPiI ZPR32:$Zdn, sve_pred_enum:$pattern, 1) - 3969
23256 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
23257 {AliasPatternCond::K_Ignore, 0},
23258 {AliasPatternCond::K_Ignore, 0},
23259 {AliasPatternCond::K_Imm, uint32_t(1)},
23260 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
23261 // (XPACLRI) - 3974
23262 {AliasPatternCond::K_Feature, AArch64::FeaturePAuth},
23263 };
23264
23265 static const char AsmStrings[] =
23266 /* 0 */ "cmn $\x02, $\xFF\x03\x01\0"
23267 /* 13 */ "cmn $\x02, $\x03\0"
23268 /* 24 */ "cmn $\x02, $\x03$\xFF\x04\x02\0"
23269 /* 39 */ "adds $\x01, $\x02, $\x03\0"
23270 /* 55 */ "cmn $\x02, $\x03$\xFF\x04\x03\0"
23271 /* 70 */ "mov $\x01, $\x02\0"
23272 /* 81 */ "add $\x01, $\x02, $\x03\0"
23273 /* 96 */ "tst $\x02, $\xFF\x03\x04\0"
23274 /* 109 */ "tst $\x02, $\x03\0"
23275 /* 120 */ "tst $\x02, $\x03$\xFF\x04\x02\0"
23276 /* 135 */ "ands $\x01, $\x02, $\x03\0"
23277 /* 151 */ "tst $\x02, $\xFF\x03\x05\0"
23278 /* 164 */ "movs $\xFF\x01\x06, $\xFF\x02\x07/z, $\xFF\x03\x06\0"
23279 /* 188 */ "and $\x01, $\x02, $\x03\0"
23280 /* 203 */ "mov $\xFF\x01\x06, $\xFF\x02\x07/z, $\xFF\x03\x06\0"
23281 /* 226 */ "and $\xFF\x01\x06, $\xFF\x01\x06, $\xFF\x03\x08\0"
23282 /* 247 */ "and $\xFF\x01\x09, $\xFF\x01\x09, $\xFF\x03\x0A\0"
23283 /* 268 */ "and $\xFF\x01\x0B, $\xFF\x01\x0B, $\xFF\x03\x04\0"
23284 /* 289 */ "autia1716\0"
23285 /* 299 */ "autiasp\0"
23286 /* 307 */ "autiaz\0"
23287 /* 314 */ "autib1716\0"
23288 /* 324 */ "autibsp\0"
23289 /* 332 */ "autibz\0"
23290 /* 339 */ "bics $\x01, $\x02, $\x03\0"
23291 /* 355 */ "bic $\x01, $\x02, $\x03\0"
23292 /* 370 */ "clrex\0"
23293 /* 376 */ "cntb $\x01\0"
23294 /* 384 */ "cntb $\x01, $\xFF\x02\x0E\0"
23295 /* 398 */ "cntd $\x01\0"
23296 /* 406 */ "cntd $\x01, $\xFF\x02\x0E\0"
23297 /* 420 */ "cnth $\x01\0"
23298 /* 428 */ "cnth $\x01, $\xFF\x02\x0E\0"
23299 /* 442 */ "cntw $\x01\0"
23300 /* 450 */ "cntw $\x01, $\xFF\x02\x0E\0"
23301 /* 464 */ "mov $\xFF\x01\x06, $\xFF\x03\x07/m, $\xFF\x04\x0F\0"
23302 /* 487 */ "mov $\xFF\x01\x10, $\xFF\x03\x07/m, $\xFF\x04\x11\0"
23303 /* 510 */ "mov $\xFF\x01\x09, $\xFF\x03\x07/m, $\xFF\x04\x12\0"
23304 /* 533 */ "mov $\xFF\x01\x0B, $\xFF\x03\x07/m, $\xFF\x04\x13\0"
23305 /* 556 */ "mov $\xFF\x01\x06, $\xFF\x03\x07/m, $\x04\0"
23306 /* 577 */ "mov $\xFF\x01\x10, $\xFF\x03\x07/m, $\x04\0"
23307 /* 598 */ "mov $\xFF\x01\x09, $\xFF\x03\x07/m, $\x04\0"
23308 /* 619 */ "mov $\xFF\x01\x0B, $\xFF\x03\x07/m, $\x04\0"
23309 /* 640 */ "mov $\xFF\x01\x06, $\xFF\x02\x07/z, $\xFF\x03\x0F\0"
23310 /* 663 */ "mov $\xFF\x01\x10, $\xFF\x02\x07/z, $\xFF\x03\x11\0"
23311 /* 686 */ "mov $\xFF\x01\x09, $\xFF\x02\x07/z, $\xFF\x03\x12\0"
23312 /* 709 */ "mov $\xFF\x01\x0B, $\xFF\x02\x07/z, $\xFF\x03\x13\0"
23313 /* 732 */ "cset $\x01, $\xFF\x04\x14\0"
23314 /* 746 */ "cinc $\x01, $\x02, $\xFF\x04\x14\0"
23315 /* 764 */ "csetm $\x01, $\xFF\x04\x14\0"
23316 /* 779 */ "cinv $\x01, $\x02, $\xFF\x04\x14\0"
23317 /* 797 */ "cneg $\x01, $\x02, $\xFF\x04\x14\0"
23318 /* 815 */ "dcps1\0"
23319 /* 821 */ "dcps2\0"
23320 /* 827 */ "dcps3\0"
23321 /* 833 */ "decb $\x01\0"
23322 /* 841 */ "decb $\x01, $\xFF\x03\x0E\0"
23323 /* 855 */ "decd $\x01\0"
23324 /* 863 */ "decd $\x01, $\xFF\x03\x0E\0"
23325 /* 877 */ "decd $\xFF\x01\x10\0"
23326 /* 887 */ "decd $\xFF\x01\x10, $\xFF\x03\x0E\0"
23327 /* 903 */ "dech $\x01\0"
23328 /* 911 */ "dech $\x01, $\xFF\x03\x0E\0"
23329 /* 925 */ "dech $\xFF\x01\x09\0"
23330 /* 935 */ "dech $\xFF\x01\x09, $\xFF\x03\x0E\0"
23331 /* 951 */ "decw $\x01\0"
23332 /* 959 */ "decw $\x01, $\xFF\x03\x0E\0"
23333 /* 973 */ "decw $\xFF\x01\x0B\0"
23334 /* 983 */ "decw $\xFF\x01\x0B, $\xFF\x03\x0E\0"
23335 /* 999 */ "ssbb\0"
23336 /* 1004 */ "pssbb\0"
23337 /* 1010 */ "mov $\xFF\x01\x09, $\xFF\x02\x15\0"
23338 /* 1025 */ "mov $\xFF\x01\x0B, $\xFF\x02\x16\0"
23339 /* 1040 */ "mov $\xFF\x01\x10, $\xFF\x02\x17\0"
23340 /* 1055 */ "dupm $\xFF\x01\x06, $\xFF\x02\x08\0"
23341 /* 1071 */ "dupm $\xFF\x01\x09, $\xFF\x02\x0A\0"
23342 /* 1087 */ "dupm $\xFF\x01\x0B, $\xFF\x02\x04\0"
23343 /* 1103 */ "mov $\xFF\x01\x06, $\xFF\x02\x0F\0"
23344 /* 1118 */ "mov $\xFF\x01\x10, $\xFF\x02\x11\0"
23345 /* 1133 */ "fmov $\xFF\x01\x10, #0.0\0"
23346 /* 1149 */ "mov $\xFF\x01\x09, $\xFF\x02\x12\0"
23347 /* 1164 */ "fmov $\xFF\x01\x09, #0.0\0"
23348 /* 1180 */ "mov $\xFF\x01\x0B, $\xFF\x02\x13\0"
23349 /* 1195 */ "fmov $\xFF\x01\x0B, #0.0\0"
23350 /* 1211 */ "mov $\xFF\x01\x06, $\x02\0"
23351 /* 1224 */ "mov $\xFF\x01\x10, $\x02\0"
23352 /* 1237 */ "mov $\xFF\x01\x09, $\x02\0"
23353 /* 1250 */ "mov $\xFF\x01\x0B, $\x02\0"
23354 /* 1263 */ "mov $\xFF\x01\x06, $\xFF\x02\x18\0"
23355 /* 1278 */ "mov $\xFF\x01\x06, $\xFF\x02\x06$\xFF\x03\x19\0"
23356 /* 1297 */ "mov $\xFF\x01\x10, $\xFF\x02\x1A\0"
23357 /* 1312 */ "mov $\xFF\x01\x10, $\xFF\x02\x10$\xFF\x03\x19\0"
23358 /* 1331 */ "mov $\xFF\x01\x09, $\xFF\x02\x1B\0"
23359 /* 1346 */ "mov $\xFF\x01\x09, $\xFF\x02\x09$\xFF\x03\x19\0"
23360 /* 1365 */ "mov $\xFF\x01\x1C, $\xFF\x02\x1D\0"
23361 /* 1380 */ "mov $\xFF\x01\x1C, $\xFF\x02\x1C$\xFF\x03\x19\0"
23362 /* 1399 */ "mov $\xFF\x01\x0B, $\xFF\x02\x1E\0"
23363 /* 1414 */ "mov $\xFF\x01\x0B, $\xFF\x02\x0B$\xFF\x03\x19\0"
23364 /* 1433 */ "eon $\x01, $\x02, $\x03\0"
23365 /* 1448 */ "nots $\xFF\x01\x06, $\xFF\x02\x07/z, $\xFF\x03\x06\0"
23366 /* 1472 */ "eor $\x01, $\x02, $\x03\0"
23367 /* 1487 */ "not $\xFF\x01\x06, $\xFF\x02\x07/z, $\xFF\x03\x06\0"
23368 /* 1510 */ "eor $\xFF\x01\x06, $\xFF\x01\x06, $\xFF\x03\x08\0"
23369 /* 1531 */ "eor $\xFF\x01\x09, $\xFF\x01\x09, $\xFF\x03\x0A\0"
23370 /* 1552 */ "eor $\xFF\x01\x0B, $\xFF\x01\x0B, $\xFF\x03\x04\0"
23371 /* 1573 */ "ror $\x01, $\x02, $\x04\0"
23372 /* 1588 */ "fmov $\xFF\x01\x10, $\xFF\x03\x07/m, $\xFF\x04\x1F\0"
23373 /* 1612 */ "fmov $\xFF\x01\x09, $\xFF\x03\x07/m, $\xFF\x04\x1F\0"
23374 /* 1636 */ "fmov $\xFF\x01\x0B, $\xFF\x03\x07/m, $\xFF\x04\x1F\0"
23375 /* 1660 */ "fmov $\xFF\x01\x10, $\xFF\x02\x1F\0"
23376 /* 1676 */ "fmov $\xFF\x01\x09, $\xFF\x02\x1F\0"
23377 /* 1692 */ "fmov $\xFF\x01\x0B, $\xFF\x02\x1F\0"
23378 /* 1708 */ "ld1b $\xFF\x01\x20, $\xFF\x02\x07/z, [$\xFF\x03\x10]\0"
23379 /* 1734 */ "ld1b $\xFF\x01\x21, $\xFF\x02\x07/z, [$\xFF\x03\x0B]\0"
23380 /* 1760 */ "ld1d $\xFF\x01\x20, $\xFF\x02\x07/z, [$\xFF\x03\x10]\0"
23381 /* 1786 */ "ld1h $\xFF\x01\x20, $\xFF\x02\x07/z, [$\xFF\x03\x10]\0"
23382 /* 1812 */ "ld1h $\xFF\x01\x21, $\xFF\x02\x07/z, [$\xFF\x03\x0B]\0"
23383 /* 1838 */ "ld1sb $\xFF\x01\x20, $\xFF\x02\x07/z, [$\xFF\x03\x10]\0"
23384 /* 1865 */ "ld1sb $\xFF\x01\x21, $\xFF\x02\x07/z, [$\xFF\x03\x0B]\0"
23385 /* 1892 */ "ld1sh $\xFF\x01\x20, $\xFF\x02\x07/z, [$\xFF\x03\x10]\0"
23386 /* 1919 */ "ld1sh $\xFF\x01\x21, $\xFF\x02\x07/z, [$\xFF\x03\x0B]\0"
23387 /* 1946 */ "ld1sw $\xFF\x01\x20, $\xFF\x02\x07/z, [$\xFF\x03\x10]\0"
23388 /* 1973 */ "ld1w $\xFF\x01\x20, $\xFF\x02\x07/z, [$\xFF\x03\x10]\0"
23389 /* 1999 */ "ld1w $\xFF\x01\x21, $\xFF\x02\x07/z, [$\xFF\x03\x0B]\0"
23390 /* 2025 */ "ldff1b $\xFF\x01\x20, $\xFF\x02\x07/z, [$\xFF\x03\x10]\0"
23391 /* 2053 */ "ldff1b $\xFF\x01\x21, $\xFF\x02\x07/z, [$\xFF\x03\x0B]\0"
23392 /* 2081 */ "ldff1d $\xFF\x01\x20, $\xFF\x02\x07/z, [$\xFF\x03\x10]\0"
23393 /* 2109 */ "ldff1h $\xFF\x01\x20, $\xFF\x02\x07/z, [$\xFF\x03\x10]\0"
23394 /* 2137 */ "ldff1h $\xFF\x01\x21, $\xFF\x02\x07/z, [$\xFF\x03\x0B]\0"
23395 /* 2165 */ "ldff1sb $\xFF\x01\x20, $\xFF\x02\x07/z, [$\xFF\x03\x10]\0"
23396 /* 2194 */ "ldff1sb $\xFF\x01\x21, $\xFF\x02\x07/z, [$\xFF\x03\x0B]\0"
23397 /* 2223 */ "ldff1sh $\xFF\x01\x20, $\xFF\x02\x07/z, [$\xFF\x03\x10]\0"
23398 /* 2252 */ "ldff1sh $\xFF\x01\x21, $\xFF\x02\x07/z, [$\xFF\x03\x0B]\0"
23399 /* 2281 */ "ldff1sw $\xFF\x01\x20, $\xFF\x02\x07/z, [$\xFF\x03\x10]\0"
23400 /* 2310 */ "ldff1w $\xFF\x01\x20, $\xFF\x02\x07/z, [$\xFF\x03\x10]\0"
23401 /* 2338 */ "ldff1w $\xFF\x01\x21, $\xFF\x02\x07/z, [$\xFF\x03\x0B]\0"
23402 /* 2366 */ "nop\0"
23403 /* 2370 */ "yield\0"
23404 /* 2376 */ "wfe\0"
23405 /* 2380 */ "wfi\0"
23406 /* 2384 */ "sev\0"
23407 /* 2388 */ "sevl\0"
23408 /* 2393 */ "dgh\0"
23409 /* 2397 */ "esb\0"
23410 /* 2401 */ "csdb\0"
23411 /* 2406 */ "bti\0"
23412 /* 2410 */ "bti $\xFF\x01\x22\0"
23413 /* 2419 */ "psb $\xFF\x01\x23\0"
23414 /* 2428 */ "incb $\x01\0"
23415 /* 2436 */ "incb $\x01, $\xFF\x03\x0E\0"
23416 /* 2450 */ "incd $\x01\0"
23417 /* 2458 */ "incd $\x01, $\xFF\x03\x0E\0"
23418 /* 2472 */ "incd $\xFF\x01\x10\0"
23419 /* 2482 */ "incd $\xFF\x01\x10, $\xFF\x03\x0E\0"
23420 /* 2498 */ "inch $\x01\0"
23421 /* 2506 */ "inch $\x01, $\xFF\x03\x0E\0"
23422 /* 2520 */ "inch $\xFF\x01\x09\0"
23423 /* 2530 */ "inch $\xFF\x01\x09, $\xFF\x03\x0E\0"
23424 /* 2546 */ "incw $\x01\0"
23425 /* 2554 */ "incw $\x01, $\xFF\x03\x0E\0"
23426 /* 2568 */ "incw $\xFF\x01\x0B\0"
23427 /* 2578 */ "incw $\xFF\x01\x0B, $\xFF\x03\x0E\0"
23428 /* 2594 */ "mov $\xFF\x01\x0C.h$\xFF\x03\x19, $\x04\0"
23429 /* 2613 */ "mov $\xFF\x01\x0C.h$\xFF\x03\x19, $\xFF\x04\x0C.h$\xFF\x05\x19\0"
23430 /* 2640 */ "mov $\xFF\x01\x0C.s$\xFF\x03\x19, $\x04\0"
23431 /* 2659 */ "mov $\xFF\x01\x0C.s$\xFF\x03\x19, $\xFF\x04\x0C.s$\xFF\x05\x19\0"
23432 /* 2686 */ "mov $\xFF\x01\x0C.d$\xFF\x03\x19, $\x04\0"
23433 /* 2705 */ "mov $\xFF\x01\x0C.d$\xFF\x03\x19, $\xFF\x04\x0C.d$\xFF\x05\x19\0"
23434 /* 2732 */ "mov $\xFF\x01\x0C.b$\xFF\x03\x19, $\x04\0"
23435 /* 2751 */ "mov $\xFF\x01\x0C.b$\xFF\x03\x19, $\xFF\x04\x0C.b$\xFF\x05\x19\0"
23436 /* 2778 */ "irg $\x01, $\x02\0"
23437 /* 2789 */ "isb\0"
23438 /* 2793 */ "ld1b $\xFF\x01\x20, $\xFF\x02\x07/z, [$\x03]\0"
23439 /* 2817 */ "ld1b $\xFF\x01\x24, $\xFF\x02\x07/z, [$\x03]\0"
23440 /* 2841 */ "ld1b $\xFF\x01\x25, $\xFF\x02\x07/z, [$\x03]\0"
23441 /* 2865 */ "ld1b $\xFF\x01\x21, $\xFF\x02\x07/z, [$\x03]\0"
23442 /* 2889 */ "ld1d $\xFF\x01\x20, $\xFF\x02\x07/z, [$\x03]\0"
23443 /* 2913 */ "ld1 $\xFF\x02\x26, [$\x01], #64\0"
23444 /* 2933 */ "ld1 $\xFF\x02\x27, [$\x01], #32\0"
23445 /* 2953 */ "ld1 $\xFF\x02\x28, [$\x01], #64\0"
23446 /* 2973 */ "ld1 $\xFF\x02\x29, [$\x01], #32\0"
23447 /* 2993 */ "ld1 $\xFF\x02\x2A, [$\x01], #32\0"
23448 /* 3013 */ "ld1 $\xFF\x02\x2B, [$\x01], #64\0"
23449 /* 3033 */ "ld1 $\xFF\x02\x2C, [$\x01], #32\0"
23450 /* 3053 */ "ld1 $\xFF\x02\x2D, [$\x01], #64\0"
23451 /* 3073 */ "ld1h $\xFF\x01\x20, $\xFF\x02\x07/z, [$\x03]\0"
23452 /* 3097 */ "ld1h $\xFF\x01\x24, $\xFF\x02\x07/z, [$\x03]\0"
23453 /* 3121 */ "ld1h $\xFF\x01\x21, $\xFF\x02\x07/z, [$\x03]\0"
23454 /* 3145 */ "ld1 $\xFF\x02\x26, [$\x01], #16\0"
23455 /* 3165 */ "ld1 $\xFF\x02\x27, [$\x01], #8\0"
23456 /* 3184 */ "ld1 $\xFF\x02\x28, [$\x01], #16\0"
23457 /* 3204 */ "ld1 $\xFF\x02\x29, [$\x01], #8\0"
23458 /* 3223 */ "ld1 $\xFF\x02\x2A, [$\x01], #8\0"
23459 /* 3242 */ "ld1 $\xFF\x02\x2B, [$\x01], #16\0"
23460 /* 3262 */ "ld1 $\xFF\x02\x2C, [$\x01], #8\0"
23461 /* 3281 */ "ld1 $\xFF\x02\x2D, [$\x01], #16\0"
23462 /* 3301 */ "ld1rb $\xFF\x01\x20, $\xFF\x02\x07/z, [$\x03]\0"
23463 /* 3326 */ "ld1rb $\xFF\x01\x24, $\xFF\x02\x07/z, [$\x03]\0"
23464 /* 3351 */ "ld1rb $\xFF\x01\x25, $\xFF\x02\x07/z, [$\x03]\0"
23465 /* 3376 */ "ld1rb $\xFF\x01\x21, $\xFF\x02\x07/z, [$\x03]\0"
23466 /* 3401 */ "ld1rd $\xFF\x01\x20, $\xFF\x02\x07/z, [$\x03]\0"
23467 /* 3426 */ "ld1rh $\xFF\x01\x20, $\xFF\x02\x07/z, [$\x03]\0"
23468 /* 3451 */ "ld1rh $\xFF\x01\x24, $\xFF\x02\x07/z, [$\x03]\0"
23469 /* 3476 */ "ld1rh $\xFF\x01\x21, $\xFF\x02\x07/z, [$\x03]\0"
23470 /* 3501 */ "ld1rob $\xFF\x01\x25, $\xFF\x02\x07/z, [$\x03]\0"
23471 /* 3527 */ "ld1rod $\xFF\x01\x20, $\xFF\x02\x07/z, [$\x03]\0"
23472 /* 3553 */ "ld1roh $\xFF\x01\x24, $\xFF\x02\x07/z, [$\x03]\0"
23473 /* 3579 */ "ld1row $\xFF\x01\x21, $\xFF\x02\x07/z, [$\x03]\0"
23474 /* 3605 */ "ld1rqb $\xFF\x01\x25, $\xFF\x02\x07/z, [$\x03]\0"
23475 /* 3631 */ "ld1rqd $\xFF\x01\x20, $\xFF\x02\x07/z, [$\x03]\0"
23476 /* 3657 */ "ld1rqh $\xFF\x01\x24, $\xFF\x02\x07/z, [$\x03]\0"
23477 /* 3683 */ "ld1rqw $\xFF\x01\x21, $\xFF\x02\x07/z, [$\x03]\0"
23478 /* 3709 */ "ld1rsb $\xFF\x01\x20, $\xFF\x02\x07/z, [$\x03]\0"
23479 /* 3735 */ "ld1rsb $\xFF\x01\x24, $\xFF\x02\x07/z, [$\x03]\0"
23480 /* 3761 */ "ld1rsb $\xFF\x01\x21, $\xFF\x02\x07/z, [$\x03]\0"
23481 /* 3787 */ "ld1rsh $\xFF\x01\x20, $\xFF\x02\x07/z, [$\x03]\0"
23482 /* 3813 */ "ld1rsh $\xFF\x01\x21, $\xFF\x02\x07/z, [$\x03]\0"
23483 /* 3839 */ "ld1rsw $\xFF\x01\x20, $\xFF\x02\x07/z, [$\x03]\0"
23484 /* 3865 */ "ld1rw $\xFF\x01\x20, $\xFF\x02\x07/z, [$\x03]\0"
23485 /* 3890 */ "ld1rw $\xFF\x01\x21, $\xFF\x02\x07/z, [$\x03]\0"
23486 /* 3915 */ "ld1r $\xFF\x02\x26, [$\x01], #1\0"
23487 /* 3935 */ "ld1r $\xFF\x02\x27, [$\x01], #8\0"
23488 /* 3955 */ "ld1r $\xFF\x02\x28, [$\x01], #8\0"
23489 /* 3975 */ "ld1r $\xFF\x02\x29, [$\x01], #4\0"
23490 /* 3995 */ "ld1r $\xFF\x02\x2A, [$\x01], #2\0"
23491 /* 4015 */ "ld1r $\xFF\x02\x2B, [$\x01], #4\0"
23492 /* 4035 */ "ld1r $\xFF\x02\x2C, [$\x01], #1\0"
23493 /* 4055 */ "ld1r $\xFF\x02\x2D, [$\x01], #2\0"
23494 /* 4075 */ "ld1sb $\xFF\x01\x20, $\xFF\x02\x07/z, [$\x03]\0"
23495 /* 4100 */ "ld1sb $\xFF\x01\x24, $\xFF\x02\x07/z, [$\x03]\0"
23496 /* 4125 */ "ld1sb $\xFF\x01\x21, $\xFF\x02\x07/z, [$\x03]\0"
23497 /* 4150 */ "ld1sh $\xFF\x01\x20, $\xFF\x02\x07/z, [$\x03]\0"
23498 /* 4175 */ "ld1sh $\xFF\x01\x21, $\xFF\x02\x07/z, [$\x03]\0"
23499 /* 4200 */ "ld1sw $\xFF\x01\x20, $\xFF\x02\x07/z, [$\x03]\0"
23500 /* 4225 */ "ld1 $\xFF\x02\x26, [$\x01], #48\0"
23501 /* 4245 */ "ld1 $\xFF\x02\x27, [$\x01], #24\0"
23502 /* 4265 */ "ld1 $\xFF\x02\x28, [$\x01], #48\0"
23503 /* 4285 */ "ld1 $\xFF\x02\x29, [$\x01], #24\0"
23504 /* 4305 */ "ld1 $\xFF\x02\x2A, [$\x01], #24\0"
23505 /* 4325 */ "ld1 $\xFF\x02\x2B, [$\x01], #48\0"
23506 /* 4345 */ "ld1 $\xFF\x02\x2C, [$\x01], #24\0"
23507 /* 4365 */ "ld1 $\xFF\x02\x2D, [$\x01], #48\0"
23508 /* 4385 */ "ld1 $\xFF\x02\x26, [$\x01], #32\0"
23509 /* 4405 */ "ld1 $\xFF\x02\x27, [$\x01], #16\0"
23510 /* 4425 */ "ld1 $\xFF\x02\x28, [$\x01], #32\0"
23511 /* 4445 */ "ld1 $\xFF\x02\x29, [$\x01], #16\0"
23512 /* 4465 */ "ld1 $\xFF\x02\x2A, [$\x01], #16\0"
23513 /* 4485 */ "ld1 $\xFF\x02\x2B, [$\x01], #32\0"
23514 /* 4505 */ "ld1 $\xFF\x02\x2C, [$\x01], #16\0"
23515 /* 4525 */ "ld1 $\xFF\x02\x2D, [$\x01], #32\0"
23516 /* 4545 */ "ld1w $\xFF\x01\x20, $\xFF\x02\x07/z, [$\x03]\0"
23517 /* 4569 */ "ld1w $\xFF\x01\x21, $\xFF\x02\x07/z, [$\x03]\0"
23518 /* 4593 */ "ld1 $\xFF\x02\x2E$\xFF\x04\x19, [$\x01], #2\0"
23519 /* 4616 */ "ld1 $\xFF\x02\x2F$\xFF\x04\x19, [$\x01], #4\0"
23520 /* 4639 */ "ld1 $\xFF\x02\x30$\xFF\x04\x19, [$\x01], #8\0"
23521 /* 4662 */ "ld1 $\xFF\x02\x31$\xFF\x04\x19, [$\x01], #1\0"
23522 /* 4685 */ "ld2b $\xFF\x01\x25, $\xFF\x02\x07/z, [$\x03]\0"
23523 /* 4709 */ "ld2d $\xFF\x01\x20, $\xFF\x02\x07/z, [$\x03]\0"
23524 /* 4733 */ "ld2h $\xFF\x01\x24, $\xFF\x02\x07/z, [$\x03]\0"
23525 /* 4757 */ "ld2r $\xFF\x02\x26, [$\x01], #2\0"
23526 /* 4777 */ "ld2r $\xFF\x02\x27, [$\x01], #16\0"
23527 /* 4798 */ "ld2r $\xFF\x02\x28, [$\x01], #16\0"
23528 /* 4819 */ "ld2r $\xFF\x02\x29, [$\x01], #8\0"
23529 /* 4839 */ "ld2r $\xFF\x02\x2A, [$\x01], #4\0"
23530 /* 4859 */ "ld2r $\xFF\x02\x2B, [$\x01], #8\0"
23531 /* 4879 */ "ld2r $\xFF\x02\x2C, [$\x01], #2\0"
23532 /* 4899 */ "ld2r $\xFF\x02\x2D, [$\x01], #4\0"
23533 /* 4919 */ "ld2 $\xFF\x02\x26, [$\x01], #32\0"
23534 /* 4939 */ "ld2 $\xFF\x02\x28, [$\x01], #32\0"
23535 /* 4959 */ "ld2 $\xFF\x02\x29, [$\x01], #16\0"
23536 /* 4979 */ "ld2 $\xFF\x02\x2A, [$\x01], #16\0"
23537 /* 4999 */ "ld2 $\xFF\x02\x2B, [$\x01], #32\0"
23538 /* 5019 */ "ld2 $\xFF\x02\x2C, [$\x01], #16\0"
23539 /* 5039 */ "ld2 $\xFF\x02\x2D, [$\x01], #32\0"
23540 /* 5059 */ "ld2w $\xFF\x01\x21, $\xFF\x02\x07/z, [$\x03]\0"
23541 /* 5083 */ "ld2 $\xFF\x02\x2E$\xFF\x04\x19, [$\x01], #4\0"
23542 /* 5106 */ "ld2 $\xFF\x02\x2F$\xFF\x04\x19, [$\x01], #8\0"
23543 /* 5129 */ "ld2 $\xFF\x02\x30$\xFF\x04\x19, [$\x01], #16\0"
23544 /* 5153 */ "ld2 $\xFF\x02\x31$\xFF\x04\x19, [$\x01], #2\0"
23545 /* 5176 */ "ld3b $\xFF\x01\x25, $\xFF\x02\x07/z, [$\x03]\0"
23546 /* 5200 */ "ld3d $\xFF\x01\x20, $\xFF\x02\x07/z, [$\x03]\0"
23547 /* 5224 */ "ld3h $\xFF\x01\x24, $\xFF\x02\x07/z, [$\x03]\0"
23548 /* 5248 */ "ld3r $\xFF\x02\x26, [$\x01], #3\0"
23549 /* 5268 */ "ld3r $\xFF\x02\x27, [$\x01], #24\0"
23550 /* 5289 */ "ld3r $\xFF\x02\x28, [$\x01], #24\0"
23551 /* 5310 */ "ld3r $\xFF\x02\x29, [$\x01], #12\0"
23552 /* 5331 */ "ld3r $\xFF\x02\x2A, [$\x01], #6\0"
23553 /* 5351 */ "ld3r $\xFF\x02\x2B, [$\x01], #12\0"
23554 /* 5372 */ "ld3r $\xFF\x02\x2C, [$\x01], #3\0"
23555 /* 5392 */ "ld3r $\xFF\x02\x2D, [$\x01], #6\0"
23556 /* 5412 */ "ld3 $\xFF\x02\x26, [$\x01], #48\0"
23557 /* 5432 */ "ld3 $\xFF\x02\x28, [$\x01], #48\0"
23558 /* 5452 */ "ld3 $\xFF\x02\x29, [$\x01], #24\0"
23559 /* 5472 */ "ld3 $\xFF\x02\x2A, [$\x01], #24\0"
23560 /* 5492 */ "ld3 $\xFF\x02\x2B, [$\x01], #48\0"
23561 /* 5512 */ "ld3 $\xFF\x02\x2C, [$\x01], #24\0"
23562 /* 5532 */ "ld3 $\xFF\x02\x2D, [$\x01], #48\0"
23563 /* 5552 */ "ld3w $\xFF\x01\x21, $\xFF\x02\x07/z, [$\x03]\0"
23564 /* 5576 */ "ld3 $\xFF\x02\x2E$\xFF\x04\x19, [$\x01], #6\0"
23565 /* 5599 */ "ld3 $\xFF\x02\x2F$\xFF\x04\x19, [$\x01], #12\0"
23566 /* 5623 */ "ld3 $\xFF\x02\x30$\xFF\x04\x19, [$\x01], #24\0"
23567 /* 5647 */ "ld3 $\xFF\x02\x31$\xFF\x04\x19, [$\x01], #3\0"
23568 /* 5670 */ "ld4b $\xFF\x01\x25, $\xFF\x02\x07/z, [$\x03]\0"
23569 /* 5694 */ "ld4d $\xFF\x01\x20, $\xFF\x02\x07/z, [$\x03]\0"
23570 /* 5718 */ "ld4 $\xFF\x02\x26, [$\x01], #64\0"
23571 /* 5738 */ "ld4 $\xFF\x02\x28, [$\x01], #64\0"
23572 /* 5758 */ "ld4 $\xFF\x02\x29, [$\x01], #32\0"
23573 /* 5778 */ "ld4 $\xFF\x02\x2A, [$\x01], #32\0"
23574 /* 5798 */ "ld4 $\xFF\x02\x2B, [$\x01], #64\0"
23575 /* 5818 */ "ld4 $\xFF\x02\x2C, [$\x01], #32\0"
23576 /* 5838 */ "ld4 $\xFF\x02\x2D, [$\x01], #64\0"
23577 /* 5858 */ "ld4h $\xFF\x01\x24, $\xFF\x02\x07/z, [$\x03]\0"
23578 /* 5882 */ "ld4r $\xFF\x02\x26, [$\x01], #4\0"
23579 /* 5902 */ "ld4r $\xFF\x02\x27, [$\x01], #32\0"
23580 /* 5923 */ "ld4r $\xFF\x02\x28, [$\x01], #32\0"
23581 /* 5944 */ "ld4r $\xFF\x02\x29, [$\x01], #16\0"
23582 /* 5965 */ "ld4r $\xFF\x02\x2A, [$\x01], #8\0"
23583 /* 5985 */ "ld4r $\xFF\x02\x2B, [$\x01], #16\0"
23584 /* 6006 */ "ld4r $\xFF\x02\x2C, [$\x01], #4\0"
23585 /* 6026 */ "ld4r $\xFF\x02\x2D, [$\x01], #8\0"
23586 /* 6046 */ "ld4w $\xFF\x01\x21, $\xFF\x02\x07/z, [$\x03]\0"
23587 /* 6070 */ "ld4 $\xFF\x02\x2E$\xFF\x04\x19, [$\x01], #8\0"
23588 /* 6093 */ "ld4 $\xFF\x02\x2F$\xFF\x04\x19, [$\x01], #16\0"
23589 /* 6117 */ "ld4 $\xFF\x02\x30$\xFF\x04\x19, [$\x01], #32\0"
23590 /* 6141 */ "ld4 $\xFF\x02\x31$\xFF\x04\x19, [$\x01], #4\0"
23591 /* 6164 */ "staddb $\x02, [$\x03]\0"
23592 /* 6180 */ "staddh $\x02, [$\x03]\0"
23593 /* 6196 */ "staddlb $\x02, [$\x03]\0"
23594 /* 6213 */ "staddlh $\x02, [$\x03]\0"
23595 /* 6230 */ "staddl $\x02, [$\x03]\0"
23596 /* 6246 */ "stadd $\x02, [$\x03]\0"
23597 /* 6261 */ "ldapurb $\x01, [$\x02]\0"
23598 /* 6278 */ "ldapurh $\x01, [$\x02]\0"
23599 /* 6295 */ "ldapursb $\x01, [$\x02]\0"
23600 /* 6313 */ "ldapursh $\x01, [$\x02]\0"
23601 /* 6331 */ "ldapursw $\x01, [$\x02]\0"
23602 /* 6349 */ "ldapur $\x01, [$\x02]\0"
23603 /* 6365 */ "stclrb $\x02, [$\x03]\0"
23604 /* 6381 */ "stclrh $\x02, [$\x03]\0"
23605 /* 6397 */ "stclrlb $\x02, [$\x03]\0"
23606 /* 6414 */ "stclrlh $\x02, [$\x03]\0"
23607 /* 6431 */ "stclrl $\x02, [$\x03]\0"
23608 /* 6447 */ "stclr $\x02, [$\x03]\0"
23609 /* 6462 */ "steorb $\x02, [$\x03]\0"
23610 /* 6478 */ "steorh $\x02, [$\x03]\0"
23611 /* 6494 */ "steorlb $\x02, [$\x03]\0"
23612 /* 6511 */ "steorlh $\x02, [$\x03]\0"
23613 /* 6528 */ "steorl $\x02, [$\x03]\0"
23614 /* 6544 */ "steor $\x02, [$\x03]\0"
23615 /* 6559 */ "ldff1b $\xFF\x01\x20, $\xFF\x02\x07/z, [$\x03]\0"
23616 /* 6585 */ "ldff1b $\xFF\x01\x24, $\xFF\x02\x07/z, [$\x03]\0"
23617 /* 6611 */ "ldff1b $\xFF\x01\x25, $\xFF\x02\x07/z, [$\x03]\0"
23618 /* 6637 */ "ldff1b $\xFF\x01\x21, $\xFF\x02\x07/z, [$\x03]\0"
23619 /* 6663 */ "ldff1d $\xFF\x01\x20, $\xFF\x02\x07/z, [$\x03]\0"
23620 /* 6689 */ "ldff1h $\xFF\x01\x20, $\xFF\x02\x07/z, [$\x03]\0"
23621 /* 6715 */ "ldff1h $\xFF\x01\x24, $\xFF\x02\x07/z, [$\x03]\0"
23622 /* 6741 */ "ldff1h $\xFF\x01\x21, $\xFF\x02\x07/z, [$\x03]\0"
23623 /* 6767 */ "ldff1sb $\xFF\x01\x20, $\xFF\x02\x07/z, [$\x03]\0"
23624 /* 6794 */ "ldff1sb $\xFF\x01\x24, $\xFF\x02\x07/z, [$\x03]\0"
23625 /* 6821 */ "ldff1sb $\xFF\x01\x21, $\xFF\x02\x07/z, [$\x03]\0"
23626 /* 6848 */ "ldff1sh $\xFF\x01\x20, $\xFF\x02\x07/z, [$\x03]\0"
23627 /* 6875 */ "ldff1sh $\xFF\x01\x21, $\xFF\x02\x07/z, [$\x03]\0"
23628 /* 6902 */ "ldff1sw $\xFF\x01\x20, $\xFF\x02\x07/z, [$\x03]\0"
23629 /* 6929 */ "ldff1w $\xFF\x01\x20, $\xFF\x02\x07/z, [$\x03]\0"
23630 /* 6955 */ "ldff1w $\xFF\x01\x21, $\xFF\x02\x07/z, [$\x03]\0"
23631 /* 6981 */ "ldg $\x01, [$\x03]\0"
23632 /* 6994 */ "ldnf1b $\xFF\x01\x20, $\xFF\x02\x07/z, [$\x03]\0"
23633 /* 7020 */ "ldnf1b $\xFF\x01\x24, $\xFF\x02\x07/z, [$\x03]\0"
23634 /* 7046 */ "ldnf1b $\xFF\x01\x25, $\xFF\x02\x07/z, [$\x03]\0"
23635 /* 7072 */ "ldnf1b $\xFF\x01\x21, $\xFF\x02\x07/z, [$\x03]\0"
23636 /* 7098 */ "ldnf1d $\xFF\x01\x20, $\xFF\x02\x07/z, [$\x03]\0"
23637 /* 7124 */ "ldnf1h $\xFF\x01\x20, $\xFF\x02\x07/z, [$\x03]\0"
23638 /* 7150 */ "ldnf1h $\xFF\x01\x24, $\xFF\x02\x07/z, [$\x03]\0"
23639 /* 7176 */ "ldnf1h $\xFF\x01\x21, $\xFF\x02\x07/z, [$\x03]\0"
23640 /* 7202 */ "ldnf1sb $\xFF\x01\x20, $\xFF\x02\x07/z, [$\x03]\0"
23641 /* 7229 */ "ldnf1sb $\xFF\x01\x24, $\xFF\x02\x07/z, [$\x03]\0"
23642 /* 7256 */ "ldnf1sb $\xFF\x01\x21, $\xFF\x02\x07/z, [$\x03]\0"
23643 /* 7283 */ "ldnf1sh $\xFF\x01\x20, $\xFF\x02\x07/z, [$\x03]\0"
23644 /* 7310 */ "ldnf1sh $\xFF\x01\x21, $\xFF\x02\x07/z, [$\x03]\0"
23645 /* 7337 */ "ldnf1sw $\xFF\x01\x20, $\xFF\x02\x07/z, [$\x03]\0"
23646 /* 7364 */ "ldnf1w $\xFF\x01\x20, $\xFF\x02\x07/z, [$\x03]\0"
23647 /* 7390 */ "ldnf1w $\xFF\x01\x21, $\xFF\x02\x07/z, [$\x03]\0"
23648 /* 7416 */ "ldnp $\x01, $\x02, [$\x03]\0"
23649 /* 7434 */ "ldnt1b $\xFF\x01\x25, $\xFF\x02\x07/z, [$\x03]\0"
23650 /* 7460 */ "ldnt1b $\xFF\x01\x20, $\xFF\x02\x07/z, [$\xFF\x03\x10]\0"
23651 /* 7488 */ "ldnt1b $\xFF\x01\x21, $\xFF\x02\x07/z, [$\xFF\x03\x0B]\0"
23652 /* 7516 */ "ldnt1d $\xFF\x01\x20, $\xFF\x02\x07/z, [$\x03]\0"
23653 /* 7542 */ "ldnt1d $\xFF\x01\x20, $\xFF\x02\x07/z, [$\xFF\x03\x10]\0"
23654 /* 7570 */ "ldnt1h $\xFF\x01\x24, $\xFF\x02\x07/z, [$\x03]\0"
23655 /* 7596 */ "ldnt1h $\xFF\x01\x20, $\xFF\x02\x07/z, [$\xFF\x03\x10]\0"
23656 /* 7624 */ "ldnt1h $\xFF\x01\x21, $\xFF\x02\x07/z, [$\xFF\x03\x0B]\0"
23657 /* 7652 */ "ldnt1sb $\xFF\x01\x20, $\xFF\x02\x07/z, [$\xFF\x03\x10]\0"
23658 /* 7681 */ "ldnt1sb $\xFF\x01\x21, $\xFF\x02\x07/z, [$\xFF\x03\x0B]\0"
23659 /* 7710 */ "ldnt1sh $\xFF\x01\x20, $\xFF\x02\x07/z, [$\xFF\x03\x10]\0"
23660 /* 7739 */ "ldnt1sh $\xFF\x01\x21, $\xFF\x02\x07/z, [$\xFF\x03\x0B]\0"
23661 /* 7768 */ "ldnt1sw $\xFF\x01\x20, $\xFF\x02\x07/z, [$\xFF\x03\x10]\0"
23662 /* 7797 */ "ldnt1w $\xFF\x01\x21, $\xFF\x02\x07/z, [$\x03]\0"
23663 /* 7823 */ "ldnt1w $\xFF\x01\x20, $\xFF\x02\x07/z, [$\xFF\x03\x10]\0"
23664 /* 7851 */ "ldnt1w $\xFF\x01\x21, $\xFF\x02\x07/z, [$\xFF\x03\x0B]\0"
23665 /* 7879 */ "ldp $\x01, $\x02, [$\x03]\0"
23666 /* 7896 */ "ldpsw $\x01, $\x02, [$\x03]\0"
23667 /* 7915 */ "ldraa $\x01, [$\x02]\0"
23668 /* 7930 */ "ldrab $\x01, [$\x02]\0"
23669 /* 7945 */ "ldrb $\x01, [$\x02, $\x03]\0"
23670 /* 7963 */ "ldrb $\x01, [$\x02]\0"
23671 /* 7977 */ "ldr $\x01, [$\x02, $\x03]\0"
23672 /* 7994 */ "ldr $\x01, [$\x02]\0"
23673 /* 8007 */ "ldrh $\x01, [$\x02, $\x03]\0"
23674 /* 8025 */ "ldrh $\x01, [$\x02]\0"
23675 /* 8039 */ "ldrsb $\x01, [$\x02, $\x03]\0"
23676 /* 8058 */ "ldrsb $\x01, [$\x02]\0"
23677 /* 8073 */ "ldrsh $\x01, [$\x02, $\x03]\0"
23678 /* 8092 */ "ldrsh $\x01, [$\x02]\0"
23679 /* 8107 */ "ldrsw $\x01, [$\x02, $\x03]\0"
23680 /* 8126 */ "ldrsw $\x01, [$\x02]\0"
23681 /* 8141 */ "ldr $\xFF\x01\x07, [$\x02]\0"
23682 /* 8156 */ "stsetb $\x02, [$\x03]\0"
23683 /* 8172 */ "stseth $\x02, [$\x03]\0"
23684 /* 8188 */ "stsetlb $\x02, [$\x03]\0"
23685 /* 8205 */ "stsetlh $\x02, [$\x03]\0"
23686 /* 8222 */ "stsetl $\x02, [$\x03]\0"
23687 /* 8238 */ "stset $\x02, [$\x03]\0"
23688 /* 8253 */ "stsmaxb $\x02, [$\x03]\0"
23689 /* 8270 */ "stsmaxh $\x02, [$\x03]\0"
23690 /* 8287 */ "stsmaxlb $\x02, [$\x03]\0"
23691 /* 8305 */ "stsmaxlh $\x02, [$\x03]\0"
23692 /* 8323 */ "stsmaxl $\x02, [$\x03]\0"
23693 /* 8340 */ "stsmax $\x02, [$\x03]\0"
23694 /* 8356 */ "stsminb $\x02, [$\x03]\0"
23695 /* 8373 */ "stsminh $\x02, [$\x03]\0"
23696 /* 8390 */ "stsminlb $\x02, [$\x03]\0"
23697 /* 8408 */ "stsminlh $\x02, [$\x03]\0"
23698 /* 8426 */ "stsminl $\x02, [$\x03]\0"
23699 /* 8443 */ "stsmin $\x02, [$\x03]\0"
23700 /* 8459 */ "ldtrb $\x01, [$\x02]\0"
23701 /* 8474 */ "ldtrh $\x01, [$\x02]\0"
23702 /* 8489 */ "ldtrsb $\x01, [$\x02]\0"
23703 /* 8505 */ "ldtrsh $\x01, [$\x02]\0"
23704 /* 8521 */ "ldtrsw $\x01, [$\x02]\0"
23705 /* 8537 */ "ldtr $\x01, [$\x02]\0"
23706 /* 8551 */ "stumaxb $\x02, [$\x03]\0"
23707 /* 8568 */ "stumaxh $\x02, [$\x03]\0"
23708 /* 8585 */ "stumaxlb $\x02, [$\x03]\0"
23709 /* 8603 */ "stumaxlh $\x02, [$\x03]\0"
23710 /* 8621 */ "stumaxl $\x02, [$\x03]\0"
23711 /* 8638 */ "stumax $\x02, [$\x03]\0"
23712 /* 8654 */ "stuminb $\x02, [$\x03]\0"
23713 /* 8671 */ "stuminh $\x02, [$\x03]\0"
23714 /* 8688 */ "stuminlb $\x02, [$\x03]\0"
23715 /* 8706 */ "stuminlh $\x02, [$\x03]\0"
23716 /* 8724 */ "stuminl $\x02, [$\x03]\0"
23717 /* 8741 */ "stumin $\x02, [$\x03]\0"
23718 /* 8757 */ "ldurb $\x01, [$\x02]\0"
23719 /* 8772 */ "ldur $\x01, [$\x02]\0"
23720 /* 8786 */ "ldurh $\x01, [$\x02]\0"
23721 /* 8801 */ "ldursb $\x01, [$\x02]\0"
23722 /* 8817 */ "ldursh $\x01, [$\x02]\0"
23723 /* 8833 */ "ldursw $\x01, [$\x02]\0"
23724 /* 8849 */ "mul $\x01, $\x02, $\x03\0"
23725 /* 8864 */ "mneg $\x01, $\x02, $\x03\0"
23726 /* 8880 */ "mvn $\xFF\x01\x0C.16b, $\xFF\x02\x0C.16b\0"
23727 /* 8903 */ "mvn $\xFF\x01\x0C.8b, $\xFF\x02\x0C.8b\0"
23728 /* 8924 */ "mvn $\x01, $\x03\0"
23729 /* 8935 */ "mvn $\x01, $\x03$\xFF\x04\x02\0"
23730 /* 8950 */ "orn $\x01, $\x02, $\x03\0"
23731 /* 8965 */ "movs $\xFF\x01\x06, $\xFF\x02\x06\0"
23732 /* 8981 */ "mov $\x01, $\x03\0"
23733 /* 8992 */ "orr $\x01, $\x02, $\x03\0"
23734 /* 9007 */ "mov $\xFF\x01\x06, $\xFF\x02\x06\0"
23735 /* 9022 */ "orr $\xFF\x01\x06, $\xFF\x01\x06, $\xFF\x03\x08\0"
23736 /* 9043 */ "orr $\xFF\x01\x09, $\xFF\x01\x09, $\xFF\x03\x0A\0"
23737 /* 9064 */ "orr $\xFF\x01\x0B, $\xFF\x01\x0B, $\xFF\x03\x04\0"
23738 /* 9085 */ "mov $\xFF\x01\x10, $\xFF\x02\x10\0"
23739 /* 9100 */ "mov $\xFF\x01\x0C.16b, $\xFF\x02\x0C.16b\0"
23740 /* 9123 */ "mov $\xFF\x01\x0C.8b, $\xFF\x02\x0C.8b\0"
23741 /* 9144 */ "pacia1716\0"
23742 /* 9154 */ "paciasp\0"
23743 /* 9162 */ "paciaz\0"
23744 /* 9169 */ "pacib1716\0"
23745 /* 9179 */ "pacibsp\0"
23746 /* 9187 */ "pacibz\0"
23747 /* 9194 */ "prfb $\xFF\x01\x33, $\xFF\x02\x07, [$\xFF\x03\x10]\0"
23748 /* 9218 */ "prfb $\xFF\x01\x33, $\xFF\x02\x07, [$\x03]\0"
23749 /* 9240 */ "prfb $\xFF\x01\x33, $\xFF\x02\x07, [$\xFF\x03\x0B]\0"
23750 /* 9264 */ "prfd $\xFF\x01\x33, $\xFF\x02\x07, [$\xFF\x03\x10]\0"
23751 /* 9288 */ "prfd $\xFF\x01\x33, $\xFF\x02\x07, [$\x03]\0"
23752 /* 9310 */ "prfd $\xFF\x01\x33, $\xFF\x02\x07, [$\xFF\x03\x0B]\0"
23753 /* 9334 */ "prfh $\xFF\x01\x33, $\xFF\x02\x07, [$\xFF\x03\x10]\0"
23754 /* 9358 */ "prfh $\xFF\x01\x33, $\xFF\x02\x07, [$\x03]\0"
23755 /* 9380 */ "prfh $\xFF\x01\x33, $\xFF\x02\x07, [$\xFF\x03\x0B]\0"
23756 /* 9404 */ "prfm $\xFF\x01\x34, [$\x02, $\x03]\0"
23757 /* 9424 */ "prfm $\xFF\x01\x34, [$\x02]\0"
23758 /* 9440 */ "prfum $\xFF\x01\x34, [$\x02]\0"
23759 /* 9457 */ "prfw $\xFF\x01\x33, $\xFF\x02\x07, [$\xFF\x03\x10]\0"
23760 /* 9481 */ "prfw $\xFF\x01\x33, $\xFF\x02\x07, [$\x03]\0"
23761 /* 9503 */ "prfw $\xFF\x01\x33, $\xFF\x02\x07, [$\xFF\x03\x0B]\0"
23762 /* 9527 */ "ptrues $\xFF\x01\x06\0"
23763 /* 9539 */ "ptrues $\xFF\x01\x10\0"
23764 /* 9551 */ "ptrues $\xFF\x01\x09\0"
23765 /* 9563 */ "ptrues $\xFF\x01\x0B\0"
23766 /* 9575 */ "ptrue $\xFF\x01\x06\0"
23767 /* 9586 */ "ptrue $\xFF\x01\x10\0"
23768 /* 9597 */ "ptrue $\xFF\x01\x09\0"
23769 /* 9608 */ "ptrue $\xFF\x01\x0B\0"
23770 /* 9619 */ "ret\0"
23771 /* 9623 */ "ngcs $\x01, $\x03\0"
23772 /* 9635 */ "ngc $\x01, $\x03\0"
23773 /* 9646 */ "asr $\x01, $\x02, $\x03\0"
23774 /* 9661 */ "sxtb $\x01, $\x02\0"
23775 /* 9673 */ "sxth $\x01, $\x02\0"
23776 /* 9685 */ "sxtw $\x01, $\x02\0"
23777 /* 9697 */ "mov $\xFF\x01\x06, $\xFF\x02\x07/m, $\xFF\x03\x06\0"
23778 /* 9720 */ "mov $\xFF\x01\x10, $\xFF\x02\x07/m, $\xFF\x03\x10\0"
23779 /* 9743 */ "mov $\xFF\x01\x09, $\xFF\x02\x07/m, $\xFF\x03\x09\0"
23780 /* 9766 */ "mov $\xFF\x01\x0B, $\xFF\x02\x07/m, $\xFF\x03\x0B\0"
23781 /* 9789 */ "smull $\x01, $\x02, $\x03\0"
23782 /* 9806 */ "smnegl $\x01, $\x02, $\x03\0"
23783 /* 9824 */ "sqdecb $\x01\0"
23784 /* 9834 */ "sqdecb $\x01, $\xFF\x03\x0E\0"
23785 /* 9850 */ "sqdecb $\x01, $\xFF\x02\x35\0"
23786 /* 9866 */ "sqdecb $\x01, $\xFF\x02\x35, $\xFF\x03\x0E\0"
23787 /* 9888 */ "sqdecd $\x01\0"
23788 /* 9898 */ "sqdecd $\x01, $\xFF\x03\x0E\0"
23789 /* 9914 */ "sqdecd $\x01, $\xFF\x02\x35\0"
23790 /* 9930 */ "sqdecd $\x01, $\xFF\x02\x35, $\xFF\x03\x0E\0"
23791 /* 9952 */ "sqdecd $\xFF\x01\x10\0"
23792 /* 9964 */ "sqdecd $\xFF\x01\x10, $\xFF\x03\x0E\0"
23793 /* 9982 */ "sqdech $\x01\0"
23794 /* 9992 */ "sqdech $\x01, $\xFF\x03\x0E\0"
23795 /* 10008 */ "sqdech $\x01, $\xFF\x02\x35\0"
23796 /* 10024 */ "sqdech $\x01, $\xFF\x02\x35, $\xFF\x03\x0E\0"
23797 /* 10046 */ "sqdech $\xFF\x01\x09\0"
23798 /* 10058 */ "sqdech $\xFF\x01\x09, $\xFF\x03\x0E\0"
23799 /* 10076 */ "sqdecw $\x01\0"
23800 /* 10086 */ "sqdecw $\x01, $\xFF\x03\x0E\0"
23801 /* 10102 */ "sqdecw $\x01, $\xFF\x02\x35\0"
23802 /* 10118 */ "sqdecw $\x01, $\xFF\x02\x35, $\xFF\x03\x0E\0"
23803 /* 10140 */ "sqdecw $\xFF\x01\x0B\0"
23804 /* 10152 */ "sqdecw $\xFF\x01\x0B, $\xFF\x03\x0E\0"
23805 /* 10170 */ "sqincb $\x01\0"
23806 /* 10180 */ "sqincb $\x01, $\xFF\x03\x0E\0"
23807 /* 10196 */ "sqincb $\x01, $\xFF\x02\x35\0"
23808 /* 10212 */ "sqincb $\x01, $\xFF\x02\x35, $\xFF\x03\x0E\0"
23809 /* 10234 */ "sqincd $\x01\0"
23810 /* 10244 */ "sqincd $\x01, $\xFF\x03\x0E\0"
23811 /* 10260 */ "sqincd $\x01, $\xFF\x02\x35\0"
23812 /* 10276 */ "sqincd $\x01, $\xFF\x02\x35, $\xFF\x03\x0E\0"
23813 /* 10298 */ "sqincd $\xFF\x01\x10\0"
23814 /* 10310 */ "sqincd $\xFF\x01\x10, $\xFF\x03\x0E\0"
23815 /* 10328 */ "sqinch $\x01\0"
23816 /* 10338 */ "sqinch $\x01, $\xFF\x03\x0E\0"
23817 /* 10354 */ "sqinch $\x01, $\xFF\x02\x35\0"
23818 /* 10370 */ "sqinch $\x01, $\xFF\x02\x35, $\xFF\x03\x0E\0"
23819 /* 10392 */ "sqinch $\xFF\x01\x09\0"
23820 /* 10404 */ "sqinch $\xFF\x01\x09, $\xFF\x03\x0E\0"
23821 /* 10422 */ "sqincw $\x01\0"
23822 /* 10432 */ "sqincw $\x01, $\xFF\x03\x0E\0"
23823 /* 10448 */ "sqincw $\x01, $\xFF\x02\x35\0"
23824 /* 10464 */ "sqincw $\x01, $\xFF\x02\x35, $\xFF\x03\x0E\0"
23825 /* 10486 */ "sqincw $\xFF\x01\x0B\0"
23826 /* 10498 */ "sqincw $\xFF\x01\x0B, $\xFF\x03\x0E\0"
23827 /* 10516 */ "st1b $\xFF\x01\x20, $\xFF\x02\x07, [$\xFF\x03\x10]\0"
23828 /* 10540 */ "st1b $\xFF\x01\x21, $\xFF\x02\x07, [$\xFF\x03\x0B]\0"
23829 /* 10564 */ "st1d $\xFF\x01\x20, $\xFF\x02\x07, [$\xFF\x03\x10]\0"
23830 /* 10588 */ "st1h $\xFF\x01\x20, $\xFF\x02\x07, [$\xFF\x03\x10]\0"
23831 /* 10612 */ "st1h $\xFF\x01\x21, $\xFF\x02\x07, [$\xFF\x03\x0B]\0"
23832 /* 10636 */ "st1w $\xFF\x01\x20, $\xFF\x02\x07, [$\xFF\x03\x10]\0"
23833 /* 10660 */ "st1w $\xFF\x01\x21, $\xFF\x02\x07, [$\xFF\x03\x0B]\0"
23834 /* 10684 */ "st1b $\xFF\x01\x20, $\xFF\x02\x07, [$\x03]\0"
23835 /* 10706 */ "st1b $\xFF\x01\x24, $\xFF\x02\x07, [$\x03]\0"
23836 /* 10728 */ "st1b $\xFF\x01\x25, $\xFF\x02\x07, [$\x03]\0"
23837 /* 10750 */ "st1b $\xFF\x01\x21, $\xFF\x02\x07, [$\x03]\0"
23838 /* 10772 */ "st1d $\xFF\x01\x20, $\xFF\x02\x07, [$\x03]\0"
23839 /* 10794 */ "st1 $\xFF\x02\x26, [$\x01], #64\0"
23840 /* 10814 */ "st1 $\xFF\x02\x27, [$\x01], #32\0"
23841 /* 10834 */ "st1 $\xFF\x02\x28, [$\x01], #64\0"
23842 /* 10854 */ "st1 $\xFF\x02\x29, [$\x01], #32\0"
23843 /* 10874 */ "st1 $\xFF\x02\x2A, [$\x01], #32\0"
23844 /* 10894 */ "st1 $\xFF\x02\x2B, [$\x01], #64\0"
23845 /* 10914 */ "st1 $\xFF\x02\x2C, [$\x01], #32\0"
23846 /* 10934 */ "st1 $\xFF\x02\x2D, [$\x01], #64\0"
23847 /* 10954 */ "st1h $\xFF\x01\x20, $\xFF\x02\x07, [$\x03]\0"
23848 /* 10976 */ "st1h $\xFF\x01\x24, $\xFF\x02\x07, [$\x03]\0"
23849 /* 10998 */ "st1h $\xFF\x01\x21, $\xFF\x02\x07, [$\x03]\0"
23850 /* 11020 */ "st1 $\xFF\x02\x26, [$\x01], #16\0"
23851 /* 11040 */ "st1 $\xFF\x02\x27, [$\x01], #8\0"
23852 /* 11059 */ "st1 $\xFF\x02\x28, [$\x01], #16\0"
23853 /* 11079 */ "st1 $\xFF\x02\x29, [$\x01], #8\0"
23854 /* 11098 */ "st1 $\xFF\x02\x2A, [$\x01], #8\0"
23855 /* 11117 */ "st1 $\xFF\x02\x2B, [$\x01], #16\0"
23856 /* 11137 */ "st1 $\xFF\x02\x2C, [$\x01], #8\0"
23857 /* 11156 */ "st1 $\xFF\x02\x2D, [$\x01], #16\0"
23858 /* 11176 */ "st1 $\xFF\x02\x26, [$\x01], #48\0"
23859 /* 11196 */ "st1 $\xFF\x02\x27, [$\x01], #24\0"
23860 /* 11216 */ "st1 $\xFF\x02\x28, [$\x01], #48\0"
23861 /* 11236 */ "st1 $\xFF\x02\x29, [$\x01], #24\0"
23862 /* 11256 */ "st1 $\xFF\x02\x2A, [$\x01], #24\0"
23863 /* 11276 */ "st1 $\xFF\x02\x2B, [$\x01], #48\0"
23864 /* 11296 */ "st1 $\xFF\x02\x2C, [$\x01], #24\0"
23865 /* 11316 */ "st1 $\xFF\x02\x2D, [$\x01], #48\0"
23866 /* 11336 */ "st1 $\xFF\x02\x26, [$\x01], #32\0"
23867 /* 11356 */ "st1 $\xFF\x02\x27, [$\x01], #16\0"
23868 /* 11376 */ "st1 $\xFF\x02\x28, [$\x01], #32\0"
23869 /* 11396 */ "st1 $\xFF\x02\x29, [$\x01], #16\0"
23870 /* 11416 */ "st1 $\xFF\x02\x2A, [$\x01], #16\0"
23871 /* 11436 */ "st1 $\xFF\x02\x2B, [$\x01], #32\0"
23872 /* 11456 */ "st1 $\xFF\x02\x2C, [$\x01], #16\0"
23873 /* 11476 */ "st1 $\xFF\x02\x2D, [$\x01], #32\0"
23874 /* 11496 */ "st1w $\xFF\x01\x20, $\xFF\x02\x07, [$\x03]\0"
23875 /* 11518 */ "st1w $\xFF\x01\x21, $\xFF\x02\x07, [$\x03]\0"
23876 /* 11540 */ "st1 $\xFF\x02\x2E$\xFF\x03\x19, [$\x01], #2\0"
23877 /* 11563 */ "st1 $\xFF\x02\x2F$\xFF\x03\x19, [$\x01], #4\0"
23878 /* 11586 */ "st1 $\xFF\x02\x30$\xFF\x03\x19, [$\x01], #8\0"
23879 /* 11609 */ "st1 $\xFF\x02\x31$\xFF\x03\x19, [$\x01], #1\0"
23880 /* 11632 */ "st2b $\xFF\x01\x25, $\xFF\x02\x07, [$\x03]\0"
23881 /* 11654 */ "st2d $\xFF\x01\x20, $\xFF\x02\x07, [$\x03]\0"
23882 /* 11676 */ "st2g $\x01, [$\x02]\0"
23883 /* 11690 */ "st2h $\xFF\x01\x24, $\xFF\x02\x07, [$\x03]\0"
23884 /* 11712 */ "st2 $\xFF\x02\x26, [$\x01], #32\0"
23885 /* 11732 */ "st2 $\xFF\x02\x28, [$\x01], #32\0"
23886 /* 11752 */ "st2 $\xFF\x02\x29, [$\x01], #16\0"
23887 /* 11772 */ "st2 $\xFF\x02\x2A, [$\x01], #16\0"
23888 /* 11792 */ "st2 $\xFF\x02\x2B, [$\x01], #32\0"
23889 /* 11812 */ "st2 $\xFF\x02\x2C, [$\x01], #16\0"
23890 /* 11832 */ "st2 $\xFF\x02\x2D, [$\x01], #32\0"
23891 /* 11852 */ "st2w $\xFF\x01\x21, $\xFF\x02\x07, [$\x03]\0"
23892 /* 11874 */ "st2 $\xFF\x02\x2E$\xFF\x03\x19, [$\x01], #4\0"
23893 /* 11897 */ "st2 $\xFF\x02\x2F$\xFF\x03\x19, [$\x01], #8\0"
23894 /* 11920 */ "st2 $\xFF\x02\x30$\xFF\x03\x19, [$\x01], #16\0"
23895 /* 11944 */ "st2 $\xFF\x02\x31$\xFF\x03\x19, [$\x01], #2\0"
23896 /* 11967 */ "st3b $\xFF\x01\x25, $\xFF\x02\x07, [$\x03]\0"
23897 /* 11989 */ "st3d $\xFF\x01\x20, $\xFF\x02\x07, [$\x03]\0"
23898 /* 12011 */ "st3h $\xFF\x01\x24, $\xFF\x02\x07, [$\x03]\0"
23899 /* 12033 */ "st3 $\xFF\x02\x26, [$\x01], #48\0"
23900 /* 12053 */ "st3 $\xFF\x02\x28, [$\x01], #48\0"
23901 /* 12073 */ "st3 $\xFF\x02\x29, [$\x01], #24\0"
23902 /* 12093 */ "st3 $\xFF\x02\x2A, [$\x01], #24\0"
23903 /* 12113 */ "st3 $\xFF\x02\x2B, [$\x01], #48\0"
23904 /* 12133 */ "st3 $\xFF\x02\x2C, [$\x01], #24\0"
23905 /* 12153 */ "st3 $\xFF\x02\x2D, [$\x01], #48\0"
23906 /* 12173 */ "st3w $\xFF\x01\x21, $\xFF\x02\x07, [$\x03]\0"
23907 /* 12195 */ "st3 $\xFF\x02\x2E$\xFF\x03\x19, [$\x01], #6\0"
23908 /* 12218 */ "st3 $\xFF\x02\x2F$\xFF\x03\x19, [$\x01], #12\0"
23909 /* 12242 */ "st3 $\xFF\x02\x30$\xFF\x03\x19, [$\x01], #24\0"
23910 /* 12266 */ "st3 $\xFF\x02\x31$\xFF\x03\x19, [$\x01], #3\0"
23911 /* 12289 */ "st4b $\xFF\x01\x25, $\xFF\x02\x07, [$\x03]\0"
23912 /* 12311 */ "st4d $\xFF\x01\x20, $\xFF\x02\x07, [$\x03]\0"
23913 /* 12333 */ "st4 $\xFF\x02\x26, [$\x01], #64\0"
23914 /* 12353 */ "st4 $\xFF\x02\x28, [$\x01], #64\0"
23915 /* 12373 */ "st4 $\xFF\x02\x29, [$\x01], #32\0"
23916 /* 12393 */ "st4 $\xFF\x02\x2A, [$\x01], #32\0"
23917 /* 12413 */ "st4 $\xFF\x02\x2B, [$\x01], #64\0"
23918 /* 12433 */ "st4 $\xFF\x02\x2C, [$\x01], #32\0"
23919 /* 12453 */ "st4 $\xFF\x02\x2D, [$\x01], #64\0"
23920 /* 12473 */ "st4h $\xFF\x01\x24, $\xFF\x02\x07, [$\x03]\0"
23921 /* 12495 */ "st4w $\xFF\x01\x21, $\xFF\x02\x07, [$\x03]\0"
23922 /* 12517 */ "st4 $\xFF\x02\x2E$\xFF\x03\x19, [$\x01], #8\0"
23923 /* 12540 */ "st4 $\xFF\x02\x2F$\xFF\x03\x19, [$\x01], #16\0"
23924 /* 12564 */ "st4 $\xFF\x02\x30$\xFF\x03\x19, [$\x01], #32\0"
23925 /* 12588 */ "st4 $\xFF\x02\x31$\xFF\x03\x19, [$\x01], #4\0"
23926 /* 12611 */ "stg $\x01, [$\x02]\0"
23927 /* 12624 */ "stgp $\x01, $\x02, [$\x03]\0"
23928 /* 12642 */ "stlurb $\x01, [$\x02]\0"
23929 /* 12658 */ "stlurh $\x01, [$\x02]\0"
23930 /* 12674 */ "stlur $\x01, [$\x02]\0"
23931 /* 12689 */ "stnp $\x01, $\x02, [$\x03]\0"
23932 /* 12707 */ "stnt1b $\xFF\x01\x25, $\xFF\x02\x07, [$\x03]\0"
23933 /* 12731 */ "stnt1b $\xFF\x01\x20, $\xFF\x02\x07, [$\xFF\x03\x10]\0"
23934 /* 12757 */ "stnt1b $\xFF\x01\x21, $\xFF\x02\x07, [$\xFF\x03\x0B]\0"
23935 /* 12783 */ "stnt1d $\xFF\x01\x20, $\xFF\x02\x07, [$\x03]\0"
23936 /* 12807 */ "stnt1d $\xFF\x01\x20, $\xFF\x02\x07, [$\xFF\x03\x10]\0"
23937 /* 12833 */ "stnt1h $\xFF\x01\x24, $\xFF\x02\x07, [$\x03]\0"
23938 /* 12857 */ "stnt1h $\xFF\x01\x20, $\xFF\x02\x07, [$\xFF\x03\x10]\0"
23939 /* 12883 */ "stnt1h $\xFF\x01\x21, $\xFF\x02\x07, [$\xFF\x03\x0B]\0"
23940 /* 12909 */ "stnt1w $\xFF\x01\x21, $\xFF\x02\x07, [$\x03]\0"
23941 /* 12933 */ "stnt1w $\xFF\x01\x20, $\xFF\x02\x07, [$\xFF\x03\x10]\0"
23942 /* 12959 */ "stnt1w $\xFF\x01\x21, $\xFF\x02\x07, [$\xFF\x03\x0B]\0"
23943 /* 12985 */ "stp $\x01, $\x02, [$\x03]\0"
23944 /* 13002 */ "strb $\x01, [$\x02, $\x03]\0"
23945 /* 13020 */ "strb $\x01, [$\x02]\0"
23946 /* 13034 */ "str $\x01, [$\x02, $\x03]\0"
23947 /* 13051 */ "str $\x01, [$\x02]\0"
23948 /* 13064 */ "strh $\x01, [$\x02, $\x03]\0"
23949 /* 13082 */ "strh $\x01, [$\x02]\0"
23950 /* 13096 */ "str $\xFF\x01\x07, [$\x02]\0"
23951 /* 13111 */ "sttrb $\x01, [$\x02]\0"
23952 /* 13126 */ "sttrh $\x01, [$\x02]\0"
23953 /* 13141 */ "sttr $\x01, [$\x02]\0"
23954 /* 13155 */ "sturb $\x01, [$\x02]\0"
23955 /* 13170 */ "stur $\x01, [$\x02]\0"
23956 /* 13184 */ "sturh $\x01, [$\x02]\0"
23957 /* 13199 */ "stz2g $\x01, [$\x02]\0"
23958 /* 13214 */ "stzg $\x01, [$\x02]\0"
23959 /* 13228 */ "cmp $\x02, $\xFF\x03\x01\0"
23960 /* 13241 */ "cmp $\x02, $\x03\0"
23961 /* 13252 */ "cmp $\x02, $\x03$\xFF\x04\x02\0"
23962 /* 13267 */ "negs $\x01, $\x03\0"
23963 /* 13279 */ "negs $\x01, $\x03$\xFF\x04\x02\0"
23964 /* 13295 */ "subs $\x01, $\x02, $\x03\0"
23965 /* 13311 */ "cmp $\x02, $\x03$\xFF\x04\x03\0"
23966 /* 13326 */ "neg $\x01, $\x03\0"
23967 /* 13337 */ "neg $\x01, $\x03$\xFF\x04\x02\0"
23968 /* 13352 */ "sub $\x01, $\x02, $\x03\0"
23969 /* 13367 */ "sys $\x01, $\xFF\x02\x36, $\xFF\x03\x36, $\x04\0"
23970 /* 13390 */ "lsr $\x01, $\x02, $\x03\0"
23971 /* 13405 */ "uxtb $\x01, $\x02\0"
23972 /* 13417 */ "uxth $\x01, $\x02\0"
23973 /* 13429 */ "uxtw $\x01, $\x02\0"
23974 /* 13441 */ "umull $\x01, $\x02, $\x03\0"
23975 /* 13458 */ "mov $\x01, $\xFF\x02\x0C.s$\xFF\x03\x19\0"
23976 /* 13477 */ "mov $\x01, $\xFF\x02\x0C.d$\xFF\x03\x19\0"
23977 /* 13496 */ "umnegl $\x01, $\x02, $\x03\0"
23978 /* 13514 */ "uqdecb $\x01\0"
23979 /* 13524 */ "uqdecb $\x01, $\xFF\x03\x0E\0"
23980 /* 13540 */ "uqdecd $\x01\0"
23981 /* 13550 */ "uqdecd $\x01, $\xFF\x03\x0E\0"
23982 /* 13566 */ "uqdecd $\xFF\x01\x10\0"
23983 /* 13578 */ "uqdecd $\xFF\x01\x10, $\xFF\x03\x0E\0"
23984 /* 13596 */ "uqdech $\x01\0"
23985 /* 13606 */ "uqdech $\x01, $\xFF\x03\x0E\0"
23986 /* 13622 */ "uqdech $\xFF\x01\x09\0"
23987 /* 13634 */ "uqdech $\xFF\x01\x09, $\xFF\x03\x0E\0"
23988 /* 13652 */ "uqdecw $\x01\0"
23989 /* 13662 */ "uqdecw $\x01, $\xFF\x03\x0E\0"
23990 /* 13678 */ "uqdecw $\xFF\x01\x0B\0"
23991 /* 13690 */ "uqdecw $\xFF\x01\x0B, $\xFF\x03\x0E\0"
23992 /* 13708 */ "uqincb $\x01\0"
23993 /* 13718 */ "uqincb $\x01, $\xFF\x03\x0E\0"
23994 /* 13734 */ "uqincd $\x01\0"
23995 /* 13744 */ "uqincd $\x01, $\xFF\x03\x0E\0"
23996 /* 13760 */ "uqincd $\xFF\x01\x10\0"
23997 /* 13772 */ "uqincd $\xFF\x01\x10, $\xFF\x03\x0E\0"
23998 /* 13790 */ "uqinch $\x01\0"
23999 /* 13800 */ "uqinch $\x01, $\xFF\x03\x0E\0"
24000 /* 13816 */ "uqinch $\xFF\x01\x09\0"
24001 /* 13828 */ "uqinch $\xFF\x01\x09, $\xFF\x03\x0E\0"
24002 /* 13846 */ "uqincw $\x01\0"
24003 /* 13856 */ "uqincw $\x01, $\xFF\x03\x0E\0"
24004 /* 13872 */ "uqincw $\xFF\x01\x0B\0"
24005 /* 13884 */ "uqincw $\xFF\x01\x0B, $\xFF\x03\x0E\0"
24006 /* 13902 */ "xpaclri\0"
24007 ;
24008
24009#ifndef NDEBUG
24010 static struct SortCheck {
24011 SortCheck(ArrayRef<PatternsForOpcode> OpToPatterns) {
24012 assert(std::is_sorted(
24013 OpToPatterns.begin(), OpToPatterns.end(),
24014 [](const PatternsForOpcode &L, const PatternsForOpcode &R) {
24015 return L.Opcode < R.Opcode;
24016 }) &&
24017 "tablegen failed to sort opcode patterns");
24018 }
24019 } sortCheckVar(OpToPatterns);
24020#endif
24021
24022 AliasMatchingData M {
24023 makeArrayRef(OpToPatterns),
24024 makeArrayRef(Patterns),
24025 makeArrayRef(Conds),
24026 StringRef(AsmStrings, array_lengthof(AsmStrings)),
24027 &AArch64InstPrinterValidateMCOperand,
24028 };
24029 const char *AsmString = matchAliasPatterns(MI, &STI, M);
24030 if (!AsmString) return false;
24031
24032 unsigned I = 0;
24033 while (AsmString[I] != ' ' && AsmString[I] != '\t' &&
24034 AsmString[I] != '$' && AsmString[I] != '\0')
24035 ++I;
24036 OS << '\t' << StringRef(AsmString, I);
24037 if (AsmString[I] != '\0') {
24038 if (AsmString[I] == ' ' || AsmString[I] == '\t') {
24039 OS << '\t';
24040 ++I;
24041 }
24042 do {
24043 if (AsmString[I] == '$') {
24044 ++I;
24045 if (AsmString[I] == (char)0xff) {
24046 ++I;
24047 int OpIdx = AsmString[I++] - 1;
24048 int PrintMethodIdx = AsmString[I++] - 1;
24049 printCustomAliasOperand(MI, Address, OpIdx, PrintMethodIdx, STI, OS);
24050 } else
24051 printOperand(MI, unsigned(AsmString[I++]) - 1, STI, OS);
24052 } else {
24053 OS << AsmString[I++];
24054 }
24055 } while (AsmString[I] != '\0');
24056 }
24057
24058 return true;
24059}
24060
24061void AArch64InstPrinter::printCustomAliasOperand(
24062 const MCInst *MI, uint64_t Address, unsigned OpIdx,
24063 unsigned PrintMethodIdx,
24064 const MCSubtargetInfo &STI,
24065 raw_ostream &OS) {
24066 switch (PrintMethodIdx) {
24067 default:
24068 llvm_unreachable("Unknown PrintMethod kind");
24069 break;
24070 case 0:
24071 printAddSubImm(MI, OpIdx, STI, OS);
24072 break;
24073 case 1:
24074 printShifter(MI, OpIdx, STI, OS);
24075 break;
24076 case 2:
24077 printArithExtend(MI, OpIdx, STI, OS);
24078 break;
24079 case 3:
24080 printLogicalImm<int32_t>(MI, OpIdx, STI, OS);
24081 break;
24082 case 4:
24083 printLogicalImm<int64_t>(MI, OpIdx, STI, OS);
24084 break;
24085 case 5:
24086 printSVERegOp<'b'>(MI, OpIdx, STI, OS);
24087 break;
24088 case 6:
24089 printSVERegOp<>(MI, OpIdx, STI, OS);
24090 break;
24091 case 7:
24092 printLogicalImm<int8_t>(MI, OpIdx, STI, OS);
24093 break;
24094 case 8:
24095 printSVERegOp<'h'>(MI, OpIdx, STI, OS);
24096 break;
24097 case 9:
24098 printLogicalImm<int16_t>(MI, OpIdx, STI, OS);
24099 break;
24100 case 10:
24101 printSVERegOp<'s'>(MI, OpIdx, STI, OS);
24102 break;
24103 case 11:
24104 printVRegOperand(MI, OpIdx, STI, OS);
24105 break;
24106 case 12:
24107 printImm(MI, OpIdx, STI, OS);
24108 break;
24109 case 13:
24110 printSVEPattern(MI, OpIdx, STI, OS);
24111 break;
24112 case 14:
24113 printImm8OptLsl<int8_t>(MI, OpIdx, STI, OS);
24114 break;
24115 case 15:
24116 printSVERegOp<'d'>(MI, OpIdx, STI, OS);
24117 break;
24118 case 16:
24119 printImm8OptLsl<int64_t>(MI, OpIdx, STI, OS);
24120 break;
24121 case 17:
24122 printImm8OptLsl<int16_t>(MI, OpIdx, STI, OS);
24123 break;
24124 case 18:
24125 printImm8OptLsl<int32_t>(MI, OpIdx, STI, OS);
24126 break;
24127 case 19:
24128 printInverseCondCode(MI, OpIdx, STI, OS);
24129 break;
24130 case 20:
24131 printSVELogicalImm<int16_t>(MI, OpIdx, STI, OS);
24132 break;
24133 case 21:
24134 printSVELogicalImm<int32_t>(MI, OpIdx, STI, OS);
24135 break;
24136 case 22:
24137 printSVELogicalImm<int64_t>(MI, OpIdx, STI, OS);
24138 break;
24139 case 23:
24140 printZPRasFPR<8>(MI, OpIdx, STI, OS);
24141 break;
24142 case 24:
24143 printVectorIndex(MI, OpIdx, STI, OS);
24144 break;
24145 case 25:
24146 printZPRasFPR<64>(MI, OpIdx, STI, OS);
24147 break;
24148 case 26:
24149 printZPRasFPR<16>(MI, OpIdx, STI, OS);
24150 break;
24151 case 27:
24152 printSVERegOp<'q'>(MI, OpIdx, STI, OS);
24153 break;
24154 case 28:
24155 printZPRasFPR<128>(MI, OpIdx, STI, OS);
24156 break;
24157 case 29:
24158 printZPRasFPR<32>(MI, OpIdx, STI, OS);
24159 break;
24160 case 30:
24161 printFPImmOperand(MI, OpIdx, STI, OS);
24162 break;
24163 case 31:
24164 printTypedVectorList<0,'d'>(MI, OpIdx, STI, OS);
24165 break;
24166 case 32:
24167 printTypedVectorList<0,'s'>(MI, OpIdx, STI, OS);
24168 break;
24169 case 33:
24170 printBTIHintOp(MI, OpIdx, STI, OS);
24171 break;
24172 case 34:
24173 printPSBHintOp(MI, OpIdx, STI, OS);
24174 break;
24175 case 35:
24176 printTypedVectorList<0,'h'>(MI, OpIdx, STI, OS);
24177 break;
24178 case 36:
24179 printTypedVectorList<0,'b'>(MI, OpIdx, STI, OS);
24180 break;
24181 case 37:
24182 printTypedVectorList<16, 'b'>(MI, OpIdx, STI, OS);
24183 break;
24184 case 38:
24185 printTypedVectorList<1, 'd'>(MI, OpIdx, STI, OS);
24186 break;
24187 case 39:
24188 printTypedVectorList<2, 'd'>(MI, OpIdx, STI, OS);
24189 break;
24190 case 40:
24191 printTypedVectorList<2, 's'>(MI, OpIdx, STI, OS);
24192 break;
24193 case 41:
24194 printTypedVectorList<4, 'h'>(MI, OpIdx, STI, OS);
24195 break;
24196 case 42:
24197 printTypedVectorList<4, 's'>(MI, OpIdx, STI, OS);
24198 break;
24199 case 43:
24200 printTypedVectorList<8, 'b'>(MI, OpIdx, STI, OS);
24201 break;
24202 case 44:
24203 printTypedVectorList<8, 'h'>(MI, OpIdx, STI, OS);
24204 break;
24205 case 45:
24206 printTypedVectorList<0, 'h'>(MI, OpIdx, STI, OS);
24207 break;
24208 case 46:
24209 printTypedVectorList<0, 's'>(MI, OpIdx, STI, OS);
24210 break;
24211 case 47:
24212 printTypedVectorList<0, 'd'>(MI, OpIdx, STI, OS);
24213 break;
24214 case 48:
24215 printTypedVectorList<0, 'b'>(MI, OpIdx, STI, OS);
24216 break;
24217 case 49:
24218 printImmHex(MI, OpIdx, STI, OS);
24219 break;
24220 case 50:
24221 printPrefetchOp<true>(MI, OpIdx, STI, OS);
24222 break;
24223 case 51:
24224 printPrefetchOp(MI, OpIdx, STI, OS);
24225 break;
24226 case 52:
24227 printGPR64as32(MI, OpIdx, STI, OS);
24228 break;
24229 case 53:
24230 printSysCROperand(MI, OpIdx, STI, OS);
24231 break;
24232 }
24233}
24234
24235static bool AArch64InstPrinterValidateMCOperand(const MCOperand &MCOp,
24236 const MCSubtargetInfo &STI,
24237 unsigned PredicateIndex) {
24238 switch (PredicateIndex) {
24239 default:
24240 llvm_unreachable("Unknown MCOperandPredicate kind");
24241 break;
24242 case 1: {
24243
24244 if (!MCOp.isImm())
24245 return false;
24246 int64_t Val = AArch64_AM::decodeLogicalImmediate(MCOp.getImm(), 64);
24247 return AArch64_AM::isSVEMaskOfIdenticalElements<int8_t>(Val);
24248
24249 }
24250 case 2: {
24251
24252 if (!MCOp.isImm())
24253 return false;
24254 int64_t Val = AArch64_AM::decodeLogicalImmediate(MCOp.getImm(), 64);
24255 return AArch64_AM::isSVEMaskOfIdenticalElements<int16_t>(Val);
24256
24257 }
24258 case 3: {
24259
24260 if (!MCOp.isImm())
24261 return false;
24262 int64_t Val = AArch64_AM::decodeLogicalImmediate(MCOp.getImm(), 64);
24263 return AArch64_AM::isSVEMaskOfIdenticalElements<int32_t>(Val);
24264
24265 }
24266 case 4: {
24267
24268 return MCOp.isImm() &&
24269 MCOp.getImm() != AArch64CC::AL &&
24270 MCOp.getImm() != AArch64CC::NV;
24271
24272 }
24273 case 5: {
24274
24275 if (!MCOp.isImm())
24276 return false;
24277 int64_t Val = AArch64_AM::decodeLogicalImmediate(MCOp.getImm(), 64);
24278 return AArch64_AM::isSVEMaskOfIdenticalElements<int16_t>(Val) &&
24279 AArch64_AM::isSVEMoveMaskPreferredLogicalImmediate(Val);
24280
24281 }
24282 case 6: {
24283
24284 if (!MCOp.isImm())
24285 return false;
24286 int64_t Val = AArch64_AM::decodeLogicalImmediate(MCOp.getImm(), 64);
24287 return AArch64_AM::isSVEMaskOfIdenticalElements<int32_t>(Val) &&
24288 AArch64_AM::isSVEMoveMaskPreferredLogicalImmediate(Val);
24289
24290 }
24291 case 7: {
24292
24293 if (!MCOp.isImm())
24294 return false;
24295 int64_t Val = AArch64_AM::decodeLogicalImmediate(MCOp.getImm(), 64);
24296 return AArch64_AM::isSVEMaskOfIdenticalElements<int64_t>(Val) &&
24297 AArch64_AM::isSVEMoveMaskPreferredLogicalImmediate(Val);
24298
24299 }
24300 case 8: {
24301
24302 // "bti" is an alias to "hint" only for certain values of CRm:Op2 fields.
24303 if (!MCOp.isImm())
24304 return false;
24305 return AArch64BTIHint::lookupBTIByEncoding((MCOp.getImm() ^ 32) >> 1) != nullptr;
24306
24307 }
24308 case 9: {
24309
24310 // Check, if operand is valid, to fix exhaustive aliasing in disassembly.
24311 // "psb" is an alias to "hint" only for certain values of CRm:Op2 fields.
24312 if (!MCOp.isImm())
24313 return false;
24314 return AArch64PSBHint::lookupPSBByEncoding(MCOp.getImm()) != nullptr;
24315
24316 }
24317 }
24318}
24319
24320#endif // PRINT_ALIAS_INSTR
24321